OV - exec - Function hypre_SeqVectorInnerProd._omp

	Function: hypre_SeqVectorInnerProd._omp_fn.0	Module: exec	Source: vector.c:483-486	Coverage: 0.65%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/vector.c: 483 - 486

--------------------------------------------------------------------------------

483: #pragma omp parallel for private(i) reduction(+:result) HYPRE_SMP_SCHEDULE

484: #endif

485:    for (i = 0; i < size; i++)

486:       result += hypre_conj(y_data[i]) * x_data[i];

0x50f92c STP	X29, X30, [SP, #976]!

0x50f930 ADD	X29, SP, #0

0x50f934 STP	X21, X22, [SP, #32]

0x50f938 LDR	X22, [X0, #16]

0x50f93c STP	X19, X20, [SP, #16]

0x50f940 ORR	X19, XZR, X0

0x50f944 BL	40f6a0

0x50f948 SBFM	X20, X0, #0, #31

0x50f94c BL	40f540

0x50f950 SDIV	X2, X22, X20

0x50f954 SBFM	X1, X0, #0, #31

0x50f958 LDP	X21, X3, [X19]

0x50f95c MSUB	X0, X2, X20, X22

0x50f960 CMP	X1, X0

0x50f964 B.LT	50faf4

(3781) 0x50f968 MADD	X11, X2, X1, X0

(3781) 0x50f96c MOVI	D0, #0

(3781) 0x50f970 ADD	X10, X2, X11

(3781) 0x50f974 CMP	X11, X10

(3781) 0x50f978 B.GE	50fac0

(3781) 0x50f97c SUB	X4, X10, X11

(3781) 0x50f980 ANDS	X5, X4, #4224

(3781) 0x50f984 B.EQ	50fa30

(3781) 0x50f988 CMP	X5, #1

(3781) 0x50f98c B.EQ	50fa18

(3781) 0x50f990 CMP	X5, #2

(3781) 0x50f994 B.EQ	50fa08

(3781) 0x50f998 CMP	X5, #3

(3781) 0x50f99c B.EQ	50f9f8

(3781) 0x50f9a0 CMP	X5, #4

(3781) 0x50f9a4 B.EQ	50f9e8

(3781) 0x50f9a8 CMP	X5, #5

(3781) 0x50f9ac B.EQ	50f9d8

(3781) 0x50f9b0 CMP	X5, #6

(3781) 0x50f9b4 B.EQ	50f9c8

(3781) 0x50f9b8 LDR	D2, [X3, X11,LSL #3]

(3781) 0x50f9bc LDR	D1, [X21, X11,LSL #3]

(3781) 0x50f9c0 ADD	X11, X11, #1

(3781) 0x50f9c4 FMADD	D0, D2, D1, D0

(3781) 0x50f9c8 LDR	D3, [X3, X11,LSL #3]

(3781) 0x50f9cc LDR	D4, [X21, X11,LSL #3]

(3781) 0x50f9d0 ADD	X11, X11, #1

(3781) 0x50f9d4 FMADD	D0, D3, D4, D0

(3781) 0x50f9d8 LDR	D5, [X3, X11,LSL #3]

(3781) 0x50f9dc LDR	D6, [X21, X11,LSL #3]

(3781) 0x50f9e0 ADD	X11, X11, #1

(3781) 0x50f9e4 FMADD	D0, D5, D6, D0

(3781) 0x50f9e8 LDR	D7, [X3, X11,LSL #3]

(3781) 0x50f9ec LDR	D16, [X21, X11,LSL #3]

(3781) 0x50f9f0 ADD	X11, X11, #1

(3781) 0x50f9f4 FMADD	D0, D7, D16, D0

(3781) 0x50f9f8 LDR	D17, [X3, X11,LSL #3]

(3781) 0x50f9fc LDR	D18, [X21, X11,LSL #3]

(3781) 0x50fa00 ADD	X11, X11, #1

(3781) 0x50fa04 FMADD	D0, D17, D18, D0

(3781) 0x50fa08 LDR	D19, [X3, X11,LSL #3]

(3781) 0x50fa0c LDR	D20, [X21, X11,LSL #3]

(3781) 0x50fa10 ADD	X11, X11, #1

(3781) 0x50fa14 FMADD	D0, D19, D20, D0

(3781) 0x50fa18 LDR	D21, [X3, X11,LSL #3]

(3781) 0x50fa1c LDR	D22, [X21, X11,LSL #3]

(3781) 0x50fa20 ADD	X11, X11, #1

(3781) 0x50fa24 FMADD	D0, D21, D22, D0

(3781) 0x50fa28 CMP	X10, X11

(3781) 0x50fa2c B.EQ	50fac0

  (3782) 0x50fa30 LDR	D23, [X3, X11,LSL #3]

  (3782) 0x50fa34 ADD	X12, X11, #1

  (3782) 0x50fa38 ADD	X9, X11, #2

  (3782) 0x50fa3c ADD	X8, X11, #3

  (3782) 0x50fa40 ADD	X7, X11, #4

  (3782) 0x50fa44 LDR	D24, [X21, X11,LSL #3]

  (3782) 0x50fa48 ADD	X6, X11, #5

  (3782) 0x50fa4c ADD	X13, X11, #6

  (3782) 0x50fa50 ADD	X14, X11, #7

  (3782) 0x50fa54 ADD	X11, X11, #8

  (3782) 0x50fa58 LDR	D25, [X3, X12,LSL #3]

  (3782) 0x50fa5c LDR	D26, [X21, X12,LSL #3]

  (3782) 0x50fa60 FMADD	D27, D23, D24, D0

  (3782) 0x50fa64 LDR	D28, [X3, X9,LSL #3]

  (3782) 0x50fa68 LDR	D29, [X21, X9,LSL #3]

  (3782) 0x50fa6c LDR	D30, [X3, X8,LSL #3]

  (3782) 0x50fa70 FMADD	D31, D25, D26, D27

  (3782) 0x50fa74 LDR	D3, [X21, X8,LSL #3]

  (3782) 0x50fa78 LDR	D2, [X3, X7,LSL #3]

  (3782) 0x50fa7c FMADD	D4, D28, D29, D31

  (3782) 0x50fa80 LDR	D1, [X21, X7,LSL #3]

  (3782) 0x50fa84 LDR	D6, [X3, X6,LSL #3]

  (3782) 0x50fa88 LDR	D5, [X21, X6,LSL #3]

  (3782) 0x50fa8c FMADD	D7, D30, D3, D4

  (3782) 0x50fa90 LDR	D16, [X3, X13,LSL #3]

  (3782) 0x50fa94 LDR	D17, [X21, X13,LSL #3]

  (3782) 0x50fa98 FMADD	D18, D2, D1, D7

  (3782) 0x50fa9c LDR	D19, [X3, X14,LSL #3]

  (3782) 0x50faa0 LDR	D20, [X21, X14,LSL #3]

  (3782) 0x50faa4 FMADD	D21, D6, D5, D18

  (3782) 0x50faa8 FMADD	D22, D16, D17, D21

  (3782) 0x50faac FMADD	D0, D19, D20, D22

  (3782) 0x50fab0 CMP	X10, X11

  (3782) 0x50fab4 B.NE	50fa30

(3781) 0x50fab8 HINT	#0

(3781) 0x50fabc HINT	#0

(3781) 0x50fac0 ADD	X17, X19, #24

(3781) 0x50fac4 LDR	X1, [X17]

  (3780) 0x50fac8 FMOV	D23, X1

  (3780) 0x50facc ORR	X16, XZR, X1

  (3780) 0x50fad0 FADD	D24, D0, D23

  (3780) 0x50fad4 FMOV	X15, D24

  (3780) 0x50fad8 CASAL	X16, X15, [X17]

  (3780) 0x50fadc CMP	X1, X16

  (3780) 0x50fae0 B.NE	50fb00

(3781) 0x50fae4 LDP	X19, X20, [SP, #16]

(3781) 0x50fae8 LDP	X21, X22, [SP, #32]

(3781) 0x50faec LDP	X29, X30, [SP], #48

(3781) 0x50faf0 RET

(3781) 0x50faf4 ADD	X2, X2, #1

(3781) 0x50faf8 MOVZ	X0, #0

(3781) 0x50fafc B	50f968

  (3780) 0x50fb00 ORR	X1, XZR, X16

  (3780) 0x50fb04 B	50fac8

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	vector.c:483-486
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/vector.c:483-486.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 20.00 to 10.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	15
loop length	60
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.83	1.50	1.67	1.50	1.50
cycles	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.83	1.50	1.67	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.88
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

1% of peak load performance is reached (1.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 50f92c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X22, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40f6a0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SBFM X20, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40f540 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SDIV X2, X22, X20	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDP X21, X3, [X19]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MSUB X0, X2, X20, X22	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 50faf4 <hypre_SeqVectorInnerProd._omp_fn.0+0x1c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	vector.c:483-486
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/vector.c:483-486.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	15
loop length	60
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.83	1.50	1.67	1.50	1.50
cycles	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.83	1.50	1.67	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.88
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

1% of peak load performance is reached (1.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 50f92c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X22, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40f6a0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SBFM X20, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40f540 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SDIV X2, X22, X20	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDP X21, X3, [X19]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MSUB X0, X2, X20, X22	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 50faf4 <hypre_SeqVectorInnerProd._omp_fn.0+0x1c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼hypre_SeqVectorInnerProd._omp_fn.0–	0.65	0.24
▼Loop 3781 - vector.c:483-486 - exec–	0	0
○Loop 3782 - vector.c:486-486 - exec	0.65	0.21
○Loop 3780 - vector.c:483-483 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code