OV - exec - Function hypre_SeqVectorAxpy._omp

	Function: hypre_SeqVectorAxpy._omp_fn.0	Module: exec	Source: vector.c:449-452	Coverage: 1.05%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/vector.c: 449 - 452

--------------------------------------------------------------------------------

449: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

450: #endif

451:    for (i = 0; i < size; i++)

452:       y_data[i] += alpha * x_data[i];

0x50f748 STP	X29, X30, [SP, #976]!

0x50f74c ADD	X29, SP, #0

0x50f750 STR	X21, [SP, #32]

0x50f754 LDR	X21, [X0, #24]

0x50f758 STP	X19, X20, [SP, #16]

0x50f75c ORR	X20, XZR, X0

0x50f760 BL	40f6a0

0x50f764 SBFM	X19, X0, #0, #31

0x50f768 BL	40f540

0x50f76c SDIV	X3, X21, X19

0x50f770 SBFM	X1, X0, #0, #31

0x50f774 MSUB	X2, X3, X19, X21

0x50f778 CMP	X1, X2

0x50f77c B.LT	50f920

(3778) 0x50f780 MADD	X13, X3, X1, X2

(3778) 0x50f784 ADD	X11, X3, X13

(3778) 0x50f788 CMP	X13, X11

(3778) 0x50f78c B.GE	50f910

(3778) 0x50f790 SUB	X4, X11, X13

(3778) 0x50f794 LDR	D0, [X20]

(3778) 0x50f798 ANDS	X5, X4, #4224

(3778) 0x50f79c LDP	X12, X0, [X20, #8]

(3778) 0x50f7a0 B.EQ	50f868

(3778) 0x50f7a4 CMP	X5, #1

(3778) 0x50f7a8 B.EQ	50f84c

(3778) 0x50f7ac CMP	X5, #2

(3778) 0x50f7b0 B.EQ	50f838

(3778) 0x50f7b4 CMP	X5, #3

(3778) 0x50f7b8 B.EQ	50f824

(3778) 0x50f7bc CMP	X5, #4

(3778) 0x50f7c0 B.EQ	50f810

(3778) 0x50f7c4 CMP	X5, #5

(3778) 0x50f7c8 B.EQ	50f7fc

(3778) 0x50f7cc CMP	X5, #6

(3778) 0x50f7d0 B.EQ	50f7e8

(3778) 0x50f7d4 LDR	D2, [X12, X13,LSL #3]

(3778) 0x50f7d8 LDR	D1, [X0, X13,LSL #3]

(3778) 0x50f7dc FMADD	D3, D0, D2, D1

(3778) 0x50f7e0 STR	D3, [X0, X13,LSL #3]

(3778) 0x50f7e4 ADD	X13, X13, #1

(3778) 0x50f7e8 LDR	D4, [X12, X13,LSL #3]

(3778) 0x50f7ec LDR	D5, [X0, X13,LSL #3]

(3778) 0x50f7f0 FMADD	D6, D0, D4, D5

(3778) 0x50f7f4 STR	D6, [X0, X13,LSL #3]

(3778) 0x50f7f8 ADD	X13, X13, #1

(3778) 0x50f7fc LDR	D7, [X12, X13,LSL #3]

(3778) 0x50f800 LDR	D16, [X0, X13,LSL #3]

(3778) 0x50f804 FMADD	D17, D0, D7, D16

(3778) 0x50f808 STR	D17, [X0, X13,LSL #3]

(3778) 0x50f80c ADD	X13, X13, #1

(3778) 0x50f810 LDR	D18, [X12, X13,LSL #3]

(3778) 0x50f814 LDR	D19, [X0, X13,LSL #3]

(3778) 0x50f818 FMADD	D20, D0, D18, D19

(3778) 0x50f81c STR	D20, [X0, X13,LSL #3]

(3778) 0x50f820 ADD	X13, X13, #1

(3778) 0x50f824 LDR	D21, [X12, X13,LSL #3]

(3778) 0x50f828 LDR	D22, [X0, X13,LSL #3]

(3778) 0x50f82c FMADD	D23, D0, D21, D22

(3778) 0x50f830 STR	D23, [X0, X13,LSL #3]

(3778) 0x50f834 ADD	X13, X13, #1

(3778) 0x50f838 LDR	D24, [X12, X13,LSL #3]

(3778) 0x50f83c LDR	D25, [X0, X13,LSL #3]

(3778) 0x50f840 FMADD	D26, D0, D24, D25

(3778) 0x50f844 STR	D26, [X0, X13,LSL #3]

(3778) 0x50f848 ADD	X13, X13, #1

(3778) 0x50f84c LDR	D27, [X12, X13,LSL #3]

(3778) 0x50f850 LDR	D28, [X0, X13,LSL #3]

(3778) 0x50f854 FMADD	D29, D0, D27, D28

(3778) 0x50f858 STR	D29, [X0, X13,LSL #3]

(3778) 0x50f85c ADD	X13, X13, #1

(3778) 0x50f860 CMP	X11, X13

(3778) 0x50f864 B.EQ	50f910

  (3779) 0x50f868 LDR	D30, [X12, X13,LSL #3]

  (3779) 0x50f86c ADD	X14, X13, #1

  (3779) 0x50f870 ADD	X10, X13, #2

  (3779) 0x50f874 ADD	X9, X13, #3

  (3779) 0x50f878 ADD	X8, X13, #4

  (3779) 0x50f87c LDR	D31, [X0, X13,LSL #3]

  (3779) 0x50f880 ADD	X7, X13, #5

  (3779) 0x50f884 ADD	X6, X13, #6

  (3779) 0x50f888 ADD	X15, X13, #7

  (3779) 0x50f88c FMADD	D2, D0, D30, D31

  (3779) 0x50f890 STR	D2, [X0, X13,LSL #3]

  (3779) 0x50f894 ADD	X13, X13, #8

  (3779) 0x50f898 LDR	D3, [X12, X14,LSL #3]

  (3779) 0x50f89c LDR	D1, [X0, X14,LSL #3]

  (3779) 0x50f8a0 FMADD	D4, D0, D3, D1

  (3779) 0x50f8a4 STR	D4, [X0, X14,LSL #3]

  (3779) 0x50f8a8 LDR	D5, [X12, X10,LSL #3]

  (3779) 0x50f8ac LDR	D6, [X0, X10,LSL #3]

  (3779) 0x50f8b0 FMADD	D7, D0, D5, D6

  (3779) 0x50f8b4 STR	D7, [X0, X10,LSL #3]

  (3779) 0x50f8b8 LDR	D16, [X12, X9,LSL #3]

  (3779) 0x50f8bc LDR	D17, [X0, X9,LSL #3]

  (3779) 0x50f8c0 FMADD	D18, D0, D16, D17

  (3779) 0x50f8c4 STR	D18, [X0, X9,LSL #3]

  (3779) 0x50f8c8 LDR	D19, [X12, X8,LSL #3]

  (3779) 0x50f8cc LDR	D20, [X0, X8,LSL #3]

  (3779) 0x50f8d0 FMADD	D21, D0, D19, D20

  (3779) 0x50f8d4 STR	D21, [X0, X8,LSL #3]

  (3779) 0x50f8d8 LDR	D22, [X12, X7,LSL #3]

  (3779) 0x50f8dc LDR	D23, [X0, X7,LSL #3]

  (3779) 0x50f8e0 FMADD	D24, D0, D22, D23

  (3779) 0x50f8e4 STR	D24, [X0, X7,LSL #3]

  (3779) 0x50f8e8 LDR	D25, [X12, X6,LSL #3]

  (3779) 0x50f8ec LDR	D26, [X0, X6,LSL #3]

  (3779) 0x50f8f0 FMADD	D27, D0, D25, D26

  (3779) 0x50f8f4 STR	D27, [X0, X6,LSL #3]

  (3779) 0x50f8f8 LDR	D28, [X12, X15,LSL #3]

  (3779) 0x50f8fc LDR	D29, [X0, X15,LSL #3]

  (3779) 0x50f900 FMADD	D30, D0, D28, D29

  (3779) 0x50f904 STR	D30, [X0, X15,LSL #3]

  (3779) 0x50f908 CMP	X11, X13

  (3779) 0x50f90c B.NE	50f868

(3778) 0x50f910 LDP	X19, X20, [SP, #16]

(3778) 0x50f914 LDR	X21, [SP, #32]

(3778) 0x50f918 LDP	X29, X30, [SP], #48

(3778) 0x50f91c RET

(3778) 0x50f920 ADD	X3, X3, #1

(3778) 0x50f924 MOVZ	X2, #0

(3778) 0x50f928 B	50f780

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	vector.c:449-452
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/vector.c:449-452.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 20.00 to 10.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 50f748

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X21, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X0, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40f6a0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40f540 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SDIV X3, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MSUB X2, X3, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP X1, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 50f920 <hypre_SeqVectorAxpy._omp_fn.0+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	vector.c:449-452
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/vector.c:449-452.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 50f748

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X21, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X0, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40f6a0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40f540 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SDIV X3, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MSUB X2, X3, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP X1, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 50f920 <hypre_SeqVectorAxpy._omp_fn.0+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼hypre_SeqVectorAxpy._omp_fn.0–	1.05	0.4
▼Loop 3778 - vector.c:449-452 - exec–	0	0
○Loop 3779 - vector.c:452-452 - exec	1.05	0.35

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code