OV - exec - Function hypre_SeqVectorScale._omp

	Function: hypre_SeqVectorScale._omp_fn.0	Module: exec	Source: vector.c:413-416	Coverage: 0.16%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/vector.c: 413 - 416

--------------------------------------------------------------------------------

413: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

414: #endif

415:    for (i = 0; i < size; i++)

416:       y_data[i] *= alpha;

0x50f5d0 STP	X29, X30, [SP, #976]!

0x50f5d4 ADD	X29, SP, #0

0x50f5d8 STR	X21, [SP, #32]

0x50f5dc LDR	X21, [X0, #16]

0x50f5e0 STP	X19, X20, [SP, #16]

0x50f5e4 ORR	X20, XZR, X0

0x50f5e8 BL	40f6a0

0x50f5ec SBFM	X19, X0, #0, #31

0x50f5f0 BL	40f540

0x50f5f4 SDIV	X2, X21, X19

0x50f5f8 SBFM	X1, X0, #0, #31

0x50f5fc MSUB	X3, X2, X19, X21

0x50f600 CMP	X1, X3

0x50f604 B.LT	50f73c

(3776) 0x50f608 MADD	X0, X2, X1, X3

(3776) 0x50f60c ADD	X4, X2, X0

(3776) 0x50f610 CMP	X0, X4

(3776) 0x50f614 B.GE	50f72c

(3776) 0x50f618 LDR	X5, [X20, #8]

(3776) 0x50f61c LDR	D0, [X20]

(3776) 0x50f620 ADD	X13, X5, X0,LSL #3

(3776) 0x50f624 ADD	X6, X5, X4,LSL #3

(3776) 0x50f628 SUB	X7, X6, X13

(3776) 0x50f62c SUB	X8, X7, #8

(3776) 0x50f630 UBFM	X9, X8, #3, #63

(3776) 0x50f634 ADD	X10, X9, #1

(3776) 0x50f638 ANDS	X11, X10, #4224

(3776) 0x50f63c B.EQ	50f6cc

(3776) 0x50f640 CMP	X11, #1

(3776) 0x50f644 B.EQ	50f6b8

(3776) 0x50f648 CMP	X11, #2

(3776) 0x50f64c B.EQ	50f6ac

(3776) 0x50f650 CMP	X11, #3

(3776) 0x50f654 B.EQ	50f6a0

(3776) 0x50f658 CMP	X11, #4

(3776) 0x50f65c B.EQ	50f694

(3776) 0x50f660 CMP	X11, #5

(3776) 0x50f664 B.EQ	50f688

(3776) 0x50f668 CMP	X11, #6

(3776) 0x50f66c B.EQ	50f67c

(3776) 0x50f670 LDR	D1, [X13]

(3776) 0x50f674 FMUL	D2, D1, D0

(3776) 0x50f678 STR	D2, [X13], #8

(3776) 0x50f67c LDR	D3, [X13]

(3776) 0x50f680 FMUL	D4, D3, D0

(3776) 0x50f684 STR	D4, [X13], #8

(3776) 0x50f688 LDR	D5, [X13]

(3776) 0x50f68c FMUL	D6, D5, D0

(3776) 0x50f690 STR	D6, [X13], #8

(3776) 0x50f694 LDR	D7, [X13]

(3776) 0x50f698 FMUL	D16, D7, D0

(3776) 0x50f69c STR	D16, [X13], #8

(3776) 0x50f6a0 LDR	D17, [X13]

(3776) 0x50f6a4 FMUL	D18, D17, D0

(3776) 0x50f6a8 STR	D18, [X13], #8

(3776) 0x50f6ac LDR	D19, [X13]

(3776) 0x50f6b0 FMUL	D20, D19, D0

(3776) 0x50f6b4 STR	D20, [X13], #8

(3776) 0x50f6b8 LDR	D21, [X13]

(3776) 0x50f6bc FMUL	D22, D21, D0

(3776) 0x50f6c0 STR	D22, [X13], #8

(3776) 0x50f6c4 CMP	X6, X13

(3776) 0x50f6c8 B.EQ	50f72c

  (3777) 0x50f6cc LDR	D23, [X13]

  (3777) 0x50f6d0 ORR	X12, XZR, X13

  (3777) 0x50f6d4 FMUL	D24, D23, D0

  (3777) 0x50f6d8 STR	D24, [X12], #8

  (3777) 0x50f6dc LDR	D25, [X13, #8]

  (3777) 0x50f6e0 FMUL	D26, D25, D0

  (3777) 0x50f6e4 STR	D26, [X13, #8]

  (3777) 0x50f6e8 LDR	D27, [X12, #8]

  (3777) 0x50f6ec FMUL	D28, D27, D0

  (3777) 0x50f6f0 STR	D28, [X12, #8]

  (3777) 0x50f6f4 LDP	D29, D30, [X13, #24]

  (3777) 0x50f6f8 LDP	D31, D2, [X13, #40]

  (3777) 0x50f6fc LDR	D1, [X13, #56]

  (3777) 0x50f700 FMUL	D5, D29, D0

  (3777) 0x50f704 FMUL	D4, D30, D0

  (3777) 0x50f708 FMUL	D3, D31, D0

  (3777) 0x50f70c FMUL	D6, D2, D0

  (3777) 0x50f710 FMUL	D7, D1, D0

  (3777) 0x50f714 STP	D5, D4, [X13, #24]

  (3777) 0x50f718 STP	D3, D6, [X13, #40]

  (3777) 0x50f71c ADD	X13, X13, #64

  (3777) 0x50f720 STUR	D7, [X13, #504]

  (3777) 0x50f724 CMP	X6, X13

  (3777) 0x50f728 B.NE	50f6cc

(3776) 0x50f72c LDP	X19, X20, [SP, #16]

(3776) 0x50f730 LDR	X21, [SP, #32]

(3776) 0x50f734 LDP	X29, X30, [SP], #48

(3776) 0x50f738 RET

(3776) 0x50f73c ADD	X2, X2, #1

(3776) 0x50f740 MOVZ	X3, #0

(3776) 0x50f744 B	50f608

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	vector.c:413-416
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/vector.c:413-416.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 20.00 to 10.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 50f5d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X21, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40f6a0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40f540 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SDIV X2, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MSUB X3, X2, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP X1, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 50f73c <hypre_SeqVectorScale._omp_fn.0+0x16c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	vector.c:413-416
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/vector.c:413-416.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 50f5d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X21, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40f6a0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40f540 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SDIV X2, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MSUB X3, X2, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP X1, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 50f73c <hypre_SeqVectorScale._omp_fn.0+0x16c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼hypre_SeqVectorScale._omp_fn.0–	0.16	0.06
▼Loop 3776 - vector.c:413-416 - exec–	0	0
○Loop 3777 - vector.c:416-416 - exec	0.16	0.05

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code