OV - exec - Function hypre_SeqVectorCopy._omp

	Function: hypre_SeqVectorCopy._omp_fn.0	Module: exec	Source: vector.c:334-337	Coverage: 0.07%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/vector.c: 334 - 337

--------------------------------------------------------------------------------

334: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

335: #endif

336:    for (i = 0; i < size; i++)

337:       y_data[i] = x_data[i];

0x50f468 STP	X29, X30, [SP, #976]!

0x50f46c ADD	X29, SP, #0

0x50f470 STR	X21, [SP, #32]

0x50f474 LDR	X21, [X0, #16]

0x50f478 STP	X19, X20, [SP, #16]

0x50f47c ORR	X20, XZR, X0

0x50f480 BL	40f6a0

0x50f484 SBFM	X19, X0, #0, #31

0x50f488 BL	40f540

0x50f48c SDIV	X3, X21, X19

0x50f490 SBFM	X1, X0, #0, #31

0x50f494 MSUB	X2, X3, X19, X21

0x50f498 CMP	X1, X2

0x50f49c B.LT	50f5c4

(3774) 0x50f4a0 MADD	X13, X3, X1, X2

(3774) 0x50f4a4 ADD	X11, X3, X13

(3774) 0x50f4a8 CMP	X13, X11

(3774) 0x50f4ac B.GE	50f5b4

(3774) 0x50f4b0 SUB	X4, X11, X13

(3774) 0x50f4b4 LDP	X12, X0, [X20]

(3774) 0x50f4b8 ANDS	X5, X4, #4224

(3774) 0x50f4bc B.EQ	50f54c

(3774) 0x50f4c0 CMP	X5, #1

(3774) 0x50f4c4 B.EQ	50f538

(3774) 0x50f4c8 CMP	X5, #2

(3774) 0x50f4cc B.EQ	50f52c

(3774) 0x50f4d0 CMP	X5, #3

(3774) 0x50f4d4 B.EQ	50f520

(3774) 0x50f4d8 CMP	X5, #4

(3774) 0x50f4dc B.EQ	50f514

(3774) 0x50f4e0 CMP	X5, #5

(3774) 0x50f4e4 B.EQ	50f508

(3774) 0x50f4e8 CMP	X5, #6

(3774) 0x50f4ec B.EQ	50f4fc

(3774) 0x50f4f0 LDR	D0, [X12, X13,LSL #3]

(3774) 0x50f4f4 STR	D0, [X0, X13,LSL #3]

(3774) 0x50f4f8 ADD	X13, X13, #1

(3774) 0x50f4fc LDR	D1, [X12, X13,LSL #3]

(3774) 0x50f500 STR	D1, [X0, X13,LSL #3]

(3774) 0x50f504 ADD	X13, X13, #1

(3774) 0x50f508 LDR	D2, [X12, X13,LSL #3]

(3774) 0x50f50c STR	D2, [X0, X13,LSL #3]

(3774) 0x50f510 ADD	X13, X13, #1

(3774) 0x50f514 LDR	D3, [X12, X13,LSL #3]

(3774) 0x50f518 STR	D3, [X0, X13,LSL #3]

(3774) 0x50f51c ADD	X13, X13, #1

(3774) 0x50f520 LDR	D4, [X12, X13,LSL #3]

(3774) 0x50f524 STR	D4, [X0, X13,LSL #3]

(3774) 0x50f528 ADD	X13, X13, #1

(3774) 0x50f52c LDR	D5, [X12, X13,LSL #3]

(3774) 0x50f530 STR	D5, [X0, X13,LSL #3]

(3774) 0x50f534 ADD	X13, X13, #1

(3774) 0x50f538 LDR	D6, [X12, X13,LSL #3]

(3774) 0x50f53c STR	D6, [X0, X13,LSL #3]

(3774) 0x50f540 ADD	X13, X13, #1

(3774) 0x50f544 CMP	X11, X13

(3774) 0x50f548 B.EQ	50f5b4

  (3775) 0x50f54c LDR	D7, [X12, X13,LSL #3]

  (3775) 0x50f550 ADD	X14, X13, #1

  (3775) 0x50f554 ADD	X10, X13, #2

  (3775) 0x50f558 ADD	X9, X13, #3

  (3775) 0x50f55c ADD	X8, X13, #4

  (3775) 0x50f560 ADD	X7, X13, #5

  (3775) 0x50f564 ADD	X6, X13, #6

  (3775) 0x50f568 ADD	X15, X13, #7

  (3775) 0x50f56c STR	D7, [X0, X13,LSL #3]

  (3775) 0x50f570 ADD	X13, X13, #8

  (3775) 0x50f574 LDR	D16, [X12, X14,LSL #3]

  (3775) 0x50f578 STR	D16, [X0, X14,LSL #3]

  (3775) 0x50f57c LDR	D17, [X12, X10,LSL #3]

  (3775) 0x50f580 STR	D17, [X0, X10,LSL #3]

  (3775) 0x50f584 LDR	D18, [X12, X9,LSL #3]

  (3775) 0x50f588 STR	D18, [X0, X9,LSL #3]

  (3775) 0x50f58c LDR	D19, [X12, X8,LSL #3]

  (3775) 0x50f590 STR	D19, [X0, X8,LSL #3]

  (3775) 0x50f594 LDR	D20, [X12, X7,LSL #3]

  (3775) 0x50f598 STR	D20, [X0, X7,LSL #3]

  (3775) 0x50f59c LDR	D21, [X12, X6,LSL #3]

  (3775) 0x50f5a0 STR	D21, [X0, X6,LSL #3]

  (3775) 0x50f5a4 LDR	D22, [X12, X15,LSL #3]

  (3775) 0x50f5a8 STR	D22, [X0, X15,LSL #3]

  (3775) 0x50f5ac CMP	X11, X13

  (3775) 0x50f5b0 B.NE	50f54c

(3774) 0x50f5b4 LDP	X19, X20, [SP, #16]

(3774) 0x50f5b8 LDR	X21, [SP, #32]

(3774) 0x50f5bc LDP	X29, X30, [SP], #48

(3774) 0x50f5c0 RET

(3774) 0x50f5c4 ADD	X3, X3, #1

(3774) 0x50f5c8 MOVZ	X2, #0

(3774) 0x50f5cc B	50f4a0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	vector.c:334-337
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/vector.c:334-337.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 20.00 to 10.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 50f468

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X21, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40f6a0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40f540 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SDIV X3, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MSUB X2, X3, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP X1, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 50f5c4 <hypre_SeqVectorCopy._omp_fn.0+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	vector.c:334-337
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/vector.c:334-337.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 50f468

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X21, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40f6a0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40f540 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SDIV X3, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MSUB X2, X3, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP X1, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 50f5c4 <hypre_SeqVectorCopy._omp_fn.0+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼hypre_SeqVectorCopy._omp_fn.0–	0.07	0.03
▼Loop 3774 - vector.c:334-337 - exec–	0	0
○Loop 3775 - vector.c:337-337 - exec	0.07	0.02

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code