OV - exec - Function hypre_SeqVectorSetConstantValues._omp

	Function: hypre_SeqVectorSetConstantValues._omp_fn.0	Module: exec	Source: vector.c:268-271	Coverage: 0.15%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/vector.c: 268 - 271

--------------------------------------------------------------------------------

268: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

269: #endif

270:    for (i = 0; i < size; i++)

271:       vector_data[i] = value;

0x50f360 STP	X29, X30, [SP, #976]!

0x50f364 ADD	X29, SP, #0

0x50f368 STR	X21, [SP, #32]

0x50f36c LDR	X21, [X0, #16]

0x50f370 STP	X19, X20, [SP, #16]

0x50f374 ORR	X20, XZR, X0

0x50f378 BL	40f6a0

0x50f37c SBFM	X19, X0, #0, #31

0x50f380 BL	40f540

0x50f384 SDIV	X2, X21, X19

0x50f388 SBFM	X1, X0, #0, #31

0x50f38c MSUB	X3, X2, X19, X21

0x50f390 CMP	X1, X3

0x50f394 B.LT	50f45c

(3772) 0x50f398 MADD	X0, X2, X1, X3

(3772) 0x50f39c ADD	X4, X2, X0

(3772) 0x50f3a0 CMP	X0, X4

(3772) 0x50f3a4 B.GE	50f44c

(3772) 0x50f3a8 LDR	X5, [X20, #8]

(3772) 0x50f3ac LDR	D0, [X20]

(3772) 0x50f3b0 ADD	X13, X5, X0,LSL #3

(3772) 0x50f3b4 ADD	X6, X5, X4,LSL #3

(3772) 0x50f3b8 SUB	X7, X6, X13

(3772) 0x50f3bc SUB	X8, X7, #8

(3772) 0x50f3c0 UBFM	X9, X8, #3, #63

(3772) 0x50f3c4 ADD	X10, X9, #1

(3772) 0x50f3c8 ANDS	X11, X10, #4224

(3772) 0x50f3cc B.EQ	50f424

(3772) 0x50f3d0 CMP	X11, #1

(3772) 0x50f3d4 B.EQ	50f418

(3772) 0x50f3d8 CMP	X11, #2

(3772) 0x50f3dc B.EQ	50f414

(3772) 0x50f3e0 CMP	X11, #3

(3772) 0x50f3e4 B.EQ	50f410

(3772) 0x50f3e8 CMP	X11, #4

(3772) 0x50f3ec B.EQ	50f40c

(3772) 0x50f3f0 CMP	X11, #5

(3772) 0x50f3f4 B.EQ	50f408

(3772) 0x50f3f8 CMP	X11, #6

(3772) 0x50f3fc B.EQ	50f404

(3772) 0x50f400 STR	D0, [X13], #8

(3772) 0x50f404 STR	D0, [X13], #8

(3772) 0x50f408 STR	D0, [X13], #8

(3772) 0x50f40c STR	D0, [X13], #8

(3772) 0x50f410 STR	D0, [X13], #8

(3772) 0x50f414 STR	D0, [X13], #8

(3772) 0x50f418 STR	D0, [X13], #8

(3772) 0x50f41c CMP	X6, X13

(3772) 0x50f420 B.EQ	50f44c

  (3773) 0x50f424 ORR	X12, XZR, X13

  (3773) 0x50f428 STR	D0, [X12], #8

  (3773) 0x50f42c STR	D0, [X13, #8]

  (3773) 0x50f430 STR	D0, [X12, #8]

  (3773) 0x50f434 STP	D0, D0, [X13, #24]

  (3773) 0x50f438 STP	D0, D0, [X13, #40]

  (3773) 0x50f43c ADD	X13, X13, #64

  (3773) 0x50f440 STUR	D0, [X13, #504]

  (3773) 0x50f444 CMP	X6, X13

  (3773) 0x50f448 B.NE	50f424

(3772) 0x50f44c LDP	X19, X20, [SP, #16]

(3772) 0x50f450 LDR	X21, [SP, #32]

(3772) 0x50f454 LDP	X29, X30, [SP], #48

(3772) 0x50f458 RET

(3772) 0x50f45c ADD	X2, X2, #1

(3772) 0x50f460 MOVZ	X3, #0

(3772) 0x50f464 B	50f398

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	vector.c:268-271
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/vector.c:268-271.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 20.00 to 10.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 50f360

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X21, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40f6a0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40f540 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SDIV X2, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MSUB X3, X2, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP X1, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 50f45c <hypre_SeqVectorSetConstantValues._omp_fn.0+0xfc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	vector.c:268-271
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/vector.c:268-271.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 50f360

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X21, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40f6a0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40f540 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SDIV X2, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MSUB X3, X2, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP X1, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 50f45c <hypre_SeqVectorSetConstantValues._omp_fn.0+0xfc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼hypre_SeqVectorSetConstantValues._omp_fn.0–	0.15	0.06
▼Loop 3772 - vector.c:268-271 - exec–	0	0
○Loop 3773 - vector.c:271-271 - exec	0.15	0.05

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code