OV - exec - Function hypre_CSRMatrixMatvecT._omp

	Function: hypre_CSRMatrixMatvecT._omp_fn.3	Module: exec	Source: csr_matvec.c:554-579 [...]	Coverage: 2.48%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 554 - 579

--------------------------------------------------------------------------------

554: #pragma omp parallel private(i,jj,j,my_thread_num,offset)

555: #endif

556:          {

557:             my_thread_num = hypre_GetThreadNum();

558:             offset =  y_size*my_thread_num;

[...]

564:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

565:                {

566:                   j = A_j[jj];

567:                   y_data_expand[offset + j] += A_data[jj] * x_data[i];

[...]

577:                for (j = 0; j < num_threads; j++)

578:                {

579:                   y_data[i] += y_data_expand[j*y_size + i];

0x50ca80 STP	X29, X30, [SP, #912]!

0x50ca84 ADD	X29, SP, #0

0x50ca88 STP	X27, X28, [SP, #80]

0x50ca8c LDP	X27, X9, [X0]

0x50ca90 STP	X19, X20, [SP, #16]

0x50ca94 STP	X25, X26, [SP, #64]

0x50ca98 LDP	X26, X20, [X0, #16]

0x50ca9c STP	X21, X22, [SP, #32]

0x50caa0 STP	X23, X24, [SP, #48]

0x50caa4 STR	X9, [SP, #104]

0x50caa8 LDP	X25, X23, [X0, #32]

0x50caac LDP	X22, X19, [X0, #48]

0x50cab0 LDR	X28, [X0, #64]

0x50cab4 BL	519580

0x50cab8 ORR	X24, XZR, X0

0x50cabc BL	40f6a0

0x50cac0 SBFM	X21, X0, #0, #31

0x50cac4 BL	40f540

0x50cac8 SDIV	X12, X20, X21

0x50cacc SBFM	X8, X0, #0, #31

0x50cad0 LDR	X14, [SP, #104]

0x50cad4 MSUB	X2, X12, X21, X20

0x50cad8 CMP	X8, X2

0x50cadc B.LT	50cdfc

0x50cae0 MADD	X18, X12, X8, X2

0x50cae4 ADD	X15, X12, X18

0x50cae8 CMP	X18, X15

0x50caec B.GE	50cc28

0x50caf0 MADD	X16, X22, X24, XZR

0x50caf4 ADD	X13, X14, #8

0x50caf8 HINT	#0

0x50cafc HINT	#0

(3729) 0x50cb00 LDR	X1, [X14, X18,LSL #3]

(3729) 0x50cb04 LDR	X11, [X13, X18,LSL #3]

(3729) 0x50cb08 CMP	X1, X11

(3729) 0x50cb0c B.GE	50cc1c

(3729) 0x50cb10 SUB	X0, X11, X1

(3729) 0x50cb14 ANDS	X3, X0, #4160

(3729) 0x50cb18 B.EQ	50cb94

(3729) 0x50cb1c CMP	X3, #1

(3729) 0x50cb20 B.EQ	50cb6c

(3729) 0x50cb24 CMP	X3, #2

(3729) 0x50cb28 B.EQ	50cb4c

(3729) 0x50cb2c LDR	X4, [X26, X1,LSL #3]

(3729) 0x50cb30 LDR	D2, [X27, X1,LSL #3]

(3729) 0x50cb34 ADD	X1, X1, #1

(3729) 0x50cb38 LDR	D1, [X25, X18,LSL #3]

(3729) 0x50cb3c ADD	X5, X16, X4

(3729) 0x50cb40 LDR	D0, [X19, X5,LSL #3]

(3729) 0x50cb44 FMADD	D3, D2, D1, D0

(3729) 0x50cb48 STR	D3, [X19, X5,LSL #3]

(3729) 0x50cb4c LDR	X6, [X26, X1,LSL #3]

(3729) 0x50cb50 LDR	D4, [X27, X1,LSL #3]

(3729) 0x50cb54 ADD	X1, X1, #1

(3729) 0x50cb58 LDR	D5, [X25, X18,LSL #3]

(3729) 0x50cb5c ADD	X7, X16, X6

(3729) 0x50cb60 LDR	D6, [X19, X7,LSL #3]

(3729) 0x50cb64 FMADD	D7, D4, D5, D6

(3729) 0x50cb68 STR	D7, [X19, X7,LSL #3]

(3729) 0x50cb6c LDR	X10, [X26, X1,LSL #3]

(3729) 0x50cb70 LDR	D16, [X27, X1,LSL #3]

(3729) 0x50cb74 ADD	X1, X1, #1

(3729) 0x50cb78 LDR	D17, [X25, X18,LSL #3]

(3729) 0x50cb7c ADD	X17, X16, X10

(3729) 0x50cb80 LDR	D18, [X19, X17,LSL #3]

(3729) 0x50cb84 FMADD	D19, D16, D17, D18

(3729) 0x50cb88 STR	D19, [X19, X17,LSL #3]

(3729) 0x50cb8c CMP	X1, X11

(3729) 0x50cb90 B.EQ	50cc1c

  (3730) 0x50cb94 LDR	X0, [X26, X1,LSL #3]

  (3730) 0x50cb98 ADD	X6, X1, #1

  (3730) 0x50cb9c ADD	X7, X1, #3

  (3730) 0x50cba0 ADD	X10, X1, #2

  (3730) 0x50cba4 LDR	D19, [X27, X1,LSL #3]

  (3730) 0x50cba8 ADD	X1, X1, #4

  (3730) 0x50cbac LDR	D20, [X25, X18,LSL #3]

  (3730) 0x50cbb0 ADD	X5, X16, X0

  (3730) 0x50cbb4 LDR	X4, [X26, X6,LSL #3]

  (3730) 0x50cbb8 LDR	D21, [X19, X5,LSL #3]

  (3730) 0x50cbbc LDR	X3, [X26, X10,LSL #3]

  (3730) 0x50cbc0 ADD	X9, X16, X4

  (3730) 0x50cbc4 LDR	X17, [X26, X7,LSL #3]

  (3730) 0x50cbc8 FMADD	D22, D19, D20, D21

  (3730) 0x50cbcc ADD	X30, X16, X3

  (3730) 0x50cbd0 ADD	X17, X16, X17

  (3730) 0x50cbd4 STR	D22, [X19, X5,LSL #3]

  (3730) 0x50cbd8 LDR	D23, [X27, X6,LSL #3]

  (3730) 0x50cbdc LDR	D24, [X25, X18,LSL #3]

  (3730) 0x50cbe0 LDR	D25, [X19, X9,LSL #3]

  (3730) 0x50cbe4 FMADD	D26, D23, D24, D25

  (3730) 0x50cbe8 STR	D26, [X19, X9,LSL #3]

  (3730) 0x50cbec LDR	D27, [X27, X10,LSL #3]

  (3730) 0x50cbf0 LDR	D28, [X25, X18,LSL #3]

  (3730) 0x50cbf4 LDR	D29, [X19, X30,LSL #3]

  (3730) 0x50cbf8 FMADD	D30, D27, D28, D29

  (3730) 0x50cbfc STR	D30, [X19, X30,LSL #3]

  (3730) 0x50cc00 LDR	D16, [X27, X7,LSL #3]

  (3730) 0x50cc04 LDR	D17, [X25, X18,LSL #3]

  (3730) 0x50cc08 LDR	D18, [X19, X17,LSL #3]

  (3730) 0x50cc0c FMADD	D19, D16, D17, D18

  (3730) 0x50cc10 STR	D19, [X19, X17,LSL #3]

  (3730) 0x50cc14 CMP	X1, X11

  (3730) 0x50cc18 B.NE	50cb94

(3729) 0x50cc1c ADD	X18, X18, #1

(3729) 0x50cc20 CMP	X15, X18

(3729) 0x50cc24 B.NE	50cb00

0x50cc28 STR	X8, [SP, #104]

0x50cc2c BL	40f590

0x50cc30 SDIV	X9, X22, X21

0x50cc34 LDR	X27, [SP, #104]

0x50cc38 MSUB	X26, X9, X21, X22

0x50cc3c CMP	X27, X26

0x50cc40 B.LT	50cdf0

0x50cc44 MADD	X16, X9, X27, X26

0x50cc48 ADD	X30, X9, X16

0x50cc4c CMP	X16, X30

0x50cc50 B.GE	50cdd4

0x50cc54 CMP	X28, #0

0x50cc58 B.LE	50cdd4

0x50cc5c ADD	X19, X19, X16,LSL #3

0x50cc60 UBFM	X20, X22, #61, #60

(3728) 0x50cc64 ANDS	X25, X28, #4224

(3728) 0x50cc68 ORR	X24, XZR, X19

(3728) 0x50cc6c LDR	D27, [X23, X16,LSL #3]

(3728) 0x50cc70 MOVZ	X22, #0

(3728) 0x50cc74 B.EQ	50cd3c

(3728) 0x50cc78 CMP	X25, #1

(3728) 0x50cc7c B.EQ	50cd20

(3728) 0x50cc80 CMP	X25, #2

(3728) 0x50cc84 B.EQ	50cd0c

(3728) 0x50cc88 CMP	X25, #3

(3728) 0x50cc8c B.EQ	50ccf8

(3728) 0x50cc90 CMP	X25, #4

(3728) 0x50cc94 B.EQ	50cce4

(3728) 0x50cc98 CMP	X25, #5

(3728) 0x50cc9c B.EQ	50ccd0

(3728) 0x50cca0 CMP	X25, #6

(3728) 0x50cca4 B.EQ	50ccbc

(3728) 0x50cca8 LDR	D20, [X19]

(3728) 0x50ccac MOVZ	X22, #1

(3728) 0x50ccb0 ADD	X24, X19, X20

(3728) 0x50ccb4 FADD	D27, D27, D20

(3728) 0x50ccb8 STR	D27, [X23, X16,LSL #3]

(3728) 0x50ccbc LDR	D21, [X24]

(3728) 0x50ccc0 ADD	X22, X22, #1

(3728) 0x50ccc4 ADD	X24, X24, X20

(3728) 0x50ccc8 FADD	D27, D27, D21

(3728) 0x50cccc STR	D27, [X23, X16,LSL #3]

(3728) 0x50ccd0 LDR	D22, [X24]

(3728) 0x50ccd4 ADD	X22, X22, #1

(3728) 0x50ccd8 ADD	X24, X24, X20

(3728) 0x50ccdc FADD	D27, D27, D22

(3728) 0x50cce0 STR	D27, [X23, X16,LSL #3]

(3728) 0x50cce4 LDR	D23, [X24]

(3728) 0x50cce8 ADD	X22, X22, #1

(3728) 0x50ccec ADD	X24, X24, X20

(3728) 0x50ccf0 FADD	D27, D27, D23

(3728) 0x50ccf4 STR	D27, [X23, X16,LSL #3]

(3728) 0x50ccf8 LDR	D24, [X24]

(3728) 0x50ccfc ADD	X22, X22, #1

(3728) 0x50cd00 ADD	X24, X24, X20

(3728) 0x50cd04 FADD	D27, D27, D24

(3728) 0x50cd08 STR	D27, [X23, X16,LSL #3]

(3728) 0x50cd0c LDR	D25, [X24]

(3728) 0x50cd10 ADD	X22, X22, #1

(3728) 0x50cd14 ADD	X24, X24, X20

(3728) 0x50cd18 FADD	D27, D27, D25

(3728) 0x50cd1c STR	D27, [X23, X16,LSL #3]

(3728) 0x50cd20 LDR	D26, [X24]

(3728) 0x50cd24 ADD	X22, X22, #1

(3728) 0x50cd28 ADD	X24, X24, X20

(3728) 0x50cd2c FADD	D27, D27, D26

(3728) 0x50cd30 STR	D27, [X23, X16,LSL #3]

(3728) 0x50cd34 CMP	X28, X22

(3728) 0x50cd38 B.EQ	50cdc4

  (3727) 0x50cd3c LDR	D28, [X24]

  (3727) 0x50cd40 ADD	X21, X24, X20

  (3727) 0x50cd44 ADD	X22, X22, #8

  (3727) 0x50cd48 ADD	X8, X21, X20

  (3727) 0x50cd4c ADD	X14, X8, X20

  (3727) 0x50cd50 ADD	X12, X14, X20

  (3727) 0x50cd54 ADD	X2, X12, X20

  (3727) 0x50cd58 ADD	X15, X2, X20

  (3727) 0x50cd5c FADD	D29, D27, D28

  (3727) 0x50cd60 STR	D29, [X23, X16,LSL #3]

  (3727) 0x50cd64 LDR	D30, [X24, X20]

  (3727) 0x50cd68 ADD	X24, X15, X20,LSL #1

  (3727) 0x50cd6c FADD	D31, D29, D30

  (3727) 0x50cd70 STR	D31, [X23, X16,LSL #3]

  (3727) 0x50cd74 LDR	D2, [X21, X20]

  (3727) 0x50cd78 FADD	D0, D31, D2

  (3727) 0x50cd7c STR	D0, [X23, X16,LSL #3]

  (3727) 0x50cd80 LDR	D1, [X8, X20]

  (3727) 0x50cd84 FADD	D3, D0, D1

  (3727) 0x50cd88 STR	D3, [X23, X16,LSL #3]

  (3727) 0x50cd8c LDR	D4, [X14, X20]

  (3727) 0x50cd90 FADD	D5, D3, D4

  (3727) 0x50cd94 STR	D5, [X23, X16,LSL #3]

  (3727) 0x50cd98 LDR	D6, [X12, X20]

  (3727) 0x50cd9c FADD	D7, D5, D6

  (3727) 0x50cda0 STR	D7, [X23, X16,LSL #3]

  (3727) 0x50cda4 LDR	D16, [X2, X20]

  (3727) 0x50cda8 FADD	D17, D7, D16

  (3727) 0x50cdac STR	D17, [X23, X16,LSL #3]

  (3727) 0x50cdb0 LDR	D18, [X15, X20]

  (3727) 0x50cdb4 FADD	D27, D17, D18

  (3727) 0x50cdb8 STR	D27, [X23, X16,LSL #3]

  (3727) 0x50cdbc CMP	X28, X22

  (3727) 0x50cdc0 B.NE	50cd3c

(3728) 0x50cdc4 ADD	X16, X16, #1

(3728) 0x50cdc8 ADD	X19, X19, #8

(3728) 0x50cdcc CMP	X30, X16

(3728) 0x50cdd0 B.NE	50cc64

0x50cdd4 LDP	X19, X20, [SP, #16]

0x50cdd8 LDP	X21, X22, [SP, #32]

0x50cddc LDP	X23, X24, [SP, #48]

0x50cde0 LDP	X25, X26, [SP, #64]

0x50cde4 LDP	X27, X28, [SP, #80]

0x50cde8 LDP	X29, X30, [SP], #112

0x50cdec B	40f590

0x50cdf0 ADD	X9, X9, #1

0x50cdf4 MOVZ	X26, #0

0x50cdf8 B	50cc44

0x50cdfc ADD	X12, X12, #1

0x50ce00 MOVZ	X2, #0

0x50ce04 B	50cae0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	csr_matvec.c:554-579
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:554-558,564-567,577-579.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 40.00 to 20.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 40.00 to 2.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 184 bytes. The binary function is storing 112 bytes.

General properties

nb instructions	60
loop length	240
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.00	6.00	7.50	7.50	7.50	7.50	0.00	0.00	0.00	0.00	7.00	7.00	7.00	4.00	4.00
cycles	6.00	6.00	7.50	7.50	7.50	7.50	0.00	0.00	0.00	0.00	7.00	7.00	7.00	4.00	4.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-40.00

Cycles summary

Front-end	7.25
Overall L1	10.00-40.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 40.00 cycles. At this rate:

4% of peak load performance is reached (4.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 50ca80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X27, X9, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X26, X20, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X9, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X25, X23, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X19, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X28, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 519580 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X24, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f6a0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X21, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f540 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SDIV X12, X20, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
SBFM X8, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MSUB X2, X12, X21, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X8, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 50cdfc <hypre_CSRMatrixMatvecT._omp_fn.3+0x37c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X18, X12, X8, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X15, X12, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X18, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 50cc28 <hypre_CSRMatrixMatvecT._omp_fn.3+0x1a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X16, X22, X24, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X13, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f590 <@plt_start@+0x3a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SDIV X9, X22, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
LDR X27, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MSUB X26, X9, X21, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X27, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 50cdf0 <hypre_CSRMatrixMatvecT._omp_fn.3+0x370>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X16, X9, X27, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X30, X9, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X16, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 50cdd4 <hypre_CSRMatrixMatvecT._omp_fn.3+0x354>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X28, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 50cdd4 <hypre_CSRMatrixMatvecT._omp_fn.3+0x354>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X19, X19, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X20, X22, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #112	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 40f590 <@plt_start@+0x3a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X26, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 50cc44 <hypre_CSRMatrixMatvecT._omp_fn.3+0x1c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X12, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 50cae0 <hypre_CSRMatrixMatvecT._omp_fn.3+0x60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	csr_matvec.c:554-579
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:554-558,564-567,577-579.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 40.00 to 2.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 184 bytes. The binary function is storing 112 bytes.

General properties

nb instructions	60
loop length	240
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.00	6.00	7.50	7.50	7.50	7.50	0.00	0.00	0.00	0.00	7.00	7.00	7.00	4.00	4.00
cycles	6.00	6.00	7.50	7.50	7.50	7.50	0.00	0.00	0.00	0.00	7.00	7.00	7.00	4.00	4.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-40.00

Cycles summary

Front-end	7.25
Overall L1	10.00-40.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 40.00 cycles. At this rate:

4% of peak load performance is reached (4.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 50ca80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X27, X9, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X26, X20, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X9, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X25, X23, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X19, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X28, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 519580 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X24, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f6a0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X21, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f540 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SDIV X12, X20, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
SBFM X8, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MSUB X2, X12, X21, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X8, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 50cdfc <hypre_CSRMatrixMatvecT._omp_fn.3+0x37c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X18, X12, X8, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X15, X12, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X18, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 50cc28 <hypre_CSRMatrixMatvecT._omp_fn.3+0x1a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X16, X22, X24, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X13, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f590 <@plt_start@+0x3a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SDIV X9, X22, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
LDR X27, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MSUB X26, X9, X21, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X27, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 50cdf0 <hypre_CSRMatrixMatvecT._omp_fn.3+0x370>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X16, X9, X27, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X30, X9, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X16, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 50cdd4 <hypre_CSRMatrixMatvecT._omp_fn.3+0x354>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X28, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 50cdd4 <hypre_CSRMatrixMatvecT._omp_fn.3+0x354>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X19, X19, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X20, X22, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #112	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 40f590 <@plt_start@+0x3a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X26, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 50cc44 <hypre_CSRMatrixMatvecT._omp_fn.3+0x1c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X12, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 50cae0 <hypre_CSRMatrixMatvecT._omp_fn.3+0x60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼hypre_CSRMatrixMatvecT._omp_fn.3–	2.48	0.94
▼Loop 3729 - csr_matvec.c:564-567 - exec–	0.61	0.2
○Loop 3730 - csr_matvec.c:564-567 - exec	0.14	0.05
▼Loop 3728 - csr_matvec.c:577-579 - exec–	0	0.01
○Loop 3727 - csr_matvec.c:577-579 - exec	1.73	0.57

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code