OV - exec - Function hypre_CSRMatrixTranspose._omp

	Function: hypre_CSRMatrixTranspose._omp_fn.0	Module: exec	Source: csr_matop.c:380-560 [...]	Coverage: 0.29%

/usr/include/aarch64-linux-gnu/bits/string_fortified.h: 59 - 59

--------------------------------------------------------------------------------

59:   return __builtin___memset_chk (__dest, __ch, __len,

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c: 380 - 560

--------------------------------------------------------------------------------

380:   return idx%dim1*dim2 + idx/dim1;

[...]

463: #pragma omp parallel

464: #endif

465:    {

466:    HYPRE_Int num_threads = hypre_NumActiveThreads();

467:    HYPRE_Int my_thread_num = hypre_GetThreadNum();

468:

469:    HYPRE_Int iBegin = hypre_CSRMatrixGetLoadBalancedPartitionBegin(A);

470:    HYPRE_Int iEnd = hypre_CSRMatrixGetLoadBalancedPartitionEnd(A);

471:    hypre_assert(iBegin <= iEnd);

472:    hypre_assert(iBegin >= 0 && iBegin <= num_rowsA);

473:    hypre_assert(iEnd >= 0 && iEnd <= num_rowsA);

474:

475:    HYPRE_Int i, j;

476:    memset(bucket + my_thread_num*num_colsA, 0, sizeof(HYPRE_Int)*num_colsA);

[...]

483:    for (j = A_i[iBegin]; j < A_i[iEnd]; ++j) {

484:      HYPRE_Int idx = A_j[j];

485:      bucket[my_thread_num*num_colsA + idx]++;

[...]

493: #pragma omp barrier

494: #endif

495:

496:    for (i = my_thread_num*num_colsA + 1; i < (my_thread_num + 1)*num_colsA; ++i) {

497:      HYPRE_Int transpose_i = transpose_idx(i, num_threads, num_colsA);

498:      HYPRE_Int transpose_i_minus_1 = transpose_idx(i - 1, num_threads, num_colsA);

499:

500:      bucket[transpose_i] += bucket[transpose_i_minus_1];

501:    }

502:

503: #ifdef HYPRE_USING_OPENMP

504: #pragma omp barrier

505: #pragma omp master

506: #endif

507:    {

508:      for (i = 1; i < num_threads; ++i) {

509:        HYPRE_Int j0 = num_colsA*i - 1, j1 = num_colsA*(i + 1) - 1;

510:        HYPRE_Int transpose_j0 = transpose_idx(j0, num_threads, num_colsA);

511:        HYPRE_Int transpose_j1 = transpose_idx(j1, num_threads, num_colsA);

512:

513:        bucket[transpose_j1] += bucket[transpose_j0];

514:      }

515:    }

516: #ifdef HYPRE_USING_OPENMP

517: #pragma omp barrier

518: #endif

519:

520:    if (my_thread_num > 0) {

521:      HYPRE_Int transpose_i0 = transpose_idx(num_colsA*my_thread_num - 1, num_threads, num_colsA);

522:      HYPRE_Int offset = bucket[transpose_i0];

523:

524:      for (i = my_thread_num*num_colsA; i < (my_thread_num + 1)*num_colsA - 1; ++i) {

525:        HYPRE_Int transpose_i = transpose_idx(i, num_threads, num_colsA);

526:

527:        bucket[transpose_i] += offset;

528:      }

529:    }

530:

531: #ifdef HYPRE_USING_OPENMP

532: #pragma omp barrier

[...]

539:    if (data) {

540:       for (i = iEnd - 1; i >= iBegin; --i) {

541:         for (j = A_i[i + 1] - 1; j >= A_i[i]; --j) {

542:           HYPRE_Int idx = A_j[j];

543:           --bucket[my_thread_num*num_colsA + idx];

544:

545:           HYPRE_Int offset = bucket[my_thread_num*num_colsA + idx];

546:

547:           AT_data[offset] = A_data[j];

548:           AT_j[offset] = i;

549:         }

550:       }

551:    }

552:    else {

553:       for (i = iEnd - 1; i >= iBegin; --i) {

554:         for (j = A_i[i + 1] - 1; j >= A_i[i]; --j) {

555:           HYPRE_Int idx = A_j[j];

556:           --bucket[my_thread_num*num_colsA + idx];

557:

558:           HYPRE_Int offset = bucket[my_thread_num*num_colsA + idx];

559:

560:           AT_j[offset] = i;

0x505a64 STP	X29, X30, [SP, #896]!

0x505a68 ADD	X29, SP, #0

0x505a6c STP	X19, X20, [SP, #16]

0x505a70 LDP	X19, X1, [X0]

0x505a74 STP	X21, X22, [SP, #32]

0x505a78 STP	X23, X24, [SP, #48]

0x505a7c STP	X25, X26, [SP, #64]

0x505a80 STP	X27, X28, [SP, #80]

0x505a84 STR	X1, [SP, #120]

0x505a88 LDP	X28, X22, [X0, #16]

0x505a8c LDP	X23, X21, [X0, #32]

0x505a90 LDP	X27, X26, [X0, #48]

0x505a94 LDP	X24, X20, [X0, #64]

0x505a98 BL	519560

0x505a9c ORR	X25, XZR, X0

0x505aa0 BL	519580

0x505aa4 ORR	X2, XZR, X0

0x505aa8 ORR	X0, XZR, X19

0x505aac STR	X2, [SP, #104]

0x505ab0 BL	509ae0

0x505ab4 ORR	X3, XZR, X0

0x505ab8 ORR	X0, XZR, X19

0x505abc STR	X3, [SP, #96]

0x505ac0 BL	509b84

0x505ac4 ORR	X19, XZR, X0

0x505ac8 LDR	X0, [SP, #96]

0x505acc CMP	X0, X19

0x505ad0 B.GT	506018

0x505ad4 LDR	X9, [SP, #96]

0x505ad8 CMP	X9, #0

0x505adc CCMP	X21, X9, #1, #10

0x505ae0 B.LT	506060

(3591) 0x505ae4 CMP	X19, #0

(3591) 0x505ae8 CCMP	X21, X19, #1, #10

(3591) 0x505aec B.LT	5060a4

(3591) 0x505af0 LDR	X30, [SP, #104]

(3591) 0x505af4 UBFM	X2, X27, #61, #60

(3591) 0x505af8 MOVZ	W1, #0

(3591) 0x505afc MADD	X21, X27, X30, XZR

(3591) 0x505b00 ADD	X0, X20, X21,LSL #3

(3591) 0x505b04 BL	40f370

(3591) 0x505b08 LDR	X2, [SP, #96]

(3591) 0x505b0c ADD	X3, X22, X19,LSL #3

(3591) 0x505b10 LDR	X0, [X22, X19,LSL #3]

(3591) 0x505b14 LDR	X5, [X22, X2,LSL #3]

(3591) 0x505b18 CMP	X5, X0

(3591) 0x505b1c B.GE	505b44

  (3600) 0x505b20 LDR	X4, [X23, X5,LSL #3]

  (3600) 0x505b24 ADD	X5, X5, #1

  (3600) 0x505b28 ADD	X6, X21, X4

  (3600) 0x505b2c LDR	X7, [X20, X6,LSL #3]

  (3600) 0x505b30 ADD	X8, X7, #1

  (3600) 0x505b34 STR	X8, [X20, X6,LSL #3]

  (3600) 0x505b38 LDR	X9, [X3]

  (3600) 0x505b3c CMP	X9, X5

  (3600) 0x505b40 B.GT	505b20

(3591) 0x505b44 BL	40f590

(3591) 0x505b48 ADD	X1, X27, X21

(3591) 0x505b4c ADD	X0, X21, #1

(3591) 0x505b50 STR	X1, [SP, #112]

(3591) 0x505b54 CMP	X27, #1

(3591) 0x505b58 B.LE	505cac

(3591) 0x505b5c SUB	X11, X1, X0

(3591) 0x505b60 ANDS	X12, X11, #4160

(3591) 0x505b64 B.EQ	505c1c

(3591) 0x505b68 CMP	X12, #1

(3591) 0x505b6c B.EQ	505bdc

(3591) 0x505b70 CMP	X12, #2

(3591) 0x505b74 B.EQ	505ba8

(3591) 0x505b78 SDIV	X13, X0, X25

(3591) 0x505b7c SDIV	X14, X21, X25

(3591) 0x505b80 MSUB	X15, X13, X25, X0

(3591) 0x505b84 ADD	X0, X0, #1

(3591) 0x505b88 MADD	X16, X15, X27, X13

(3591) 0x505b8c MSUB	X17, X14, X25, X21

(3591) 0x505b90 ADD	X18, X20, X16,LSL #3

(3591) 0x505b94 MADD	X30, X17, X27, X14

(3591) 0x505b98 LDR	X2, [X18]

(3591) 0x505b9c LDR	X3, [X20, X30,LSL #3]

(3591) 0x505ba0 ADD	X4, X2, X3

(3591) 0x505ba4 STR	X4, [X18]

(3591) 0x505ba8 SDIV	X6, X0, X25

(3591) 0x505bac SUB	X5, X0, #1

(3591) 0x505bb0 SDIV	X7, X5, X25

(3591) 0x505bb4 MSUB	X8, X6, X25, X0

(3591) 0x505bb8 ADD	X0, X0, #1

(3591) 0x505bbc MADD	X9, X8, X27, X6

(3591) 0x505bc0 MSUB	X10, X7, X25, X5

(3591) 0x505bc4 ADD	X1, X20, X9,LSL #3

(3591) 0x505bc8 MADD	X11, X10, X27, X7

(3591) 0x505bcc LDR	X13, [X1]

(3591) 0x505bd0 LDR	X12, [X20, X11,LSL #3]

(3591) 0x505bd4 ADD	X14, X13, X12

(3591) 0x505bd8 STR	X14, [X1]

(3591) 0x505bdc SDIV	X16, X0, X25

(3591) 0x505be0 SUB	X15, X0, #1

(3591) 0x505be4 LDR	X8, [SP, #112]

(3591) 0x505be8 SDIV	X17, X15, X25

(3591) 0x505bec MSUB	X18, X16, X25, X0

(3591) 0x505bf0 ADD	X0, X0, #1

(3591) 0x505bf4 MADD	X30, X18, X27, X16

(3591) 0x505bf8 MSUB	X3, X17, X25, X15

(3591) 0x505bfc ADD	X4, X20, X30,LSL #3

(3591) 0x505c00 MADD	X2, X3, X27, X17

(3591) 0x505c04 LDR	X6, [X4]

(3591) 0x505c08 LDR	X5, [X20, X2,LSL #3]

(3591) 0x505c0c ADD	X7, X6, X5

(3591) 0x505c10 STR	X7, [X4]

(3591) 0x505c14 CMP	X0, X8

(3591) 0x505c18 B.EQ	505cac

  (3599) 0x505c1c SUB	X12, X0, #1

  (3599) 0x505c20 SDIV	X13, X0, X25

  (3599) 0x505c24 ADD	X9, X0, #1

  (3599) 0x505c28 ADD	X11, X0, #2

  (3599) 0x505c2c ADD	X10, X0, #3

  (3599) 0x505c30 SDIV	X14, X12, X25

  (3599) 0x505c34 SDIV	X1, X9, X25

  (3599) 0x505c38 MSUB	X15, X13, X25, X0

  (3599) 0x505c3c ADD	X0, X0, #4

  (3599) 0x505c40 SDIV	X5, X11, X25

  (3599) 0x505c44 MSUB	X16, X14, X25, X12

  (3599) 0x505c48 MADD	X17, X15, X27, X13

  (3599) 0x505c4c MSUB	X4, X1, X25, X9

  (3599) 0x505c50 MADD	X18, X16, X27, X14

  (3599) 0x505c54 LDR	X30, [X20, X17,LSL #3]

  (3599) 0x505c58 SDIV	X7, X10, X25

  (3599) 0x505c5c LDR	X3, [X20, X18,LSL #3]

  (3599) 0x505c60 MADD	X6, X4, X27, X1

  (3599) 0x505c64 LDR	X18, [SP, #112]

  (3599) 0x505c68 MSUB	X12, X5, X25, X11

  (3599) 0x505c6c ADD	X2, X30, X3

  (3599) 0x505c70 MADD	X13, X12, X27, X5

  (3599) 0x505c74 STR	X2, [X20, X17,LSL #3]

  (3599) 0x505c78 LDR	X8, [X20, X6,LSL #3]

  (3599) 0x505c7c MSUB	X11, X7, X25, X10

  (3599) 0x505c80 MADD	X14, X11, X27, X7

  (3599) 0x505c84 ADD	X9, X8, X2

  (3599) 0x505c88 STR	X9, [X20, X6,LSL #3]

  (3599) 0x505c8c LDR	X1, [X20, X13,LSL #3]

  (3599) 0x505c90 ADD	X2, X1, X9

  (3599) 0x505c94 STR	X2, [X20, X13,LSL #3]

  (3599) 0x505c98 LDR	X15, [X20, X14,LSL #3]

  (3599) 0x505c9c ADD	X17, X15, X2

  (3599) 0x505ca0 STR	X17, [X20, X14,LSL #3]

  (3599) 0x505ca4 CMP	X0, X18

  (3599) 0x505ca8 B.NE	505c1c

(3591) 0x505cac BL	40f590

(3591) 0x505cb0 BL	40f540

(3591) 0x505cb4 CBNZ	W0, 505de0

(3591) 0x505cb8 CMP	X25, #1

(3591) 0x505cbc B.LE	505de0

(3591) 0x505cc0 SUB	X30, X27, #1

(3591) 0x505cc4 MOVZ	X0, #1

(3591) 0x505cc8 SDIV	X4, X30, X25

(3591) 0x505ccc MSUB	X5, X4, X25, X30

(3591) 0x505cd0 MADD	X3, X5, X27, X4

(3591) 0x505cd4 LDR	X2, [X20, X3,LSL #3]

(3591) 0x505cd8 CMP	X27, X0

(3591) 0x505cdc B.NE	5061e0

(3591) 0x505ce0 SUB	X4, X25, X27

(3591) 0x505ce4 ANDS	X12, X4, #4160

(3591) 0x505ce8 B.EQ	505d64

(3591) 0x505cec CMP	X12, X0

(3591) 0x505cf0 B.EQ	505d3c

(3591) 0x505cf4 CMP	X12, #2

(3591) 0x505cf8 B.EQ	505d1c

(3591) 0x505cfc SDIV	X11, X27, X25

(3591) 0x505d00 MOVZ	X0, #2

(3591) 0x505d04 MSUB	X14, X11, X25, X27

(3591) 0x505d08 ADD	X10, X11, X14

(3591) 0x505d0c ADD	X15, X20, X10,LSL #3

(3591) 0x505d10 LDR	X1, [X15]

(3591) 0x505d14 ADD	X2, X2, X1

(3591) 0x505d18 STR	X2, [X15]

(3591) 0x505d1c SDIV	X16, X0, X25

(3591) 0x505d20 MSUB	X17, X16, X25, X0

(3591) 0x505d24 ADD	X0, X0, #1

(3591) 0x505d28 ADD	X18, X16, X17

(3591) 0x505d2c ADD	X30, X20, X18,LSL #3

(3591) 0x505d30 LDR	X5, [X30]

(3591) 0x505d34 ADD	X2, X2, X5

(3591) 0x505d38 STR	X2, [X30]

(3591) 0x505d3c SDIV	X6, X0, X25

(3591) 0x505d40 MSUB	X3, X6, X25, X0

(3591) 0x505d44 ADD	X0, X0, #1

(3591) 0x505d48 ADD	X7, X6, X3

(3591) 0x505d4c ADD	X13, X20, X7,LSL #3

(3591) 0x505d50 LDR	X9, [X13]

(3591) 0x505d54 ADD	X2, X2, X9

(3591) 0x505d58 STR	X2, [X13]

(3591) 0x505d5c CMP	X25, X0

(3591) 0x505d60 B.EQ	505de0

  (3598) 0x505d64 SDIV	X8, X0, X25

  (3598) 0x505d68 ADD	X4, X0, #1

  (3598) 0x505d6c ADD	X12, X0, #2

  (3598) 0x505d70 ADD	X11, X0, #3

  (3598) 0x505d74 SDIV	X14, X4, X25

  (3598) 0x505d78 SDIV	X16, X12, X25

  (3598) 0x505d7c MSUB	X10, X8, X25, X0

  (3598) 0x505d80 ADD	X0, X0, #4

  (3598) 0x505d84 SDIV	X5, X11, X25

  (3598) 0x505d88 ADD	X15, X8, X10

  (3598) 0x505d8c LDR	X1, [X20, X15,LSL #3]

  (3598) 0x505d90 MSUB	X17, X14, X25, X4

  (3598) 0x505d94 MSUB	X6, X16, X25, X12

  (3598) 0x505d98 ADD	X30, X14, X17

  (3598) 0x505d9c ADD	X18, X2, X1

  (3598) 0x505da0 ADD	X13, X16, X6

  (3598) 0x505da4 STR	X18, [X20, X15,LSL #3]

  (3598) 0x505da8 MSUB	X3, X5, X25, X11

  (3598) 0x505dac LDR	X2, [X20, X30,LSL #3]

  (3598) 0x505db0 ADD	X8, X5, X3

  (3598) 0x505db4 ADD	X7, X18, X2

  (3598) 0x505db8 STR	X7, [X20, X30,LSL #3]

  (3598) 0x505dbc LDR	X9, [X20, X13,LSL #3]

  (3598) 0x505dc0 ADD	X4, X7, X9

  (3598) 0x505dc4 STR	X4, [X20, X13,LSL #3]

  (3598) 0x505dc8 LDR	X11, [X20, X8,LSL #3]

  (3598) 0x505dcc ADD	X2, X4, X11

  (3598) 0x505dd0 STR	X2, [X20, X8,LSL #3]

  (3598) 0x505dd4 CMP	X25, X0

  (3598) 0x505dd8 B.NE	505d64

(3591) 0x505ddc HINT	#0

(3591) 0x505de0 BL	40f590

(3591) 0x505de4 LDR	X0, [SP, #104]

(3591) 0x505de8 CMP	X0, #0

(3591) 0x505dec B.LE	505f00

(3591) 0x505df0 SUB	X12, X21, #1

(3591) 0x505df4 LDR	X14, [SP, #112]

(3591) 0x505df8 SDIV	X10, X12, X25

(3591) 0x505dfc SUB	X15, X14, #1

(3591) 0x505e00 MSUB	X1, X10, X25, X12

(3591) 0x505e04 MADD	X16, X1, X27, X10

(3591) 0x505e08 LDR	X17, [X20, X16,LSL #3]

(3591) 0x505e0c CMP	X21, X15

(3591) 0x505e10 B.GE	505f00

(3591) 0x505e14 ORR	X0, XZR, X21

(3591) 0x505e18 SUB	X18, X15, X21

(3591) 0x505e1c CMP	X27, #1

(3591) 0x505e20 B.NE	5060e0

(3591) 0x505e24 ANDS	X27, X18, #4160

(3591) 0x505e28 B.EQ	505e84

(3591) 0x505e2c CMP	X27, #1

(3591) 0x505e30 B.EQ	505e5c

(3591) 0x505e34 CMP	X27, #2

(3591) 0x505e38 B.NE	5061bc

(3591) 0x505e3c SDIV	X16, X0, X25

(3591) 0x505e40 MSUB	X1, X16, X25, X0

(3591) 0x505e44 ADD	X0, X0, #1

(3591) 0x505e48 ADD	X18, X1, X16

(3591) 0x505e4c ADD	X30, X20, X18,LSL #3

(3591) 0x505e50 LDR	X5, [X30]

(3591) 0x505e54 ADD	X6, X5, X17

(3591) 0x505e58 STR	X6, [X30]

(3591) 0x505e5c SDIV	X7, X0, X25

(3591) 0x505e60 MSUB	X2, X7, X25, X0

(3591) 0x505e64 ADD	X0, X0, #1

(3591) 0x505e68 ADD	X13, X2, X7

(3591) 0x505e6c ADD	X3, X20, X13,LSL #3

(3591) 0x505e70 LDR	X8, [X3]

(3591) 0x505e74 ADD	X27, X8, X17

(3591) 0x505e78 STR	X27, [X3]

(3591) 0x505e7c CMP	X0, X15

(3591) 0x505e80 B.EQ	505f00

  (3596) 0x505e84 SDIV	X9, X0, X25

  (3596) 0x505e88 ADD	X4, X0, #1

  (3596) 0x505e8c ADD	X14, X0, #2

  (3596) 0x505e90 ADD	X12, X0, #3

  (3596) 0x505e94 SDIV	X10, X4, X25

  (3596) 0x505e98 SDIV	X11, X14, X25

  (3596) 0x505e9c MSUB	X16, X9, X25, X0

  (3596) 0x505ea0 ADD	X0, X0, #4

  (3596) 0x505ea4 SDIV	X6, X12, X25

  (3596) 0x505ea8 ADD	X18, X16, X9

  (3596) 0x505eac LDR	X30, [X20, X18,LSL #3]

  (3596) 0x505eb0 MSUB	X1, X10, X25, X4

  (3596) 0x505eb4 MSUB	X2, X11, X25, X14

  (3596) 0x505eb8 ADD	X5, X1, X10

  (3596) 0x505ebc ADD	X7, X30, X17

  (3596) 0x505ec0 ADD	X3, X2, X11

  (3596) 0x505ec4 STR	X7, [X20, X18,LSL #3]

  (3596) 0x505ec8 MSUB	X8, X6, X25, X12

  (3596) 0x505ecc LDR	X13, [X20, X5,LSL #3]

  (3596) 0x505ed0 ADD	X9, X8, X6

  (3596) 0x505ed4 ADD	X27, X13, X17

  (3596) 0x505ed8 STR	X27, [X20, X5,LSL #3]

  (3596) 0x505edc LDR	X4, [X20, X3,LSL #3]

  (3596) 0x505ee0 ADD	X12, X4, X17

  (3596) 0x505ee4 STR	X12, [X20, X3,LSL #3]

  (3596) 0x505ee8 LDR	X14, [X20, X9,LSL #3]

  (3596) 0x505eec ADD	X10, X14, X17

  (3596) 0x505ef0 STR	X10, [X20, X9,LSL #3]

  (3596) 0x505ef4 CMP	X0, X15

  (3596) 0x505ef8 B.NE	505e84

(3591) 0x505efc HINT	#0

(3591) 0x505f00 BL	40f590

(3591) 0x505f04 LDR	X25, [SP, #120]

(3591) 0x505f08 SUB	X3, X19, #1

(3591) 0x505f0c CBNZ	X25, 505f90

(3591) 0x505f10 LDR	X28, [SP, #96]

(3591) 0x505f14 CMP	X28, X3

(3591) 0x505f18 B.GT	505f74

(3591) 0x505f1c SUB	X26, X28, #1

(3591) 0x505f20 ADD	X19, X22, #8

  (3593) 0x505f24 LDR	X15, [X19, X3,LSL #3]

  (3593) 0x505f28 LDR	X17, [X22, X3,LSL #3]

  (3593) 0x505f2c SUB	X11, X15, #1

  (3593) 0x505f30 CMP	X11, X17

  (3593) 0x505f34 B.LT	505f68

  (3593) 0x505f38 HINT	#0

  (3593) 0x505f3c HINT	#0

    (3594) 0x505f40 LDR	X0, [X23, X11,LSL #3]

    (3594) 0x505f44 SUB	X11, X11, #1

    (3594) 0x505f48 ADD	X16, X21, X0

    (3594) 0x505f4c LDR	X1, [X20, X16,LSL #3]

    (3594) 0x505f50 SUB	X18, X1, #1

    (3594) 0x505f54 STR	X18, [X20, X16,LSL #3]

    (3594) 0x505f58 STR	X3, [X24, X18,LSL #3]

    (3594) 0x505f5c LDR	X30, [X22, X3,LSL #3]

    (3594) 0x505f60 CMP	X30, X11

    (3594) 0x505f64 B.LE	505f40

  (3593) 0x505f68 SUB	X3, X3, #1

  (3593) 0x505f6c CMP	X3, X26

  (3593) 0x505f70 B.NE	505f24

  (3589) 0x505f74 LDP	X19, X20, [SP, #16]

  (3589) 0x505f78 LDP	X21, X22, [SP, #32]

  (3589) 0x505f7c LDP	X23, X24, [SP, #48]

  (3589) 0x505f80 LDP	X25, X26, [SP, #64]

  (3589) 0x505f84 LDP	X27, X28, [SP, #80]

  (3589) 0x505f88 LDP	X29, X30, [SP], #128

  (3589) 0x505f8c RET

  (3589) 0x505f90 LDR	X5, [SP, #96]

  (3589) 0x505f94 CMP	X5, X3

  (3589) 0x505f98 B.GT	505f74

(3591) 0x505f9c SUB	X6, X5, #1

(3591) 0x505fa0 ADD	X7, X22, #8

  (3590) 0x505fa4 LDR	X2, [X7, X3,LSL #3]

  (3590) 0x505fa8 LDR	X13, [X22, X3,LSL #3]

  (3590) 0x505fac SUB	X27, X2, #1

  (3590) 0x505fb0 CMP	X27, X13

  (3590) 0x505fb4 B.LT	505ff0

  (3590) 0x505fb8 HINT	#0

  (3590) 0x505fbc HINT	#0

    (3592) 0x505fc0 LDR	X8, [X23, X27,LSL #3]

    (3592) 0x505fc4 LDR	D0, [X28, X27,LSL #3]

    (3592) 0x505fc8 SUB	X27, X27, #1

    (3592) 0x505fcc ADD	X9, X21, X8

    (3592) 0x505fd0 LDR	X4, [X20, X9,LSL #3]

    (3592) 0x505fd4 SUB	X12, X4, #1

    (3592) 0x505fd8 STR	X12, [X20, X9,LSL #3]

    (3592) 0x505fdc STR	D0, [X26, X12,LSL #3]

    (3592) 0x505fe0 STR	X3, [X24, X12,LSL #3]

    (3592) 0x505fe4 LDR	X14, [X22, X3,LSL #3]

    (3592) 0x505fe8 CMP	X14, X27

    (3592) 0x505fec B.LE	505fc0

  (3590) 0x505ff0 SUB	X3, X3, #1

  (3590) 0x505ff4 CMP	X3, X6

  (3590) 0x505ff8 B.NE	505fa4

(3591) 0x505ffc LDP	X19, X20, [SP, #16]

(3591) 0x506000 LDP	X21, X22, [SP, #32]

(3591) 0x506004 LDP	X23, X24, [SP, #48]

(3591) 0x506008 LDP	X25, X26, [SP, #64]

(3591) 0x50600c LDP	X27, X28, [SP, #80]

(3591) 0x506010 LDP	X29, X30, [SP], #128

(3591) 0x506014 RET

(3591) 0x506018 ADRP	X4,

(3591) 0x50601c ADRP	X5,

(3591) 0x506020 LDR	X6, [X4, #4064]

(3591) 0x506024 ADRP	X7,

(3591) 0x506028 ADD	X2, X5, #1240

(3591) 0x50602c ADD	X1, X7, #2624

(3591) 0x506030 LDR	X0, [X6]

(3591) 0x506034 BL	516a84

(3591) 0x506038 ADRP	X8,

(3591) 0x50603c MOVZ	X3, #0

(3591) 0x506040 ADD	X0, X8, #1112

(3591) 0x506044 MOVZ	X2, #1

(3591) 0x506048 MOVZ	X1, #471

(3591) 0x50604c BL	51a420

(3591) 0x506050 LDR	X9, [SP, #96]

(3591) 0x506054 CMP	X9, #0

(3591) 0x506058 CCMP	X21, X9, #1, #10

(3591) 0x50605c B.GE	505ae4

(3591) 0x506060 ADRP	X10,

(3591) 0x506064 ADRP	X11,

(3591) 0x506068 LDR	X12, [X10, #4064]

(3591) 0x50606c ADRP	X13,

(3591) 0x506070 ADD	X2, X11, #1200

(3591) 0x506074 ADD	X1, X13, #2624

(3591) 0x506078 LDR	X0, [X12]

(3591) 0x50607c BL	516a84

(3591) 0x506080 ADRP	X14,

(3591) 0x506084 MOVZ	X3, #0

(3591) 0x506088 ADD	X0, X14, #1112

(3591) 0x50608c MOVZ	X2, #1

(3591) 0x506090 MOVZ	X1, #472

(3591) 0x506094 BL	51a420

(3591) 0x506098 CMP	X19, #0

(3591) 0x50609c CCMP	X21, X19, #1, #10

(3591) 0x5060a0 B.GE	505af0

(3591) 0x5060a4 ADRP	X15,

(3591) 0x5060a8 ADRP	X16,

(3591) 0x5060ac LDR	X17, [X15, #4064]

(3591) 0x5060b0 ADRP	X18,

(3591) 0x5060b4 ADD	X2, X16, #1080

(3591) 0x5060b8 ADD	X1, X18, #2624

(3591) 0x5060bc LDR	X0, [X17]

(3591) 0x5060c0 BL	516a84

(3591) 0x5060c4 ADRP	X1,

(3591) 0x5060c8 MOVZ	X3, #0

(3591) 0x5060cc ADD	X0, X1, #1112

(3591) 0x5060d0 MOVZ	X2, #1

(3591) 0x5060d4 MOVZ	X1, #473

(3591) 0x5060d8 BL	51a420

(3591) 0x5060dc B	505af0

(3591) 0x5060e0 ANDS	X30, X18, #4160

(3591) 0x5060e4 B.EQ	506140

(3591) 0x5060e8 CMP	X30, #1

(3591) 0x5060ec B.EQ	506118

(3591) 0x5060f0 CMP	X30, #2

(3591) 0x5060f4 B.NE	5062f8

(3591) 0x5060f8 SDIV	X3, X0, X25

(3591) 0x5060fc MSUB	X8, X3, X25, X0

(3591) 0x506100 ADD	X0, X0, #1

(3591) 0x506104 MADD	X4, X8, X27, X3

(3591) 0x506108 ADD	X11, X20, X4,LSL #3

(3591) 0x50610c LDR	X12, [X11]

(3591) 0x506110 ADD	X14, X12, X17

(3591) 0x506114 STR	X14, [X11]

(3591) 0x506118 SDIV	X10, X0, X25

(3591) 0x50611c MSUB	X1, X10, X25, X0

(3591) 0x506120 ADD	X0, X0, #1

(3591) 0x506124 MADD	X16, X1, X27, X10

(3591) 0x506128 ADD	X18, X20, X16,LSL #3

(3591) 0x50612c LDR	X30, [X18]

(3591) 0x506130 ADD	X5, X30, X17

(3591) 0x506134 STR	X5, [X18]

(3591) 0x506138 CMP	X0, X15

(3591) 0x50613c B.EQ	505f00

  (3595) 0x506140 SDIV	X6, X0, X25

  (3595) 0x506144 ADD	X7, X0, #1

  (3595) 0x506148 ADD	X13, X0, #2

  (3595) 0x50614c ADD	X2, X0, #3

  (3595) 0x506150 SDIV	X3, X7, X25

  (3595) 0x506154 SDIV	X8, X13, X25

  (3595) 0x506158 MSUB	X9, X6, X25, X0

  (3595) 0x50615c ADD	X0, X0, #4

  (3595) 0x506160 SDIV	X11, X2, X25

  (3595) 0x506164 MADD	X12, X9, X27, X6

  (3595) 0x506168 MSUB	X4, X3, X25, X7

  (3595) 0x50616c MSUB	X1, X8, X25, X13

  (3595) 0x506170 LDR	X10, [X20, X12,LSL #3]

  (3595) 0x506174 MADD	X14, X4, X27, X3

  (3595) 0x506178 MADD	X18, X1, X27, X8

  (3595) 0x50617c MSUB	X5, X11, X25, X2

  (3595) 0x506180 ADD	X16, X10, X17

  (3595) 0x506184 MADD	X7, X5, X27, X11

  (3595) 0x506188 STR	X16, [X20, X12,LSL #3]

  (3595) 0x50618c LDR	X30, [X20, X14,LSL #3]

  (3595) 0x506190 ADD	X6, X30, X17

  (3595) 0x506194 STR	X6, [X20, X14,LSL #3]

  (3595) 0x506198 LDR	X2, [X20, X18,LSL #3]

  (3595) 0x50619c ADD	X13, X2, X17

  (3595) 0x5061a0 STR	X13, [X20, X18,LSL #3]

  (3595) 0x5061a4 LDR	X3, [X20, X7,LSL #3]

  (3595) 0x5061a8 ADD	X8, X3, X17

  (3595) 0x5061ac STR	X8, [X20, X7,LSL #3]

  (3595) 0x5061b0 CMP	X0, X15

  (3595) 0x5061b4 B.NE	506140

(3591) 0x5061b8 B	505f00

(3591) 0x5061bc SDIV	X9, X21, X25

(3591) 0x5061c0 ADD	X0, X21, #1

(3591) 0x5061c4 MSUB	X4, X9, X25, X21

(3591) 0x5061c8 ADD	X12, X4, X9

(3591) 0x5061cc ADD	X14, X20, X12,LSL #3

(3591) 0x5061d0 LDR	X10, [X14]

(3591) 0x5061d4 ADD	X11, X10, X17

(3591) 0x5061d8 STR	X11, [X14]

(3591) 0x5061dc B	505e3c

(3591) 0x5061e0 SUB	X7, X25, X0

(3591) 0x5061e4 UBFM	X6, X27, #63, #62

(3591) 0x5061e8 ANDS	X12, X7, #4160

(3591) 0x5061ec SUB	X4, X6, #1

(3591) 0x5061f0 B.EQ	506278

(3591) 0x5061f4 CMP	X12, #1

(3591) 0x5061f8 B.EQ	50624c

(3591) 0x5061fc CMP	X12, #2

(3591) 0x506200 B.EQ	506228

(3591) 0x506204 SDIV	X8, X4, X25

(3591) 0x506208 MOVZ	X0, #2

(3591) 0x50620c MSUB	X13, X8, X25, X4

(3591) 0x506210 ADD	X4, X4, X27

(3591) 0x506214 MADD	X9, X13, X27, X8

(3591) 0x506218 ADD	X11, X20, X9,LSL #3

(3591) 0x50621c LDR	X10, [X11]

(3591) 0x506220 ADD	X2, X2, X10

(3591) 0x506224 STR	X2, [X11]

(3591) 0x506228 SDIV	X14, X4, X25

(3591) 0x50622c ADD	X0, X0, #1

(3591) 0x506230 MSUB	X1, X14, X25, X4

(3591) 0x506234 ADD	X4, X4, X27

(3591) 0x506238 MADD	X15, X1, X27, X14

(3591) 0x50623c ADD	X16, X20, X15,LSL #3

(3591) 0x506240 LDR	X17, [X16]

(3591) 0x506244 ADD	X2, X2, X17

(3591) 0x506248 STR	X2, [X16]

(3591) 0x50624c SDIV	X18, X4, X25

(3591) 0x506250 ADD	X0, X0, #1

(3591) 0x506254 MSUB	X30, X18, X25, X4

(3591) 0x506258 ADD	X4, X4, X27

(3591) 0x50625c MADD	X5, X30, X27, X18

(3591) 0x506260 ADD	X3, X20, X5,LSL #3

(3591) 0x506264 LDR	X6, [X3]

(3591) 0x506268 ADD	X2, X2, X6

(3591) 0x50626c STR	X2, [X3]

(3591) 0x506270 CMP	X25, X0

(3591) 0x506274 B.EQ	505de0

  (3597) 0x506278 SDIV	X7, X4, X25

  (3597) 0x50627c ADD	X13, X4, X27

  (3597) 0x506280 ADD	X0, X0, #4

  (3597) 0x506284 ADD	X9, X13, X27

  (3597) 0x506288 ADD	X8, X9, X27

  (3597) 0x50628c SDIV	X12, X13, X25

  (3597) 0x506290 SDIV	X15, X9, X25

  (3597) 0x506294 MSUB	X11, X7, X25, X4

  (3597) 0x506298 ADD	X4, X8, X27

  (3597) 0x50629c SDIV	X18, X8, X25

  (3597) 0x5062a0 MADD	X14, X11, X27, X7

  (3597) 0x5062a4 MSUB	X10, X12, X25, X13

  (3597) 0x5062a8 MSUB	X5, X15, X25, X9

  (3597) 0x5062ac LDR	X1, [X20, X14,LSL #3]

  (3597) 0x5062b0 MADD	X16, X10, X27, X12

  (3597) 0x5062b4 MADD	X3, X5, X27, X15

  (3597) 0x5062b8 ADD	X17, X2, X1

  (3597) 0x5062bc MSUB	X2, X18, X25, X8

  (3597) 0x5062c0 STR	X17, [X20, X14,LSL #3]

  (3597) 0x5062c4 LDR	X30, [X20, X16,LSL #3]

  (3597) 0x5062c8 MADD	X13, X2, X27, X18

  (3597) 0x5062cc ADD	X6, X17, X30

  (3597) 0x5062d0 STR	X6, [X20, X16,LSL #3]

  (3597) 0x5062d4 LDR	X7, [X20, X3,LSL #3]

  (3597) 0x5062d8 ADD	X9, X6, X7

  (3597) 0x5062dc STR	X9, [X20, X3,LSL #3]

  (3597) 0x5062e0 LDR	X8, [X20, X13,LSL #3]

  (3597) 0x5062e4 ADD	X2, X9, X8

  (3597) 0x5062e8 STR	X2, [X20, X13,LSL #3]

  (3597) 0x5062ec CMP	X25, X0

  (3597) 0x5062f0 B.NE	506278

(3591) 0x5062f4 B	505de0

(3591) 0x5062f8 SDIV	X5, X21, X25

(3591) 0x5062fc ADD	X0, X21, #1

(3591) 0x506300 MSUB	X2, X5, X25, X21

(3591) 0x506304 MADD	X6, X2, X27, X5

(3591) 0x506308 ADD	X7, X20, X6,LSL #3

(3591) 0x50630c LDR	X13, [X7]

(3591) 0x506310 ADD	X9, X13, X17

(3591) 0x506314 STR	X9, [X7]

(3591) 0x506318 B	5060f8

0x50631c HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	csr_matop.c:380-560
Module	exec

The function is defined in:

/usr/include/aarch64-linux-gnu/bits/string_fortified.h:59
/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:380,463-476,483-485,493-532,539-560

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 5.50 to 1.37 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.50 to 2.00 cycles (2.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 96 bytes. The binary function is storing 120 bytes.

General properties

nb instructions	33
loop length	132
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	5.50	5.17	5.33	4.50	4.50
cycles	3.00	3.00	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	5.50	5.17	5.33	4.50	4.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.00
Overall L1	5.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.50 cycles. At this rate:

18% of peak load performance is reached (17.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
45% of peak store performance is reached (21.82 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 505a64

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #896]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X19, X1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X1, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X28, X22, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X21, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X27, X26, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X20, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
BL 519560 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 519580 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X2, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 509ae0 <hypre_CSRMatrixGetLoadBalancedPartitionBegin>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X3, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X3, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 509b84 <hypre_CSRMatrixGetLoadBalancedPartitionEnd>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X0, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 506018 <hypre_CSRMatrixTranspose._omp_fn.0+0x5b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X21, X9, #1, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.LT 506060 <hypre_CSRMatrixTranspose._omp_fn.0+0x5fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Source file and lines	csr_matop.c:380-560
Module	exec

The function is defined in:

/usr/include/aarch64-linux-gnu/bits/string_fortified.h:59
/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:380,463-476,483-485,493-532,539-560

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.50 to 2.00 cycles (2.75x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 96 bytes. The binary function is storing 120 bytes.

General properties

nb instructions	33
loop length	132
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	5.50	5.17	5.33	4.50	4.50
cycles	3.00	3.00	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	5.50	5.17	5.33	4.50	4.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.00
Overall L1	5.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.50 cycles. At this rate:

18% of peak load performance is reached (17.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
45% of peak store performance is reached (21.82 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 505a64

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #896]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X19, X1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X1, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X28, X22, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X21, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X27, X26, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X20, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
BL 519560 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 519580 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X2, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 509ae0 <hypre_CSRMatrixGetLoadBalancedPartitionBegin>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X3, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X3, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 509b84 <hypre_CSRMatrixGetLoadBalancedPartitionEnd>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X0, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 506018 <hypre_CSRMatrixTranspose._omp_fn.0+0x5b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X21, X9, #1, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.LT 506060 <hypre_CSRMatrixTranspose._omp_fn.0+0x5fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Name	Coverage (%)	Time (s)
▼hypre_CSRMatrixTranspose._omp_fn.0–	0.29	0.11
▼Loop 3591 - csr_matop.c:380-560 - exec–	0	0
○Loop 3600 - csr_matop.c:483-485 - exec	0.01	0.01
○Loop 3598 - csr_matop.c:380-513 - exec	0	0
▼Loop 3593 - csr_matop.c:553-560 - exec–	0	0
○Loop 3594 - csr_matop.c:554-560 - exec	0	0
▼Loop 3590 - csr_matop.c:540-548 - exec–	0	0.01
○Loop 3592 - csr_matop.c:541-548 - exec	0.28	0.09
○Loop 3599 - csr_matop.c:380-500 - exec	0	0
○Loop 3597 - csr_matop.c:380-513 - exec	0	0
○Loop 3595 - csr_matop.c:380-527 - exec	0	0.01
○Loop 3596 - csr_matop.c:380-527 - exec	0	0
○Loop 3589 - csr_matop.c:463-540 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code