OV - exec - Function hypre_CSRMatrixMultiply._omp

	Function: hypre_CSRMatrixMultiply._omp_fn.0	Module: exec	Source: csr_matop.c:185-302 [...]	Coverage: 0.71%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c: 185 - 302

--------------------------------------------------------------------------------

185: #pragma omp parallel private(ia, ib, ic, ja, jb, num_nonzeros, row_start, counter, a_entry, b_entry)

[...]

192:     ii = hypre_GetThreadNum();

193:     num_threads = hypre_NumActiveThreads();

194:

195:    size = nrows_A/num_threads;

196:    rest = nrows_A - size*num_threads;

197:     if (ii < rest)

198:     {

199:        ns = ii*size+ii;

200:        ne = (ii+1)*size+ii+1;

201:     }

202:     else

203:     {

204:        ns = ii*size+rest;

205:        ne = (ii+1)*size+rest;

206:     }

207:

208:     B_marker = hypre_CTAlloc(HYPRE_Int, ncols_B);

209:

210:     for (ib = 0; ib < ncols_B; ib++)

211:       B_marker[ib] = -1;

212:

213:     num_nonzeros = 0;

214:     for (ic = ns; ic < ne; ic++)

215:     {

216:         C_i[ic] = num_nonzeros;

217: 	if (allsquare)

218:         {

219:            B_marker[ic] = ic;

220:            num_nonzeros++;

221:         }

222: 	for (ia = A_i[ic]; ia < A_i[ic+1]; ia++)

223: 	{

224: 	   ja = A_j[ia];

225: 	   for (ib = B_i[ja]; ib < B_i[ja+1]; ib++)

226: 	   {

227: 	      jb = B_j[ib];

228: 	      if (B_marker[jb] != ic)

229: 	      {

230: 	 	 B_marker[jb] = ic;

231: 		 num_nonzeros++;

232: 	      }

233: 	   }

234:    	}

235:    }

236:    jj_count[ii] = num_nonzeros;

237:

238: #ifdef HYPRE_USING_OPENMP

239: #pragma omp barrier

240: #endif

241:

242:     if (ii)

243:     {

244:        jj = jj_count[0];

245:        for (i1 = 1; i1 < ii; i1++)

246:           jj += jj_count[i1];

247:

248:        for (i1 = ns; i1 < ne; i1++)

249:           C_i[i1] += jj;

250:     }

251:     else

252:     {

253:        C_i[nrows_A] = 0;

254:        for (i1 = 0; i1 < num_threads; i1++)

255:           C_i[nrows_A] += jj_count[i1];

256:

257:        C = hypre_CSRMatrixCreate(nrows_A, ncols_B, C_i[nrows_A]);

258:        hypre_CSRMatrixI(C) = C_i;

259:        hypre_CSRMatrixInitialize(C);

260:        C_j = hypre_CSRMatrixJ(C);

261:        C_data = hypre_CSRMatrixData(C);

262:     }

263:

264: #ifdef HYPRE_USING_OPENMP

265: #pragma omp barrier

266: #endif

267:

268:    for (ib = 0; ib < ncols_B; ib++)

269:       B_marker[ib] = -1;

270:

271:    counter = C_i[ns];

272:    for (ic = ns; ic < ne; ic++)

273:    {

274:       row_start = C_i[ic];

275:       if (allsquare)

276:       {

277:          B_marker[ic] = counter;

278:          C_data[counter] = 0;

279:          C_j[counter] = ic;

280:          counter++;

281:       }

282:       for (ia = A_i[ic]; ia < A_i[ic+1]; ia++)

283:       {

284: 	 ja = A_j[ia];

285: 	 a_entry = A_data[ia];

286: 	 for (ib = B_i[ja]; ib < B_i[ja+1]; ib++)

287: 	 {

288: 	    jb = B_j[ib];

289: 	    b_entry = B_data[ib];

290: 	    if (B_marker[jb] < row_start)

291: 	    {

292: 		B_marker[jb] = counter;

293: 		C_j[B_marker[jb]] = jb;

294: 		C_data[B_marker[jb]] = a_entry*b_entry;

295: 		counter++;

296: 	    }

297: 	    else

298: 		C_data[B_marker[jb]] += a_entry*b_entry;

299: 	}

300:       }

301:    }

302:    hypre_TFree(B_marker);

0x5053c0 STP	X29, X30, [SP, #864]!

0x5053c4 ADD	X29, SP, #0

0x5053c8 STP	X19, X20, [SP, #16]

0x5053cc STP	X21, X22, [SP, #32]

0x5053d0 ORR	X22, XZR, X0

0x5053d4 STP	X25, X26, [SP, #64]

0x5053d8 STP	X27, X28, [SP, #80]

0x5053dc LDP	X5, X8, [X0]

0x5053e0 LDP	X28, X19, [X0, #16]

0x5053e4 LDP	X26, X27, [X0, #32]

0x5053e8 LDP	X20, X0, [X0, #48]

0x5053ec STP	X23, X24, [SP, #48]

0x5053f0 STP	X0, X19, [SP, #96]

0x5053f4 STP	X8, X5, [SP, #128]

0x5053f8 LDR	X23, [X22, #80]

0x5053fc LDP	X25, X21, [X22, #96]

0x505400 BL	519580

0x505404 STR	X0, [SP, #120]

0x505408 BL	519560

0x50540c SDIV	X6, X19, X0

0x505410 LDP	X12, X2, [SP, #120]

0x505414 STR	X0, [SP, #112]

0x505418 LDR	X3, [SP, #136]

0x50541c MSUB	X7, X6, X0, X19

0x505420 CMP	X7, X12

0x505424 B.LE	505a48

0x505428 MADD	X10, X12, X6, XZR

0x50542c ADD	X11, X6, X10

0x505430 ADD	X13, X12, X10

0x505434 ADD	X14, X11, X12

0x505438 ADD	X24, X14, #1

0x50543c MOVZ	X1, #8

0x505440 LDR	X0, [SP, #96]

0x505444 STP	X2, X3, [SP, #120]

0x505448 STP	X12, X13, [SP, #136]

0x50544c BL	51674c

0x505450 LDR	X15, [SP, #96]

0x505454 ORR	X19, XZR, X0

0x505458 LDP	X18, X5, [SP, #120]

0x50545c LDP	X8, X12, [SP, #136]

0x505460 CMP	X15, #0

0x505464 B.LE	505484

0x505468 UBFM	X2, X15, #61, #60

0x50546c MOVZ	W1, #255

0x505470 STP	X18, X5, [SP, #120]

0x505474 STP	X8, X12, [SP, #136]

0x505478 BL	40f370

0x50547c LDP	X18, X5, [SP, #120]

0x505480 LDP	X8, X12, [SP, #136]

0x505484 ORR	X10, XZR, X12

0x505488 MOVZ	X17, #0

0x50548c ADD	X16, X18, #8

0x505490 CMP	X12, X24

0x505494 B.GE	505524

0x505498 HINT	#0

0x50549c HINT	#0

(3586) 0x5054a0 STR	X17, [X23, X10,LSL #3]

(3586) 0x5054a4 CBZ	X25, 5054b0

(3586) 0x5054a8 ADD	X17, X17, #1

(3586) 0x5054ac STR	X10, [X19, X10,LSL #3]

(3586) 0x5054b0 LDR	X11, [X18, X10,LSL #3]

(3586) 0x5054b4 LDR	X9, [X16, X10,LSL #3]

(3586) 0x5054b8 CMP	X11, X9

(3586) 0x5054bc B.GE	505518

  (3587) 0x5054c0 LDR	X30, [X28, X11,LSL #3]

  (3587) 0x5054c4 UBFM	X2, X30, #61, #60

  (3587) 0x5054c8 LDR	X0, [X27, X30,LSL #3]

  (3587) 0x5054cc ADD	X6, X2, #8

  (3587) 0x5054d0 LDR	X3, [X27, X6]

  (3587) 0x5054d4 ADD	X7, X27, X6

  (3587) 0x5054d8 CMP	X0, X3

  (3587) 0x5054dc B.GE	50550c

    (3588) 0x5054e0 LDR	X1, [X20, X0,LSL #3]

    (3588) 0x5054e4 LDR	X4, [X19, X1,LSL #3]

    (3588) 0x5054e8 CMP	X4, X10

    (3588) 0x5054ec B.EQ	505864

    (3588) 0x5054f0 STR	X10, [X19, X1,LSL #3]

    (3588) 0x5054f4 ADD	X0, X0, #1

    (3588) 0x5054f8 ADD	X17, X17, #1

    (3588) 0x5054fc LDR	X3, [X7]

    (3588) 0x505500 CMP	X0, X3

    (3588) 0x505504 B.LT	5054e0

  (3587) 0x505508 LDR	X9, [X16, X10,LSL #3]

  (3587) 0x50550c ADD	X11, X11, #1

  (3587) 0x505510 CMP	X11, X9

  (3587) 0x505514 B.LT	5054c0

(3586) 0x505518 ADD	X10, X10, #1

(3586) 0x50551c CMP	X24, X10

(3586) 0x505520 B.NE	5054a0

0x505524 UBFM	X13, X8, #61, #60

0x505528 STR	X17, [X21, X8,LSL #3]

0x50552c STP	X18, X5, [SP, #136]

0x505530 STP	X13, X8, [SP, #120]

0x505534 STR	X12, [SP, #152]

0x505538 BL	40f590

0x50553c LDP	X14, X12, [SP, #120]

0x505540 LDP	X15, X18, [SP, #136]

0x505544 LDR	X5, [SP, #152]

0x505548 CBZ	X12, 5058cc

0x50554c ADD	X16, X21, X14

0x505550 LDR	X1, [X21], #8

0x505554 CMP	X12, #1

0x505558 B.LE	505630

0x50555c SUB	X30, X16, X21

0x505560 SUB	X17, X30, #8

0x505564 UBFM	X2, X17, #3, #63

0x505568 ADD	X6, X2, #1

0x50556c ANDS	X7, X6, #4224

0x505570 B.EQ	5055e4

0x505574 CMP	X7, #1

0x505578 B.EQ	5055d4

0x50557c CMP	X7, #2

0x505580 B.EQ	5055cc

0x505584 CMP	X7, #3

0x505588 B.EQ	5055c4

0x50558c CMP	X7, #4

0x505590 B.EQ	5055bc

0x505594 CMP	X7, #5

0x505598 B.EQ	5055b4

0x50559c CMP	X7, #6

0x5055a0 B.EQ	5055ac

0x5055a4 LDR	X4, [X21], #8

0x5055a8 ADD	X1, X1, X4

0x5055ac LDR	X0, [X21], #8

0x5055b0 ADD	X1, X1, X0

0x5055b4 LDR	X3, [X21], #8

0x5055b8 ADD	X1, X1, X3

0x5055bc LDR	X9, [X21], #8

0x5055c0 ADD	X1, X1, X9

0x5055c4 LDR	X11, [X21], #8

0x5055c8 ADD	X1, X1, X11

0x5055cc LDR	X10, [X21], #8

0x5055d0 ADD	X1, X1, X10

0x5055d4 LDR	X13, [X21], #8

0x5055d8 ADD	X1, X1, X13

0x5055dc CMP	X16, X21

0x5055e0 B.EQ	505630

(3585) 0x5055e4 ORR	X14, XZR, X21

(3585) 0x5055e8 LDR	X17, [X21, #8]

(3585) 0x5055ec LDP	X2, X6, [X21, #24]

(3585) 0x5055f0 ADD	X21, X21, #64

(3585) 0x5055f4 LDR	X12, [X14], #8

(3585) 0x5055f8 LDUR	X11, [X21, #488]

(3585) 0x5055fc LDUR	X7, [X21, #496]

(3585) 0x505600 ADD	X8, X1, X12

(3585) 0x505604 LDR	X30, [X14, #8]

(3585) 0x505608 ADD	X4, X8, X17

(3585) 0x50560c LDUR	X10, [X21, #504]

(3585) 0x505610 ADD	X0, X4, X30

(3585) 0x505614 ADD	X3, X0, X2

(3585) 0x505618 ADD	X9, X3, X6

(3585) 0x50561c ADD	X13, X9, X11

(3585) 0x505620 ADD	X1, X13, X7

(3585) 0x505624 ADD	X1, X1, X10

(3585) 0x505628 CMP	X16, X21

(3585) 0x50562c B.NE	5055e4

0x505630 CMP	X5, X24

0x505634 B.GE	505890

0x505638 ADD	X16, X23, X24,LSL #3

0x50563c UBFM	X21, X5, #61, #60

0x505640 ADD	X0, X23, X21

0x505644 SUB	X14, X16, X0

0x505648 SUB	X12, X14, #8

0x50564c UBFM	X30, X12, #3, #63

0x505650 ADD	X17, X30, #1

0x505654 ANDS	X2, X17, #4224

0x505658 B.EQ	5056e8

0x50565c CMP	X2, #1

0x505660 B.EQ	5056d4

0x505664 CMP	X2, #2

0x505668 B.EQ	5056c8

0x50566c CMP	X2, #3

0x505670 B.EQ	5056bc

0x505674 CMP	X2, #4

0x505678 B.EQ	5056b0

0x50567c CMP	X2, #5

0x505680 B.EQ	5056a4

0x505684 CMP	X2, #6

0x505688 B.EQ	505698

0x50568c LDR	X6, [X0]

0x505690 ADD	X7, X6, X1

0x505694 STR	X7, [X0], #8

0x505698 LDR	X4, [X0]

0x50569c ADD	X3, X4, X1

0x5056a0 STR	X3, [X0], #8

0x5056a4 LDR	X9, [X0]

0x5056a8 ADD	X11, X9, X1

0x5056ac STR	X11, [X0], #8

0x5056b0 LDR	X10, [X0]

0x5056b4 ADD	X13, X10, X1

0x5056b8 STR	X13, [X0], #8

0x5056bc LDR	X8, [X0]

0x5056c0 ADD	X14, X8, X1

0x5056c4 STR	X14, [X0], #8

0x5056c8 LDR	X12, [X0]

0x5056cc ADD	X30, X12, X1

0x5056d0 STR	X30, [X0], #8

0x5056d4 LDR	X17, [X0]

0x5056d8 ADD	X2, X17, X1

0x5056dc STR	X2, [X0], #8

0x5056e0 CMP	X16, X0

0x5056e4 B.EQ	505748

(3584) 0x5056e8 LDR	X7, [X0]

(3584) 0x5056ec ORR	X6, XZR, X0

(3584) 0x5056f0 ADD	X4, X7, X1

(3584) 0x5056f4 STR	X4, [X6], #8

(3584) 0x5056f8 LDR	X3, [X0, #8]

(3584) 0x5056fc ADD	X9, X3, X1

(3584) 0x505700 STR	X9, [X0, #8]

(3584) 0x505704 LDR	X11, [X6, #8]

(3584) 0x505708 ADD	X10, X11, X1

(3584) 0x50570c STR	X10, [X6, #8]

(3584) 0x505710 LDP	X13, X8, [X0, #24]

(3584) 0x505714 LDP	X14, X30, [X0, #40]

(3584) 0x505718 ADD	X17, X13, X1

(3584) 0x50571c ADD	X12, X8, X1

(3584) 0x505720 LDR	X7, [X0, #56]

(3584) 0x505724 ADD	X2, X14, X1

(3584) 0x505728 ADD	X6, X30, X1

(3584) 0x50572c STP	X17, X12, [X0, #24]

(3584) 0x505730 STP	X2, X6, [X0, #40]

(3584) 0x505734 ADD	X0, X0, #64

(3584) 0x505738 ADD	X4, X7, X1

(3584) 0x50573c STUR	X4, [X0, #504]

(3584) 0x505740 CMP	X16, X0

(3584) 0x505744 B.NE	5056e8

0x505748 STP	X15, X18, [SP, #104]

0x50574c STR	X5, [SP, #120]

0x505750 BL	40f590

0x505754 LDP	X15, X18, [SP, #96]

0x505758 LDP	X5, X8, [SP, #112]

0x50575c CMP	X15, #0

0x505760 B.LE	505a5c

0x505764 MOVZ	X11, #8

0x505768 MOVZ	W1, #255

0x50576c STP	X18, X5, [SP, #104]

0x505770 ORR	X0, XZR, X19

0x505774 LDR	X16, [SP, #96]

0x505778 STR	X8, [SP, #120]

0x50577c CMP	X16, #0

0x505780 UBFM	X9, X16, #61, #60

0x505784 CSEL	X2, X9, X11, #12

0x505788 BL	40f370

0x50578c LDP	X18, X5, [SP, #104]

0x505790 LDR	X8, [SP, #120]

0x505794 LDR	X21, [X23, X8,LSL #3]

0x505798 CMP	X8, X24

0x50579c B.GE	5058ac

0x5057a0 ORR	X13, XZR, X21

0x5057a4 ADD	X15, X18, #8

0x5057a8 LDR	X4, [X22, #72]

0x5057ac LDR	X0, [X22, #88]

(3580) 0x5057b0 CBZ	X25, 5057c4

(3580) 0x5057b4 STR	X21, [X19, X8,LSL #3]

(3580) 0x5057b8 STR	XZR, [X4, X21,LSL #3]

(3580) 0x5057bc STR	X8, [X0, X21,LSL #3]

(3580) 0x5057c0 ADD	X21, X21, #1

(3580) 0x5057c4 LDR	X14, [X18, X8,LSL #3]

(3580) 0x5057c8 LDR	X16, [X15, X8,LSL #3]

(3580) 0x5057cc CMP	X14, X16

(3580) 0x5057d0 B.GE	505850

(3580) 0x5057d4 HINT	#0

(3580) 0x5057d8 HINT	#0

(3580) 0x5057dc HINT	#0

  (3581) 0x5057e0 LDR	X22, [X28, X14,LSL #3]

  (3581) 0x5057e4 LDR	D2, [X5, X14,LSL #3]

  (3581) 0x5057e8 UBFM	X10, X22, #61, #60

  (3581) 0x5057ec LDR	X2, [X27, X22,LSL #3]

  (3581) 0x5057f0 ADD	X30, X10, #8

  (3581) 0x5057f4 LDR	X7, [X27, X30]

  (3581) 0x5057f8 ADD	X17, X27, X30

  (3581) 0x5057fc CMP	X2, X7

  (3581) 0x505800 B.GE	505844

    (3582) 0x505804 LDR	X1, [X20, X2,LSL #3]

    (3582) 0x505808 LDR	D0, [X26, X2,LSL #3]

    (3582) 0x50580c LDR	X12, [X19, X1,LSL #3]

    (3582) 0x505810 FMUL	D3, D2, D0

    (3582) 0x505814 CMP	X12, X13

    (3582) 0x505818 B.GE	505874

    (3582) 0x50581c STR	X21, [X19, X1,LSL #3]

    (3582) 0x505820 ADD	X2, X2, #1

    (3582) 0x505824 STR	X1, [X0, X21,LSL #3]

    (3582) 0x505828 ADD	X21, X21, #1

    (3582) 0x50582c LDR	X6, [X19, X1,LSL #3]

    (3582) 0x505830 LDR	X7, [X17]

    (3582) 0x505834 STR	D3, [X4, X6,LSL #3]

    (3582) 0x505838 CMP	X7, X2

    (3582) 0x50583c B.GT	505804

  (3581) 0x505840 LDR	X16, [X15, X8,LSL #3]

  (3581) 0x505844 ADD	X14, X14, #1

  (3581) 0x505848 CMP	X14, X16

  (3581) 0x50584c B.LT	5057e0

(3580) 0x505850 ADD	X8, X8, #1

(3580) 0x505854 CMP	X24, X8

(3580) 0x505858 B.LE	5058ac

(3580) 0x50585c LDR	X13, [X23, X8,LSL #3]

(3580) 0x505860 B	5057b0

    (3588) 0x505864 ADD	X0, X0, #1

    (3588) 0x505868 CMP	X0, X3

    (3588) 0x50586c B.LT	5054e0

  (3587) 0x505870 B	505508

    (3582) 0x505874 LDR	D1, [X4, X12,LSL #3]

    (3582) 0x505878 ADD	X2, X2, #1

    (3582) 0x50587c FADD	D4, D1, D3

    (3582) 0x505880 STR	D4, [X4, X12,LSL #3]

    (3582) 0x505884 CMP	X7, X2

    (3582) 0x505888 B.GT	505804

  (3581) 0x50588c B	505840

0x505890 STP	X15, X18, [SP, #104]

0x505894 STR	X5, [SP, #120]

0x505898 BL	40f590

0x50589c LDP	X21, X18, [SP, #96]

0x5058a0 LDP	X5, X8, [SP, #112]

0x5058a4 CMP	X21, #0

0x5058a8 B.GT	505764

0x5058ac ORR	X0, XZR, X19

0x5058b0 LDP	X19, X20, [SP, #16]

0x5058b4 LDP	X21, X22, [SP, #32]

0x5058b8 LDP	X23, X24, [SP, #48]

0x5058bc LDP	X25, X26, [SP, #64]

0x5058c0 LDP	X27, X28, [SP, #80]

0x5058c4 LDP	X29, X30, [SP], #160

0x5058c8 B	516820

0x5058cc LDR	X8, [SP, #104]

0x5058d0 LDR	X17, [SP, #112]

0x5058d4 STR	XZR, [X23, X8,LSL #3]

0x5058d8 ADD	X16, X23, X8,LSL #3

0x5058dc ADD	X30, X21, X17,LSL #3

0x5058e0 CMP	X17, #0

0x5058e4 B.LE	5059f8

0x5058e8 SUB	X2, X30, X21

0x5058ec SUB	X6, X2, #8

0x5058f0 UBFM	X7, X6, #3, #63

0x5058f4 ADD	X1, X7, #1

0x5058f8 ANDS	X4, X1, #4224

0x5058fc B.EQ	505988

0x505900 CMP	X4, #1

0x505904 B.EQ	505974

0x505908 CMP	X4, #2

0x50590c B.EQ	505968

0x505910 CMP	X4, #3

0x505914 B.EQ	50595c

0x505918 CMP	X4, #4

0x50591c B.EQ	505950

0x505920 CMP	X4, #5

0x505924 B.EQ	505944

0x505928 CMP	X4, #6

0x50592c B.EQ	505938

0x505930 LDR	X12, [X21], #8

0x505934 STR	X12, [X16]

0x505938 LDR	X0, [X21], #8

0x50593c ADD	X12, X12, X0

0x505940 STR	X12, [X16]

0x505944 LDR	X3, [X21], #8

0x505948 ADD	X12, X12, X3

0x50594c STR	X12, [X16]

0x505950 LDR	X9, [X21], #8

0x505954 ADD	X12, X12, X9

0x505958 STR	X12, [X16]

0x50595c LDR	X11, [X21], #8

0x505960 ADD	X12, X12, X11

0x505964 STR	X12, [X16]

0x505968 LDR	X10, [X21], #8

0x50596c ADD	X12, X12, X10

0x505970 STR	X12, [X16]

0x505974 LDR	X13, [X21], #8

0x505978 ADD	X12, X12, X13

0x50597c STR	X12, [X16]

0x505980 CMP	X30, X21

0x505984 B.EQ	5059f8

(3583) 0x505988 ORR	X14, XZR, X21

(3583) 0x50598c ADD	X21, X21, #64

(3583) 0x505990 LDR	X8, [X14], #8

(3583) 0x505994 ADD	X17, X12, X8

(3583) 0x505998 STR	X17, [X16]

(3583) 0x50599c LDUR	X2, [X21, #456]

(3583) 0x5059a0 ADD	X6, X17, X2

(3583) 0x5059a4 STR	X6, [X16]

(3583) 0x5059a8 LDR	X7, [X14, #8]

(3583) 0x5059ac ADD	X1, X6, X7

(3583) 0x5059b0 STR	X1, [X16]

(3583) 0x5059b4 LDUR	X4, [X21, #472]

(3583) 0x5059b8 ADD	X0, X1, X4

(3583) 0x5059bc STR	X0, [X16]

(3583) 0x5059c0 LDUR	X3, [X21, #480]

(3583) 0x5059c4 ADD	X9, X0, X3

(3583) 0x5059c8 STR	X9, [X16]

(3583) 0x5059cc LDUR	X11, [X21, #488]

(3583) 0x5059d0 ADD	X10, X9, X11

(3583) 0x5059d4 STR	X10, [X16]

(3583) 0x5059d8 LDUR	X13, [X21, #496]

(3583) 0x5059dc ADD	X14, X10, X13

(3583) 0x5059e0 STR	X14, [X16]

(3583) 0x5059e4 LDUR	X12, [X21, #504]

(3583) 0x5059e8 ADD	X12, X14, X12

(3583) 0x5059ec STR	X12, [X16]

(3583) 0x5059f0 CMP	X30, X21

(3583) 0x5059f4 B.NE	505988

0x5059f8 LDP	X21, X0, [SP, #96]

0x5059fc ORR	X2, XZR, X12

0x505a00 STP	X15, X18, [SP, #112]

0x505a04 ORR	X1, XZR, X21

0x505a08 STR	X5, [SP, #128]

0x505a0c BL	507660

0x505a10 STR	X23, [X0]

0x505a14 STR	X0, [X22, #64]

0x505a18 BL	507740

0x505a1c LDR	X18, [X22, #64]

0x505a20 LDR	X5, [X18, #8]

0x505a24 LDR	X8, [X18, #48]

0x505a28 STR	X5, [X22, #88]

0x505a2c STR	X8, [X22, #72]

0x505a30 BL	40f590

0x505a34 CMP	X21, #0

0x505a38 LDP	X18, X5, [SP, #112]

0x505a3c LDR	X8, [SP, #128]

0x505a40 B.GT	505764

0x505a44 B	505794

0x505a48 MADD	X4, X12, X6, XZR

0x505a4c ADD	X9, X6, X4

0x505a50 ADD	X13, X7, X4

0x505a54 ADD	X24, X9, X7

0x505a58 B	50543c

0x505a5c LDR	X21, [X23, X21]

0x505a60 B	5057a0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	csr_matop.c:185-302
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:185,192-302.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 36.50 to 10.00 cycles (3.65x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 36.50 to 5.50 cycles (6.64x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 712 bytes. The binary function is storing 504 bytes.

General properties

nb instructions	265
loop length	1060
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

32.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	25.00	25.00	32.75	32.75	32.75	32.75	0.00	0.00	0.00	0.00	36.50	36.17	36.33	22.50	22.50
cycles	25.00	25.00	32.75	32.75	32.75	32.75	0.00	0.00	0.00	0.00	36.50	36.17	36.33	22.50	22.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	32.88
Overall L1	36.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 36.50 cycles. At this rate:

20% of peak load performance is reached (19.51 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
28% of peak store performance is reached (13.81 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 5053c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #864]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X5, X8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X19, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X27, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X20, X0, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X0, X19, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X8, X5, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X23, [X22, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X25, X21, [X22, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
BL 519580 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 519560 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SDIV X6, X19, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
LDP X12, X2, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X0, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MSUB X7, X6, X0, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X7, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 505a48 <hypre_CSRMatrixMultiply._omp_fn.0+0x688>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X10, X12, X6, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X11, X6, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X12, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X24, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X2, X3, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X12, X13, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 51674c <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X18, X5, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X8, X12, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 505484 <hypre_CSRMatrixMultiply._omp_fn.0+0xc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X2, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #255	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X18, X5, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X8, X12, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f370 <@plt_start@+0x180>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X18, X5, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X8, X12, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X10, XZR, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X17, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X12, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 505524 <hypre_CSRMatrixMultiply._omp_fn.0+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
UBFM X13, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X17, [X21, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X18, X5, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X13, X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f590 <@plt_start@+0x3a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X14, X12, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X15, X18, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X5, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X12, 5058cc <hypre_CSRMatrixMultiply._omp_fn.0+0x50c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X16, X21, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X21], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 505630 <hypre_CSRMatrixMultiply._omp_fn.0+0x270>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X30, X16, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X17, X30, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X2, X17, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X7, X6, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 5055e4 <hypre_CSRMatrixMultiply._omp_fn.0+0x224>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 5055d4 <hypre_CSRMatrixMultiply._omp_fn.0+0x214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X7, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 5055cc <hypre_CSRMatrixMultiply._omp_fn.0+0x20c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X7, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 5055c4 <hypre_CSRMatrixMultiply._omp_fn.0+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X7, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 5055bc <hypre_CSRMatrixMultiply._omp_fn.0+0x1fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X7, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 5055b4 <hypre_CSRMatrixMultiply._omp_fn.0+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X7, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 5055ac <hypre_CSRMatrixMultiply._omp_fn.0+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X4, [X21], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X21], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X3, [X21], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X21], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X21], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X21], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X13, [X21], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X16, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 505630 <hypre_CSRMatrixMultiply._omp_fn.0+0x270>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X5, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 505890 <hypre_CSRMatrixMultiply._omp_fn.0+0x4d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X16, X23, X24,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X21, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X23, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X14, X16, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X12, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X30, X12, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X2, X17, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 5056e8 <hypre_CSRMatrixMultiply._omp_fn.0+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 5056d4 <hypre_CSRMatrixMultiply._omp_fn.0+0x314>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 5056c8 <hypre_CSRMatrixMultiply._omp_fn.0+0x308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 5056bc <hypre_CSRMatrixMultiply._omp_fn.0+0x2fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 5056b0 <hypre_CSRMatrixMultiply._omp_fn.0+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 5056a4 <hypre_CSRMatrixMultiply._omp_fn.0+0x2e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 505698 <hypre_CSRMatrixMultiply._omp_fn.0+0x2d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X6, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X7, X6, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X7, [X0], #8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X4, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X3, [X0], #8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X9, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X11, [X0], #8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X10, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X13, [X0], #8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X8, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X14, [X0], #8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X30, X12, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X30, [X0], #8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X17, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X17, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X2, [X0], #8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X16, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 505748 <hypre_CSRMatrixMultiply._omp_fn.0+0x388>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X15, X18, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X5, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f590 <@plt_start@+0x3a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X15, X18, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X5, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 505a5c <hypre_CSRMatrixMultiply._omp_fn.0+0x69c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #255	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X18, X5, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X16, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
UBFM X9, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X2, X9, X11, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f370 <@plt_start@+0x180>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X18, X5, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X23, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 5058ac <hypre_CSRMatrixMultiply._omp_fn.0+0x4ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X13, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X4, [X22, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X22, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X15, X18, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X5, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f590 <@plt_start@+0x3a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X21, X18, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X5, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X21, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 505764 <hypre_CSRMatrixMultiply._omp_fn.0+0x3a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #160	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 516820 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X23, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X16, X23, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X30, X21, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X17, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 5059f8 <hypre_CSRMatrixMultiply._omp_fn.0+0x638>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X2, X30, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X7, X6, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X4, X1, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 505988 <hypre_CSRMatrixMultiply._omp_fn.0+0x5c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 505974 <hypre_CSRMatrixMultiply._omp_fn.0+0x5b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 505968 <hypre_CSRMatrixMultiply._omp_fn.0+0x5a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X4, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 50595c <hypre_CSRMatrixMultiply._omp_fn.0+0x59c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X4, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 505950 <hypre_CSRMatrixMultiply._omp_fn.0+0x590>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X4, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 505944 <hypre_CSRMatrixMultiply._omp_fn.0+0x584>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X4, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 505938 <hypre_CSRMatrixMultiply._omp_fn.0+0x578>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X12, [X21], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X12, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X21], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X12, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X12, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X21], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X12, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X12, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X21], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X12, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X12, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X11, [X21], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X12, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X21], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X12, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X12, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [X21], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X12, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X12, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X30, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 5059f8 <hypre_CSRMatrixMultiply._omp_fn.0+0x638>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X21, X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X2, XZR, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X15, X18, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X1, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X5, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 507660 <hypre_CSRMatrixCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X23, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X0, [X22, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 507740 <hypre_CSRMatrixInitialize>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X22, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X18, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X18, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X5, [X22, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [X22, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f590 <@plt_start@+0x3a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X21, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDP X18, X5, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.GT 505764 <hypre_CSRMatrixMultiply._omp_fn.0+0x3a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 505794 <hypre_CSRMatrixMultiply._omp_fn.0+0x3d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X4, X12, X6, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X9, X6, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X7, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X24, X9, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 50543c <hypre_CSRMatrixMultiply._omp_fn.0+0x7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X21, [X23, X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 5057a0 <hypre_CSRMatrixMultiply._omp_fn.0+0x3e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	csr_matop.c:185-302
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:185,192-302.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 36.50 to 5.50 cycles (6.64x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 712 bytes. The binary function is storing 504 bytes.

General properties

nb instructions	265
loop length	1060
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

32.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	25.00	25.00	32.75	32.75	32.75	32.75	0.00	0.00	0.00	0.00	36.50	36.17	36.33	22.50	22.50
cycles	25.00	25.00	32.75	32.75	32.75	32.75	0.00	0.00	0.00	0.00	36.50	36.17	36.33	22.50	22.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	32.88
Overall L1	36.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 36.50 cycles. At this rate:

20% of peak load performance is reached (19.51 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
28% of peak store performance is reached (13.81 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 5053c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #864]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X5, X8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X19, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X27, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X20, X0, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X0, X19, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X8, X5, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X23, [X22, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X25, X21, [X22, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
BL 519580 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 519560 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SDIV X6, X19, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
LDP X12, X2, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X0, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MSUB X7, X6, X0, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X7, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 505a48 <hypre_CSRMatrixMultiply._omp_fn.0+0x688>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X10, X12, X6, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X11, X6, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X12, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X24, X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X2, X3, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X12, X13, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 51674c <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X18, X5, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X8, X12, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 505484 <hypre_CSRMatrixMultiply._omp_fn.0+0xc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X2, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #255	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X18, X5, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X8, X12, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f370 <@plt_start@+0x180>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X18, X5, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X8, X12, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X10, XZR, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X17, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X12, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 505524 <hypre_CSRMatrixMultiply._omp_fn.0+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
UBFM X13, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X17, [X21, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X18, X5, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X13, X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f590 <@plt_start@+0x3a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X14, X12, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X15, X18, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X5, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X12, 5058cc <hypre_CSRMatrixMultiply._omp_fn.0+0x50c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X16, X21, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X21], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 505630 <hypre_CSRMatrixMultiply._omp_fn.0+0x270>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X30, X16, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X17, X30, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X2, X17, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X7, X6, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 5055e4 <hypre_CSRMatrixMultiply._omp_fn.0+0x224>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 5055d4 <hypre_CSRMatrixMultiply._omp_fn.0+0x214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X7, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 5055cc <hypre_CSRMatrixMultiply._omp_fn.0+0x20c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X7, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 5055c4 <hypre_CSRMatrixMultiply._omp_fn.0+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X7, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 5055bc <hypre_CSRMatrixMultiply._omp_fn.0+0x1fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X7, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 5055b4 <hypre_CSRMatrixMultiply._omp_fn.0+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X7, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 5055ac <hypre_CSRMatrixMultiply._omp_fn.0+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X4, [X21], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X21], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X3, [X21], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X21], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X21], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X21], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X13, [X21], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X16, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 505630 <hypre_CSRMatrixMultiply._omp_fn.0+0x270>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X5, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 505890 <hypre_CSRMatrixMultiply._omp_fn.0+0x4d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X16, X23, X24,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X21, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X23, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X14, X16, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X12, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X30, X12, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X2, X17, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 5056e8 <hypre_CSRMatrixMultiply._omp_fn.0+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 5056d4 <hypre_CSRMatrixMultiply._omp_fn.0+0x314>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 5056c8 <hypre_CSRMatrixMultiply._omp_fn.0+0x308>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 5056bc <hypre_CSRMatrixMultiply._omp_fn.0+0x2fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 5056b0 <hypre_CSRMatrixMultiply._omp_fn.0+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 5056a4 <hypre_CSRMatrixMultiply._omp_fn.0+0x2e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X2, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 505698 <hypre_CSRMatrixMultiply._omp_fn.0+0x2d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X6, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X7, X6, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X7, [X0], #8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X4, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X3, [X0], #8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X9, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X11, [X0], #8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X10, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X13, [X0], #8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X8, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X14, [X0], #8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X30, X12, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X30, [X0], #8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X17, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X17, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X2, [X0], #8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X16, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 505748 <hypre_CSRMatrixMultiply._omp_fn.0+0x388>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X15, X18, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X5, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f590 <@plt_start@+0x3a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X15, X18, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X5, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 505a5c <hypre_CSRMatrixMultiply._omp_fn.0+0x69c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #255	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X18, X5, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X16, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
UBFM X9, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X2, X9, X11, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f370 <@plt_start@+0x180>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X18, X5, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X23, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 5058ac <hypre_CSRMatrixMultiply._omp_fn.0+0x4ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X13, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X4, [X22, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X22, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X15, X18, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X5, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f590 <@plt_start@+0x3a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X21, X18, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X5, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X21, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 505764 <hypre_CSRMatrixMultiply._omp_fn.0+0x3a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #160	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 516820 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X23, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X16, X23, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X30, X21, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X17, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 5059f8 <hypre_CSRMatrixMultiply._omp_fn.0+0x638>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X2, X30, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X7, X6, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X4, X1, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 505988 <hypre_CSRMatrixMultiply._omp_fn.0+0x5c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 505974 <hypre_CSRMatrixMultiply._omp_fn.0+0x5b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 505968 <hypre_CSRMatrixMultiply._omp_fn.0+0x5a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X4, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 50595c <hypre_CSRMatrixMultiply._omp_fn.0+0x59c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X4, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 505950 <hypre_CSRMatrixMultiply._omp_fn.0+0x590>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X4, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 505944 <hypre_CSRMatrixMultiply._omp_fn.0+0x584>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X4, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 505938 <hypre_CSRMatrixMultiply._omp_fn.0+0x578>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X12, [X21], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X12, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X21], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X12, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X12, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X21], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X12, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X12, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X21], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X12, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X12, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X11, [X21], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X12, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X21], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X12, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X12, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [X21], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X12, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X12, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X30, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 5059f8 <hypre_CSRMatrixMultiply._omp_fn.0+0x638>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X21, X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X2, XZR, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X15, X18, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X1, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X5, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 507660 <hypre_CSRMatrixCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X23, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X0, [X22, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 507740 <hypre_CSRMatrixInitialize>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X22, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X18, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X18, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X5, [X22, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [X22, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f590 <@plt_start@+0x3a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X21, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDP X18, X5, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.GT 505764 <hypre_CSRMatrixMultiply._omp_fn.0+0x3a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 505794 <hypre_CSRMatrixMultiply._omp_fn.0+0x3d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X4, X12, X6, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X9, X6, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X7, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X24, X9, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 50543c <hypre_CSRMatrixMultiply._omp_fn.0+0x7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X21, [X23, X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 5057a0 <hypre_CSRMatrixMultiply._omp_fn.0+0x3e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼hypre_CSRMatrixMultiply._omp_fn.0–	0.71	0.27
○Loop 3583 - csr_matop.c:254-255 - exec	0	0
▼Loop 3580 - csr_matop.c:272-298 - exec–	0	0
▼Loop 3581 - csr_matop.c:282-298 - exec–	0.06	0.02
○Loop 3582 - csr_matop.c:286-298 - exec	0.36	0.12
○Loop 3585 - csr_matop.c:245-246 - exec	0	0
○Loop 3584 - csr_matop.c:248-249 - exec	0	0
▼Loop 3586 - csr_matop.c:214-231 - exec–	0	0
▼Loop 3587 - csr_matop.c:222-231 - exec–	0.05	0.02
○Loop 3588 - csr_matop.c:225-231 - exec	0.24	0.08

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code