OV - exec - Function hypre_IJVectorSetValuesPar._omp

	Function: hypre_IJVectorSetValuesPar._omp_fn.0	Module: exec	Source: IJVector_parcsr.c:440-443	Coverage: 0.2%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJVector_parcsr.c: 440 - 443

--------------------------------------------------------------------------------

440: #pragma omp parallel for private(j) HYPRE_SMP_SCHEDULE

441: #endif

442:       for (j = 0; j < num_values; j++)

443:          data[j] = values[j];

0x50162c STP	X29, X30, [SP, #976]!

0x501630 ADD	X29, SP, #0

0x501634 STR	X21, [SP, #32]

0x501638 LDR	X21, [X0]

0x50163c STP	X19, X20, [SP, #16]

0x501640 ORR	X20, XZR, X0

0x501644 BL	40f6a0

0x501648 SBFM	X19, X0, #0, #31

0x50164c BL	40f540

0x501650 SDIV	X3, X21, X19

0x501654 SBFM	X1, X0, #0, #31

0x501658 MSUB	X2, X3, X19, X21

0x50165c CMP	X1, X2

0x501660 B.LT	501788

(3534) 0x501664 MADD	X13, X3, X1, X2

(3534) 0x501668 ADD	X11, X3, X13

(3534) 0x50166c CMP	X13, X11

(3534) 0x501670 B.GE	501778

(3534) 0x501674 SUB	X4, X11, X13

(3534) 0x501678 LDP	X12, X0, [X20, #8]

(3534) 0x50167c ANDS	X5, X4, #4224

(3534) 0x501680 B.EQ	501710

(3534) 0x501684 CMP	X5, #1

(3534) 0x501688 B.EQ	5016fc

(3534) 0x50168c CMP	X5, #2

(3534) 0x501690 B.EQ	5016f0

(3534) 0x501694 CMP	X5, #3

(3534) 0x501698 B.EQ	5016e4

(3534) 0x50169c CMP	X5, #4

(3534) 0x5016a0 B.EQ	5016d8

(3534) 0x5016a4 CMP	X5, #5

(3534) 0x5016a8 B.EQ	5016cc

(3534) 0x5016ac CMP	X5, #6

(3534) 0x5016b0 B.EQ	5016c0

(3534) 0x5016b4 LDR	D0, [X12, X13,LSL #3]

(3534) 0x5016b8 STR	D0, [X0, X13,LSL #3]

(3534) 0x5016bc ADD	X13, X13, #1

(3534) 0x5016c0 LDR	D1, [X12, X13,LSL #3]

(3534) 0x5016c4 STR	D1, [X0, X13,LSL #3]

(3534) 0x5016c8 ADD	X13, X13, #1

(3534) 0x5016cc LDR	D2, [X12, X13,LSL #3]

(3534) 0x5016d0 STR	D2, [X0, X13,LSL #3]

(3534) 0x5016d4 ADD	X13, X13, #1

(3534) 0x5016d8 LDR	D3, [X12, X13,LSL #3]

(3534) 0x5016dc STR	D3, [X0, X13,LSL #3]

(3534) 0x5016e0 ADD	X13, X13, #1

(3534) 0x5016e4 LDR	D4, [X12, X13,LSL #3]

(3534) 0x5016e8 STR	D4, [X0, X13,LSL #3]

(3534) 0x5016ec ADD	X13, X13, #1

(3534) 0x5016f0 LDR	D5, [X12, X13,LSL #3]

(3534) 0x5016f4 STR	D5, [X0, X13,LSL #3]

(3534) 0x5016f8 ADD	X13, X13, #1

(3534) 0x5016fc LDR	D6, [X12, X13,LSL #3]

(3534) 0x501700 STR	D6, [X0, X13,LSL #3]

(3534) 0x501704 ADD	X13, X13, #1

(3534) 0x501708 CMP	X11, X13

(3534) 0x50170c B.EQ	501778

  (3535) 0x501710 LDR	D7, [X12, X13,LSL #3]

  (3535) 0x501714 ADD	X14, X13, #1

  (3535) 0x501718 ADD	X10, X13, #2

  (3535) 0x50171c ADD	X9, X13, #3

  (3535) 0x501720 ADD	X8, X13, #4

  (3535) 0x501724 ADD	X7, X13, #5

  (3535) 0x501728 ADD	X6, X13, #6

  (3535) 0x50172c ADD	X15, X13, #7

  (3535) 0x501730 STR	D7, [X0, X13,LSL #3]

  (3535) 0x501734 ADD	X13, X13, #8

  (3535) 0x501738 LDR	D16, [X12, X14,LSL #3]

  (3535) 0x50173c STR	D16, [X0, X14,LSL #3]

  (3535) 0x501740 LDR	D17, [X12, X10,LSL #3]

  (3535) 0x501744 STR	D17, [X0, X10,LSL #3]

  (3535) 0x501748 LDR	D18, [X12, X9,LSL #3]

  (3535) 0x50174c STR	D18, [X0, X9,LSL #3]

  (3535) 0x501750 LDR	D19, [X12, X8,LSL #3]

  (3535) 0x501754 STR	D19, [X0, X8,LSL #3]

  (3535) 0x501758 LDR	D20, [X12, X7,LSL #3]

  (3535) 0x50175c STR	D20, [X0, X7,LSL #3]

  (3535) 0x501760 LDR	D21, [X12, X6,LSL #3]

  (3535) 0x501764 STR	D21, [X0, X6,LSL #3]

  (3535) 0x501768 LDR	D22, [X12, X15,LSL #3]

  (3535) 0x50176c STR	D22, [X0, X15,LSL #3]

  (3535) 0x501770 CMP	X11, X13

  (3535) 0x501774 B.NE	501710

(3534) 0x501778 LDP	X19, X20, [SP, #16]

(3534) 0x50177c LDR	X21, [SP, #32]

(3534) 0x501780 LDP	X29, X30, [SP], #48

(3534) 0x501784 RET

(3534) 0x501788 ADD	X3, X3, #1

(3534) 0x50178c MOVZ	X2, #0

(3534) 0x501790 B	501664

0x501794 HINT	#0

0x501798 HINT	#0

0x50179c HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	IJVector_parcsr.c:440-443
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJVector_parcsr.c:440-443.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 20.00 to 10.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	17
loop length	68
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 50162c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f6a0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f540 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SDIV X3, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MSUB X2, X3, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X1, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 501788 <hypre_IJVectorSetValuesPar._omp_fn.0+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Source file and lines	IJVector_parcsr.c:440-443
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJVector_parcsr.c:440-443.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	17
loop length	68
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 50162c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f6a0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f540 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SDIV X3, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MSUB X2, X3, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X1, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 501788 <hypre_IJVectorSetValuesPar._omp_fn.0+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼hypre_IJVectorSetValuesPar._omp_fn.0–	0.2	0.08
▼Loop 3534 - IJVector_parcsr.c:440-443 - exec–	0	0
○Loop 3535 - IJVector_parcsr.c:443-443 - exec	0.2	0.07

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code