OV - exec - Function hypre_IJMatrixSetValuesOMPParCSR._omp

	Function: hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1	Module: exec	Source: IJMatrix_parcsr.c:3240-3500 [...]	Coverage: 3.61%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 3240 - 3500

--------------------------------------------------------------------------------

3240: #pragma omp parallel

[...]

3256:          num_threads = hypre_NumActiveThreads();

3257:          my_thread_num = hypre_GetThreadNum();

3258:

3259:          len = nrows/num_threads;

3260:          rest = nrows - len*num_threads;

3261:

3262:          if (my_thread_num < rest)

3263:          {

3264:             ns = my_thread_num*(len+1);

3265:             ne = (my_thread_num+1)*(len+1);

3266:          }

3267:          else

3268:          {

3269:             ns = my_thread_num*len+rest;

3270:             ne = (my_thread_num+1)*len+rest;

3271:          }

3272:

3273:          value_start[my_thread_num] = 0;

3274:          for (ii=ns; ii < ne; ii++)

3275:             value_start[my_thread_num] += ncols[ii];

3276:

3277: #ifdef HYPRE_USING_OPENMP

3278: #pragma omp barrier

3279: #endif

3280:          if (my_thread_num == 0)

3281:          {

3282:             for (i=0; i < max_num_threads; i++)

3283:                value_start[i+1] += value_start[i];

3284:          }

3285: #ifdef HYPRE_USING_OPENMP

3286: #pragma omp barrier

3287: #endif

3288:          indx = 0;

3289:          if (my_thread_num)

3290:             indx = value_start[my_thread_num-1];

3291:          for (ii=ns; ii < ne; ii++)

3292:          {

3293:             row = rows[ii];

3294:             n = ncols[ii];

3295:             /* processor owns the row */

3296:             if (row >= row_partitioning[pstart] && row < row_partitioning[pstart+1])

3297:             {

3298:                row_local = row - row_partitioning[pstart];

3299:                /* compute local row number */

3300:                if (need_aux)

3301:                {

3302:                   local_j = aux_j[row_local];

3303:                   local_data = aux_data[row_local];

3304:    	          space = row_space[row_local];

3305:    	          old_size = row_length[row_local];

3306:    	          size = space - old_size;

3307:    	          if (size < n)

3308:       	          {

3309:       	             size = n - size;

3310:       	             tmp_j = hypre_CTAlloc(HYPRE_Int,size);

3311:       	             tmp_data = hypre_CTAlloc(HYPRE_Complex,size);

3312:       	          }

3313:       	          tmp_indx = 0;

3314:       	          not_found = 1;

3315:       	          size = old_size;

3316:                   for (i=0; i < n; i++)

3317:       	          {

3318:       	             for (j=0; j < old_size; j++)

3319:       	             {

3320:       	                if (local_j[j] == cols[indx])

3321:       	                {

3322:                            local_data[j] = values[indx];

3323:       		           not_found = 0;

3324:       		           break;

3325:       	                }

3326:       	             }

3327:       	             if (not_found)

3328:       	             {

3329:       	                if (size < space)

3330:       	                {

3331:       	                   local_j[size] = cols[indx];

3332:       	                   local_data[size++] = values[indx];

3333:       	                }

3334:       	                else

3335:       	                {

3336:       	                   tmp_j[tmp_indx] = cols[indx];

3337:       	                   tmp_data[tmp_indx++] = values[indx];

3338:       	                }

3339:       	             }

3340:       	             not_found = 1;

3341:         	     indx++;

3342:       	          }

3343:

3344:                   row_length[row_local] = size+tmp_indx;

3345:

3346:                   if (tmp_indx)

3347:                   {

3348:    	             aux_j[row_local] = hypre_TReAlloc(aux_j[row_local],HYPRE_Int,

3349:                                                     size+tmp_indx);

3350:    	             aux_data[row_local] = hypre_TReAlloc(aux_data[row_local],

3351:                                                        HYPRE_Complex,size+tmp_indx);

3352:                      row_space[row_local] = size+tmp_indx;

3353:                      local_j = aux_j[row_local];

[...]

3359:    	          for (i=0; i < tmp_indx; i++)

3360:    	          {

3361:    	             local_j[cnt] = tmp_j[i];

3362:    	             local_data[cnt++] = tmp_data[i];

3363: 	          }

3364:

3365: 	          if (tmp_j)

3366: 	          {

3367: 	             hypre_TFree(tmp_j);

3368: 	             hypre_TFree(tmp_data);

[...]

3376: 	          offd_indx = hypre_AuxParCSRMatrixIndxOffd(aux_matrix)[row_local];

3377: 	          diag_indx = hypre_AuxParCSRMatrixIndxDiag(aux_matrix)[row_local];

3378: 	          cnt_diag = diag_indx;

3379: 	          cnt_offd = offd_indx;

3380: 	          diag_space = diag_i[row_local+1];

3381: 	          offd_space = offd_i[row_local+1];

3382: 	          not_found = 1;

3383:   	          for (i=0; i < n; i++)

3384: 	          {

3385: 	             if (cols[indx] < col_0 || cols[indx] > col_n)

3386:                      /* insert into offd */

3387: 	             {

3388: 	                for (j=offd_i[row_local]; j < offd_indx; j++)

3389: 	                {

3390: 		           if (offd_j[j] == cols[indx])

3391: 		           {

3392:                               offd_data[j] = values[indx];

3393: 		              not_found = 0;

3394: 		              break;

3395: 		           }

3396: 	                }

3397: 	                if (not_found)

3398: 	                {

3399: 	                   if (cnt_offd < offd_space)

3400: 	                   {

3401: 	                      offd_j[cnt_offd] = cols[indx];

3402: 	                      offd_data[cnt_offd++] = values[indx];

3403: 	                   }

3404: 	                   else

3405: 	 	           {

3406:                               hypre_error(HYPRE_ERROR_GENERIC);

3407: #ifdef HYPRE_USING_OPENMP

3408: #pragma omp atomic

3409: #endif

3410:                               error_flag++;

3411: 	    	              if (print_level)

3412:                                  hypre_printf("Error in row %d ! Too many elements!\n",

[...]

3422: 	                for (j=diag_i[row_local]; j < diag_indx; j++)

3423: 	                {

3424: 		           if (diag_j[j] == cols[indx])

3425: 		           {

3426:                               diag_data[j] = values[indx];

3427: 		              not_found = 0;

3428: 		              break;

3429: 		           }

3430: 	                }

3431: 	                if (not_found)

3432: 	                {

3433: 	                   if (cnt_diag < diag_space)

3434: 	                   {

3435: 	                      diag_j[cnt_diag] = cols[indx];

3436: 	                      diag_data[cnt_diag++] = values[indx];

3437: 	                   }

3438: 	                   else

3439: 	 	           {

3440:                               hypre_error(HYPRE_ERROR_GENERIC);

3441: #ifdef HYPRE_USING_OPENMP

3442: #pragma omp atomic

3443: #endif

3444:                               error_flag++;

3445: 	    	              if (print_level)

3446:                                  hypre_printf("Error in row %d ! Too many elements !\n",

[...]

3454: 	             indx++;

3455: 	          }

3456:

3457:                   hypre_AuxParCSRMatrixIndxDiag(aux_matrix)[row_local] = cnt_diag;

3458:                   hypre_AuxParCSRMatrixIndxOffd(aux_matrix)[row_local] = cnt_offd;

[...]

3466:                indx +=  n;

3467:    	       if (aux_matrix)

3468:                {

3469:                   col_indx = 0;

3470:                   for (i=0; i < off_proc_i_indx; i=i+2)

3471:                   {

3472: 	             row_len = off_proc_i[i+1];

3473: 	             if (off_proc_i[i] == row)

3474: 		     {

3475: 		        for (j=0; j < n; j++)

3476: 		        {

3477: 			   cnt1 = col_indx;

3478: 			   for (k=0; k < row_len; k++)

3479: 			   {

3480: 			      if (off_proc_j[cnt1] == cols[j])

3481: 			      {

3482:                                  off_proc_j[cnt1++] = -1;

3483:                		         /*cancel_indx++;*/

3484: 	                         offproc_cnt[my_thread_num]++;

[...]

3500: 		        col_indx += row_len;

0x4f62c8 STP	X29, X30, [SP, #688]!

0x4f62cc ADD	X29, SP, #0

0x4f62d0 STP	X25, X26, [SP, #64]

0x4f62d4 STP	X27, X28, [SP, #80]

0x4f62d8 LDP	X26, X1, [X0]

0x4f62dc LDP	X15, X28, [X0, #24]

0x4f62e0 STP	X19, X20, [SP, #16]

0x4f62e4 LDR	X2, [X0, #16]

0x4f62e8 STP	X21, X22, [SP, #32]

0x4f62ec LDR	X3, [X0, #40]

0x4f62f0 STP	X23, X24, [SP, #48]

0x4f62f4 LDR	X4, [X0, #56]

0x4f62f8 STP	X15, X1, [SP, #96]

0x4f62fc LDR	X5, [X0, #64]

0x4f6300 STR	X2, [SP, #112]

0x4f6304 LDR	X6, [X0, #72]

0x4f6308 STR	X3, [SP, #128]

0x4f630c LDR	X7, [X0, #80]

0x4f6310 STR	X5, [SP, #168]

0x4f6314 STR	X4, [SP, #208]

0x4f6318 STR	X6, [SP, #256]

0x4f631c STR	X0, [SP, #328]

0x4f6320 LDR	X25, [X0, #48]

0x4f6324 STR	X7, [SP, #248]

0x4f6328 LDR	X8, [X0, #88]

0x4f632c LDP	X22, X20, [X0, #192]

0x4f6330 LDR	X9, [X0, #96]

0x4f6334 STR	X8, [SP, #200]

0x4f6338 LDR	X10, [X0, #104]

0x4f633c LDR	X11, [X0, #112]

0x4f6340 STR	X9, [SP, #240]

0x4f6344 LDR	X24, [X0, #120]

0x4f6348 STR	X10, [SP, #192]

0x4f634c LDR	X12, [X0, #128]

0x4f6350 STR	X11, [SP, #232]

0x4f6354 LDR	X13, [X0, #136]

0x4f6358 LDR	X23, [X0, #144]

0x4f635c STR	X12, [SP, #296]

0x4f6360 LDR	X14, [X0, #152]

0x4f6364 STR	X13, [SP, #224]

0x4f6368 LDR	X16, [X0, #160]

0x4f636c LDR	X17, [X0, #168]

0x4f6370 STR	X14, [SP, #288]

0x4f6374 LDR	X18, [X0, #176]

0x4f6378 STR	X16, [SP, #120]

0x4f637c LDR	X19, [X0, #184]

0x4f6380 LDP	X21, X0, [X0, #208]

0x4f6384 STR	X17, [SP, #152]

0x4f6388 STR	X18, [SP, #160]

0x4f638c STR	X0, [SP, #144]

0x4f6390 STR	X19, [SP, #184]

0x4f6394 STR	X21, [SP, #320]

0x4f6398 BL	519560

0x4f639c ORR	X27, XZR, X0

0x4f63a0 BL	519580

0x4f63a4 SDIV	X1, X26, X27

0x4f63a8 ORR	X21, XZR, X0

0x4f63ac LDR	X15, [SP, #96]

0x4f63b0 MSUB	X2, X1, X27, X26

0x4f63b4 CMP	X2, X0

0x4f63b8 B.LE	4f72a0

0x4f63bc MADD	X26, X1, X0, X0

0x4f63c0 ADD	X4, X1, #1

0x4f63c4 ADD	X5, X4, X26

0x4f63c8 STR	X5, [SP, #96]

0x4f63cc UBFM	X19, X21, #61, #60

0x4f63d0 STR	XZR, [X22, X21,LSL #3]

0x4f63d4 ADD	X27, X22, X19

0x4f63d8 CMP	X26, X5

0x4f63dc B.GE	4f64f8

0x4f63e0 LDR	X7, [SP, #104]

0x4f63e4 MOVZ	X0, #0

0x4f63e8 ADD	X2, X7, X26,LSL #3

0x4f63ec ADD	X8, X7, X5,LSL #3

0x4f63f0 SUB	X9, X8, X2

0x4f63f4 SUB	X10, X9, #8

0x4f63f8 UBFM	X11, X10, #3, #63

0x4f63fc ADD	X12, X11, #1

0x4f6400 ANDS	X13, X12, #4224

0x4f6404 B.EQ	4f6488

0x4f6408 CMP	X13, #1

0x4f640c B.EQ	4f6474

0x4f6410 CMP	X13, #2

0x4f6414 B.EQ	4f6468

0x4f6418 CMP	X13, #3

0x4f641c B.EQ	4f645c

0x4f6420 CMP	X13, #4

0x4f6424 B.EQ	4f6450

0x4f6428 CMP	X13, #5

0x4f642c B.EQ	4f6444

0x4f6430 CMP	X13, #6

0x4f6434 B.NE	4f73a8

0x4f6438 LDR	X14, [X2], #8

0x4f643c ADD	X0, X0, X14

0x4f6440 STR	X0, [X27]

0x4f6444 LDR	X16, [X2], #8

0x4f6448 ADD	X0, X0, X16

0x4f644c STR	X0, [X27]

0x4f6450 LDR	X17, [X2], #8

0x4f6454 ADD	X0, X0, X17

0x4f6458 STR	X0, [X27]

0x4f645c LDR	X18, [X2], #8

0x4f6460 ADD	X0, X0, X18

0x4f6464 STR	X0, [X27]

0x4f6468 LDR	X1, [X2], #8

0x4f646c ADD	X0, X0, X1

0x4f6470 STR	X0, [X27]

0x4f6474 LDR	X30, [X2], #8

0x4f6478 ADD	X0, X0, X30

0x4f647c STR	X0, [X27]

0x4f6480 CMP	X8, X2

0x4f6484 B.EQ	4f64f8

(3411) 0x4f6488 ORR	X3, XZR, X2

(3411) 0x4f648c ADD	X2, X2, #64

(3411) 0x4f6490 LDR	X4, [X3], #8

(3411) 0x4f6494 ADD	X5, X0, X4

(3411) 0x4f6498 STR	X5, [X27]

(3411) 0x4f649c LDUR	X6, [X2, #456]

(3411) 0x4f64a0 ADD	X7, X5, X6

(3411) 0x4f64a4 STR	X7, [X27]

(3411) 0x4f64a8 LDR	X9, [X3, #8]

(3411) 0x4f64ac ADD	X10, X7, X9

(3411) 0x4f64b0 STR	X10, [X27]

(3411) 0x4f64b4 LDUR	X11, [X2, #472]

(3411) 0x4f64b8 ADD	X12, X10, X11

(3411) 0x4f64bc STR	X12, [X27]

(3411) 0x4f64c0 LDUR	X13, [X2, #480]

(3411) 0x4f64c4 ADD	X14, X12, X13

(3411) 0x4f64c8 STR	X14, [X27]

(3411) 0x4f64cc LDUR	X16, [X2, #488]

(3411) 0x4f64d0 ADD	X17, X14, X16

(3411) 0x4f64d4 STR	X17, [X27]

(3411) 0x4f64d8 LDUR	X18, [X2, #496]

(3411) 0x4f64dc ADD	X30, X17, X18

(3411) 0x4f64e0 STR	X30, [X27]

(3411) 0x4f64e4 LDUR	X1, [X2, #504]

(3411) 0x4f64e8 ADD	X0, X30, X1

(3411) 0x4f64ec STR	X0, [X27]

(3411) 0x4f64f0 CMP	X8, X2

(3411) 0x4f64f4 B.NE	4f6488

0x4f64f8 STR	X15, [SP, #136]

0x4f64fc BL	40f590

0x4f6500 LDR	X15, [SP, #136]

0x4f6504 CBNZ	X21, 4f728c

0x4f6508 LDR	X8, [SP, #144]

0x4f650c CMP	X8, #0

0x4f6510 B.LE	4f6648

0x4f6514 UBFM	X0, X8, #61, #60

0x4f6518 ADD	X9, X22, X8,LSL #3

0x4f651c ORR	X1, XZR, X22

0x4f6520 SUB	X3, X0, #8

0x4f6524 LDR	X16, [X22]

0x4f6528 UBFM	X4, X3, #3, #63

0x4f652c ADD	X5, X4, #1

0x4f6530 ANDS	X6, X5, #4224

0x4f6534 B.EQ	4f65c4

0x4f6538 CMP	X6, #1

0x4f653c B.EQ	4f65b0

0x4f6540 CMP	X6, #2

0x4f6544 B.EQ	4f65a4

0x4f6548 CMP	X6, #3

0x4f654c B.EQ	4f6598

0x4f6550 CMP	X6, #4

0x4f6554 B.EQ	4f658c

0x4f6558 CMP	X6, #5

0x4f655c B.EQ	4f6580

0x4f6560 CMP	X6, #6

0x4f6564 B.EQ	4f6574

0x4f6568 LDR	X22, [X22, #8]

0x4f656c ADD	X16, X16, X22

0x4f6570 STR	X16, [X1, #8]!

0x4f6574 LDR	X7, [X1, #8]

0x4f6578 ADD	X16, X16, X7

0x4f657c STR	X16, [X1, #8]!

0x4f6580 LDR	X10, [X1, #8]

0x4f6584 ADD	X16, X16, X10

0x4f6588 STR	X16, [X1, #8]!

0x4f658c LDR	X11, [X1, #8]

0x4f6590 ADD	X16, X16, X11

0x4f6594 STR	X16, [X1, #8]!

0x4f6598 LDR	X12, [X1, #8]

0x4f659c ADD	X16, X16, X12

0x4f65a0 STR	X16, [X1, #8]!

0x4f65a4 LDR	X13, [X1, #8]

0x4f65a8 ADD	X16, X16, X13

0x4f65ac STR	X16, [X1, #8]!

0x4f65b0 LDR	X14, [X1, #8]

0x4f65b4 ADD	X16, X16, X14

0x4f65b8 STR	X16, [X1, #8]!

0x4f65bc CMP	X9, X1

0x4f65c0 B.EQ	4f6648

(3410) 0x4f65c4 LDR	X2, [X1, #8]

(3410) 0x4f65c8 ORR	X17, XZR, X1

(3410) 0x4f65cc ADD	X18, X1, #24

(3410) 0x4f65d0 ADD	X30, X1, #32

(3410) 0x4f65d4 ADD	X27, X1, #40

(3410) 0x4f65d8 ADD	X4, X1, #48

(3410) 0x4f65dc ADD	X3, X1, #56

(3410) 0x4f65e0 ADD	X1, X1, #64

(3410) 0x4f65e4 ADD	X8, X16, X2

(3410) 0x4f65e8 STR	X8, [X17, #8]!

(3410) 0x4f65ec LDR	X0, [X17, #8]

(3410) 0x4f65f0 ADD	X5, X8, X0

(3410) 0x4f65f4 STR	X5, [X17, #8]!

(3410) 0x4f65f8 LDR	X6, [X17, #8]

(3410) 0x4f65fc ADD	X22, X5, X6

(3410) 0x4f6600 STR	X22, [X17, #8]

(3410) 0x4f6604 LDR	X7, [X18, #8]

(3410) 0x4f6608 ADD	X10, X22, X7

(3410) 0x4f660c STR	X10, [X18, #8]

(3410) 0x4f6610 LDR	X11, [X30, #8]

(3410) 0x4f6614 ADD	X12, X10, X11

(3410) 0x4f6618 STR	X12, [X30, #8]

(3410) 0x4f661c LDR	X13, [X27, #8]

(3410) 0x4f6620 ADD	X14, X12, X13

(3410) 0x4f6624 STR	X14, [X27, #8]

(3410) 0x4f6628 LDR	X16, [X4, #8]

(3410) 0x4f662c ADD	X17, X14, X16

(3410) 0x4f6630 STR	X17, [X4, #8]

(3410) 0x4f6634 LDR	X18, [X3, #8]

(3410) 0x4f6638 ADD	X16, X17, X18

(3410) 0x4f663c STR	X16, [X3, #8]

(3410) 0x4f6640 CMP	X9, X1

(3410) 0x4f6644 B.NE	4f65c4

0x4f6648 STR	X15, [SP, #136]

0x4f664c BL	40f590

0x4f6650 LDR	X27, [SP, #136]

0x4f6654 LDR	X15, [SP, #96]

0x4f6658 CMP	X26, X15

0x4f665c B.GE	4f6950

0x4f6660 LDR	X30, [SP, #152]

0x4f6664 ORR	X5, XZR, X28

0x4f6668 MOVN	X22, #0

0x4f666c STR	XZR, [SP, #136]

0x4f6670 LDR	X28, [SP, #120]

0x4f6674 LDR	X1, [SP, #160]

0x4f6678 SUB	X4, X30, #1

0x4f667c LDR	X8, [SP, #168]

0x4f6680 UBFM	X0, X4, #1, #63

0x4f6684 UBFM	X2, X28, #61, #60

0x4f6688 LDR	X9, [SP, #208]

0x4f668c ADD	X3, X2, #8

0x4f6690 ADD	X10, X25, X2

0x4f6694 ADD	X6, X1, #16

0x4f6698 ADD	X25, X25, X3

0x4f669c ADD	X7, X6, X0,LSL #4

0x4f66a0 STR	X10, [SP, #120]

0x4f66a4 STR	X25, [SP, #144]

0x4f66a8 STR	X7, [SP, #176]

      (3396) 0x4f66ac LDR	X11, [SP, #112]

      (3396) 0x4f66b0 LDR	X12, [SP, #120]

      (3396) 0x4f66b4 LDR	X14, [SP, #104]

      (3396) 0x4f66b8 LDR	X25, [X11, X26,LSL #3]

      (3396) 0x4f66bc LDR	X13, [X12]

      (3396) 0x4f66c0 LDR	X2, [X14, X26,LSL #3]

      (3396) 0x4f66c4 CMP	X25, X13

      (3396) 0x4f66c8 B.LT	4f6b14

      (3396) 0x4f66cc LDR	X16, [SP, #144]

      (3396) 0x4f66d0 LDR	X17, [X16]

      (3396) 0x4f66d4 CMP	X25, X17

      (3396) 0x4f66d8 B.GE	4f6b14

      (3396) 0x4f66dc SUB	X14, X25, X13

      (3396) 0x4f66e0 LDR	X18, [SP, #192]

      (3396) 0x4f66e4 UBFM	X6, X14, #61, #60

      (3396) 0x4f66e8 CBNZ	X18, 4f6e20

    (3403) 0x4f66ec LDR	X1, [SP, #128]

    (3403) 0x4f66f0 ADD	X13, X6, #8

    (3403) 0x4f66f4 ADD	X17, X21, X2

    (3403) 0x4f66f8 LDR	X16, [SP, #232]

    (3403) 0x4f66fc LDR	X11, [SP, #224]

    (3403) 0x4f6700 LDP	X30, X0, [X1, #56]

    (3403) 0x4f6704 LDR	X15, [X16, X13]

    (3403) 0x4f6708 ADD	X4, X30, X6

    (3403) 0x4f670c ADD	X7, X0, X6

    (3403) 0x4f6710 LDR	X16, [X30, X14,LSL #3]

    (3403) 0x4f6714 STP	X7, X4, [SP, #208]

    (3403) 0x4f6718 LDR	X3, [X0, X14,LSL #3]

    (3403) 0x4f671c STR	X15, [SP, #168]

    (3403) 0x4f6720 ORR	X10, XZR, X16

    (3403) 0x4f6724 LDR	X12, [X11, X13]

    (3403) 0x4f6728 ORR	X28, XZR, X3

    (3403) 0x4f672c CMP	X2, #0

    (3403) 0x4f6730 B.LE	4f7480

    (3403) 0x4f6734 STP	X20, X19, [SP, #264]

    (3403) 0x4f6738 ORR	X18, XZR, X11

    (3403) 0x4f673c ORR	X20, XZR, X12

    (3403) 0x4f6740 STR	X26, [SP, #280]

    (3403) 0x4f6744 LDR	X26, [SP, #232]

    (3403) 0x4f6748 STR	X25, [SP, #304]

    (3403) 0x4f674c LDR	X19, [SP, #288]

    (3403) 0x4f6750 LDR	X7, [SP, #296]

    (3403) 0x4f6754 HINT	#0

    (3403) 0x4f6758 HINT	#0

    (3403) 0x4f675c HINT	#0

      (3406) 0x4f6760 LDR	X1, [X27, X21,LSL #3]

      (3406) 0x4f6764 CMP	X8, X1

      (3406) 0x4f6768 CCMP	X9, X1, #0, #10

      (3406) 0x4f676c B.LE	4f696c

      (3406) 0x4f6770 LDR	X0, [X18, X6]

      (3406) 0x4f6774 CMP	X3, X0

      (3406) 0x4f6778 B.LE	4f68f4

      (3406) 0x4f677c SUB	X30, X3, X0

      (3406) 0x4f6780 ANDS	X4, X30, #4224

      (3406) 0x4f6784 B.EQ	4f684c

      (3406) 0x4f6788 CMP	X4, #1

      (3406) 0x4f678c B.EQ	4f6830

      (3406) 0x4f6790 CMP	X4, #2

      (3406) 0x4f6794 B.EQ	4f681c

      (3406) 0x4f6798 CMP	X4, #3

      (3406) 0x4f679c B.EQ	4f6808

      (3406) 0x4f67a0 CMP	X4, #4

      (3406) 0x4f67a4 B.EQ	4f67f4

      (3406) 0x4f67a8 CMP	X4, #5

      (3406) 0x4f67ac B.EQ	4f67e0

      (3406) 0x4f67b0 CMP	X4, #6

      (3406) 0x4f67b4 B.EQ	4f67cc

      (3406) 0x4f67b8 LDR	X11, [X23, X0,LSL #3]

      (3406) 0x4f67bc UBFM	X2, X0, #61, #60

      (3406) 0x4f67c0 CMP	X1, X11

      (3406) 0x4f67c4 B.EQ	4f6e08

      (3406) 0x4f67c8 ADD	X0, X0, #1

      (3406) 0x4f67cc LDR	X12, [X23, X0,LSL #3]

      (3406) 0x4f67d0 UBFM	X2, X0, #61, #60

      (3406) 0x4f67d4 CMP	X1, X12

      (3406) 0x4f67d8 B.EQ	4f6e08

      (3406) 0x4f67dc ADD	X0, X0, #1

      (3406) 0x4f67e0 LDR	X13, [X23, X0,LSL #3]

      (3406) 0x4f67e4 UBFM	X2, X0, #61, #60

      (3406) 0x4f67e8 CMP	X1, X13

      (3406) 0x4f67ec B.EQ	4f6e08

      (3406) 0x4f67f0 ADD	X0, X0, #1

      (3406) 0x4f67f4 LDR	X14, [X23, X0,LSL #3]

      (3406) 0x4f67f8 UBFM	X2, X0, #61, #60

      (3406) 0x4f67fc CMP	X1, X14

      (3406) 0x4f6800 B.EQ	4f6e08

      (3406) 0x4f6804 ADD	X0, X0, #1

      (3406) 0x4f6808 LDR	X15, [X23, X0,LSL #3]

      (3406) 0x4f680c UBFM	X2, X0, #61, #60

      (3406) 0x4f6810 CMP	X1, X15

      (3406) 0x4f6814 B.EQ	4f6e08

      (3406) 0x4f6818 ADD	X0, X0, #1

      (3406) 0x4f681c LDR	X25, [X23, X0,LSL #3]

      (3406) 0x4f6820 UBFM	X2, X0, #61, #60

      (3406) 0x4f6824 CMP	X1, X25

      (3406) 0x4f6828 B.EQ	4f6e08

      (3406) 0x4f682c ADD	X0, X0, #1

      (3406) 0x4f6830 LDR	X30, [X23, X0,LSL #3]

      (3406) 0x4f6834 UBFM	X2, X0, #61, #60

      (3406) 0x4f6838 CMP	X1, X30

      (3406) 0x4f683c B.EQ	4f6e08

      (3406) 0x4f6840 ADD	X0, X0, #1

      (3406) 0x4f6844 CMP	X3, X0

      (3406) 0x4f6848 B.EQ	4f68f4

        (3407) 0x4f684c LDR	X30, [X23, X0,LSL #3]

        (3407) 0x4f6850 ADD	X4, X0, #1

        (3407) 0x4f6854 ADD	X12, X0, #3

        (3407) 0x4f6858 ADD	X11, X0, #2

        (3407) 0x4f685c ADD	X13, X0, #4

        (3407) 0x4f6860 ADD	X14, X0, #5

        (3407) 0x4f6864 ADD	X15, X0, #6

        (3407) 0x4f6868 ADD	X25, X0, #7

        (3407) 0x4f686c UBFM	X2, X0, #61, #60

        (3407) 0x4f6870 ADD	X0, X0, #8

        (3407) 0x4f6874 CMP	X1, X30

        (3407) 0x4f6878 B.EQ	4f6e08

        (3407) 0x4f687c LDR	X30, [X23, X4,LSL #3]

        (3407) 0x4f6880 UBFM	X2, X4, #61, #60

        (3407) 0x4f6884 CMP	X1, X30

        (3407) 0x4f6888 B.EQ	4f6e08

        (3407) 0x4f688c LDR	X4, [X23, X11,LSL #3]

        (3407) 0x4f6890 UBFM	X2, X11, #61, #60

        (3407) 0x4f6894 CMP	X1, X4

        (3407) 0x4f6898 B.EQ	4f6e08

        (3407) 0x4f689c LDR	X11, [X23, X12,LSL #3]

        (3407) 0x4f68a0 UBFM	X2, X12, #61, #60

        (3407) 0x4f68a4 CMP	X1, X11

        (3407) 0x4f68a8 B.EQ	4f6e08

        (3407) 0x4f68ac LDR	X12, [X23, X13,LSL #3]

        (3407) 0x4f68b0 UBFM	X2, X13, #61, #60

        (3407) 0x4f68b4 CMP	X1, X12

        (3407) 0x4f68b8 B.EQ	4f6e08

        (3407) 0x4f68bc LDR	X13, [X23, X14,LSL #3]

        (3407) 0x4f68c0 UBFM	X2, X14, #61, #60

        (3407) 0x4f68c4 CMP	X1, X13

        (3407) 0x4f68c8 B.EQ	4f6e08

        (3407) 0x4f68cc LDR	X14, [X23, X15,LSL #3]

        (3407) 0x4f68d0 UBFM	X2, X15, #61, #60

        (3407) 0x4f68d4 CMP	X1, X14

        (3407) 0x4f68d8 B.EQ	4f6e08

        (3407) 0x4f68dc LDR	X15, [X23, X25,LSL #3]

        (3407) 0x4f68e0 UBFM	X2, X25, #61, #60

        (3407) 0x4f68e4 CMP	X1, X15

        (3407) 0x4f68e8 B.EQ	4f6e08

        (3407) 0x4f68ec CMP	X3, X0

        (3407) 0x4f68f0 B.NE	4f684c

      (3406) 0x4f68f4 CMP	X20, X28

      (3406) 0x4f68f8 B.LE	4f7318

      (3406) 0x4f68fc LDR	D2, [X5, X21,LSL #3]

      (3406) 0x4f6900 UBFM	X2, X28, #61, #60

      (3406) 0x4f6904 STR	X1, [X23, X28,LSL #3]

      (3406) 0x4f6908 ADD	X28, X28, #1

      (3406) 0x4f690c STR	D2, [X19, X2]

      (3406) 0x4f6910 ADD	X21, X21, #1

      (3406) 0x4f6914 CMP	X21, X17

      (3406) 0x4f6918 B.NE	4f6760

    (3403) 0x4f691c LDP	X20, X19, [SP, #264]

    (3403) 0x4f6920 LDR	X26, [SP, #280]

    (3403) 0x4f6924 ORR	X21, XZR, X17

    (3403) 0x4f6928 LDR	X25, [SP, #216]

    (3403) 0x4f692c STR	X10, [X25]

    (3403) 0x4f6930 LDR	X10, [SP, #208]

    (3403) 0x4f6934 STR	X28, [X10]

    (3403) 0x4f6938 HINT	#0

    (3403) 0x4f693c HINT	#0

      (3396) 0x4f6940 LDR	X7, [SP, #96]

      (3396) 0x4f6944 ADD	X26, X26, #1

      (3396) 0x4f6948 CMP	X7, X26

      (3396) 0x4f694c B.NE	4f66ac

(3408) 0x4f6950 LDP	X19, X20, [SP, #16]

(3408) 0x4f6954 LDP	X21, X22, [SP, #32]

(3408) 0x4f6958 LDP	X23, X24, [SP, #48]

(3408) 0x4f695c LDP	X25, X26, [SP, #64]

(3408) 0x4f6960 LDP	X27, X28, [SP, #80]

(3408) 0x4f6964 LDP	X29, X30, [SP], #336

(3408) 0x4f6968 RET

  (3404) 0x4f696c LDR	X0, [X26, X6]

  (3404) 0x4f6970 CMP	X16, X0

  (3404) 0x4f6974 B.LE	4f6af0

  (3404) 0x4f6978 SUB	X2, X16, X0

  (3404) 0x4f697c ANDS	X14, X2, #4224

  (3404) 0x4f6980 B.EQ	4f6a48

  (3404) 0x4f6984 CMP	X14, #1

  (3404) 0x4f6988 B.EQ	4f6a2c

  (3404) 0x4f698c CMP	X14, #2

  (3404) 0x4f6990 B.EQ	4f6a18

  (3404) 0x4f6994 CMP	X14, #3

  (3404) 0x4f6998 B.EQ	4f6a04

  (3404) 0x4f699c CMP	X14, #4

  (3404) 0x4f69a0 B.EQ	4f69f0

  (3404) 0x4f69a4 CMP	X14, #5

  (3404) 0x4f69a8 B.EQ	4f69dc

  (3404) 0x4f69ac CMP	X14, #6

  (3404) 0x4f69b0 B.EQ	4f69c8

  (3404) 0x4f69b4 LDR	X25, [X24, X0,LSL #3]

  (3404) 0x4f69b8 UBFM	X2, X0, #61, #60

  (3404) 0x4f69bc CMP	X1, X25

  (3404) 0x4f69c0 B.EQ	4f6e14

  (3404) 0x4f69c4 ADD	X0, X0, #1

  (3404) 0x4f69c8 LDR	X13, [X24, X0,LSL #3]

  (3404) 0x4f69cc UBFM	X2, X0, #61, #60

  (3404) 0x4f69d0 CMP	X1, X13

  (3404) 0x4f69d4 B.EQ	4f6e14

  (3404) 0x4f69d8 ADD	X0, X0, #1

  (3404) 0x4f69dc LDR	X15, [X24, X0,LSL #3]

  (3404) 0x4f69e0 UBFM	X2, X0, #61, #60

  (3404) 0x4f69e4 CMP	X1, X15

  (3404) 0x4f69e8 B.EQ	4f6e14

  (3404) 0x4f69ec ADD	X0, X0, #1

  (3404) 0x4f69f0 LDR	X30, [X24, X0,LSL #3]

  (3404) 0x4f69f4 UBFM	X2, X0, #61, #60

  (3404) 0x4f69f8 CMP	X1, X30

  (3404) 0x4f69fc B.EQ	4f6e14

  (3404) 0x4f6a00 ADD	X0, X0, #1

  (3404) 0x4f6a04 LDR	X4, [X24, X0,LSL #3]

  (3404) 0x4f6a08 UBFM	X2, X0, #61, #60

  (3404) 0x4f6a0c CMP	X1, X4

  (3404) 0x4f6a10 B.EQ	4f6e14

  (3404) 0x4f6a14 ADD	X0, X0, #1

  (3404) 0x4f6a18 LDR	X11, [X24, X0,LSL #3]

  (3404) 0x4f6a1c UBFM	X2, X0, #61, #60

  (3404) 0x4f6a20 CMP	X1, X11

  (3404) 0x4f6a24 B.EQ	4f6e14

  (3404) 0x4f6a28 ADD	X0, X0, #1

  (3404) 0x4f6a2c LDR	X12, [X24, X0,LSL #3]

  (3404) 0x4f6a30 UBFM	X2, X0, #61, #60

  (3404) 0x4f6a34 CMP	X1, X12

  (3404) 0x4f6a38 B.EQ	4f6e14

  (3404) 0x4f6a3c ADD	X0, X0, #1

  (3404) 0x4f6a40 CMP	X16, X0

  (3404) 0x4f6a44 B.EQ	4f6af0

    (3409) 0x4f6a48 LDR	X30, [X24, X0,LSL #3]

    (3409) 0x4f6a4c ADD	X4, X0, #1

    (3409) 0x4f6a50 ADD	X12, X0, #3

    (3409) 0x4f6a54 ADD	X11, X0, #2

    (3409) 0x4f6a58 ADD	X13, X0, #4

    (3409) 0x4f6a5c ADD	X14, X0, #5

    (3409) 0x4f6a60 ADD	X15, X0, #6

    (3409) 0x4f6a64 ADD	X25, X0, #7

    (3409) 0x4f6a68 UBFM	X2, X0, #61, #60

    (3409) 0x4f6a6c ADD	X0, X0, #8

    (3409) 0x4f6a70 CMP	X1, X30

    (3409) 0x4f6a74 B.EQ	4f6e14

    (3409) 0x4f6a78 LDR	X30, [X24, X4,LSL #3]

    (3409) 0x4f6a7c UBFM	X2, X4, #61, #60

    (3409) 0x4f6a80 CMP	X1, X30

    (3409) 0x4f6a84 B.EQ	4f6e14

    (3409) 0x4f6a88 LDR	X4, [X24, X11,LSL #3]

    (3409) 0x4f6a8c UBFM	X2, X11, #61, #60

    (3409) 0x4f6a90 CMP	X1, X4

    (3409) 0x4f6a94 B.EQ	4f6e14

    (3409) 0x4f6a98 LDR	X11, [X24, X12,LSL #3]

    (3409) 0x4f6a9c UBFM	X2, X12, #61, #60

    (3409) 0x4f6aa0 CMP	X1, X11

    (3409) 0x4f6aa4 B.EQ	4f6e14

    (3409) 0x4f6aa8 LDR	X12, [X24, X13,LSL #3]

    (3409) 0x4f6aac UBFM	X2, X13, #61, #60

    (3409) 0x4f6ab0 CMP	X1, X12

    (3409) 0x4f6ab4 B.EQ	4f6e14

    (3409) 0x4f6ab8 LDR	X13, [X24, X14,LSL #3]

    (3409) 0x4f6abc UBFM	X2, X14, #61, #60

    (3409) 0x4f6ac0 CMP	X1, X13

    (3409) 0x4f6ac4 B.EQ	4f6e14

    (3409) 0x4f6ac8 LDR	X14, [X24, X15,LSL #3]

    (3409) 0x4f6acc UBFM	X2, X15, #61, #60

    (3409) 0x4f6ad0 CMP	X1, X14

    (3409) 0x4f6ad4 B.EQ	4f6e14

    (3409) 0x4f6ad8 LDR	X15, [X24, X25,LSL #3]

    (3409) 0x4f6adc UBFM	X2, X25, #61, #60

    (3409) 0x4f6ae0 CMP	X1, X15

    (3409) 0x4f6ae4 B.EQ	4f6e14

    (3409) 0x4f6ae8 CMP	X16, X0

    (3409) 0x4f6aec B.NE	4f6a48

  (3404) 0x4f6af0 LDR	X25, [SP, #168]

  (3404) 0x4f6af4 CMP	X25, X10

  (3404) 0x4f6af8 B.LE	4f7400

  (3404) 0x4f6afc LDR	D0, [X5, X21,LSL #3]

  (3404) 0x4f6b00 UBFM	X0, X10, #61, #60

  (3404) 0x4f6b04 STR	X1, [X24, X10,LSL #3]

  (3404) 0x4f6b08 ADD	X10, X10, #1

  (3404) 0x4f6b0c STR	D0, [X7, X0]

  (3404) 0x4f6b10 B	4f6910

      (3396) 0x4f6b14 LDR	X18, [SP, #128]

      (3396) 0x4f6b18 ADD	X21, X21, X2

      (3396) 0x4f6b1c CBZ	X18, 4f6940

      (3396) 0x4f6b20 LDR	X15, [SP, #152]

      (3396) 0x4f6b24 CMP	X15, #0

      (3396) 0x4f6b28 B.LE	4f6940

      (3396) 0x4f6b2c ADD	X14, X27, X2,LSL #3

      (3396) 0x4f6b30 MOVZ	X11, #0

      (3396) 0x4f6b34 LDR	X6, [SP, #160]

      (3396) 0x4f6b38 LDP	X7, X10, [SP, #176]

      (3396) 0x4f6b3c B	4f6b4c

        (3397) 0x4f6b40 ADD	X6, X6, #16

        (3397) 0x4f6b44 CMP	X7, X6

        (3397) 0x4f6b48 B.EQ	4f6940

        (3397) 0x4f6b4c LDP	X30, X4, [X6]

        (3397) 0x4f6b50 ORR	X28, XZR, X11

        (3397) 0x4f6b54 ADD	X11, X11, X4

        (3397) 0x4f6b58 CMP	X25, X30

        (3397) 0x4f6b5c B.NE	4f6b40

        (3397) 0x4f6b60 CMP	X2, #0

        (3397) 0x4f6b64 B.LE	4f6b40

        (3397) 0x4f6b68 CMP	X4, #0

        (3397) 0x4f6b6c B.LE	4f6b40

        (3397) 0x4f6b70 ADD	X12, X10, X28,LSL #3

        (3397) 0x4f6b74 ORR	X3, XZR, X27

        (3397) 0x4f6b78 ADD	X4, X10, X11,LSL #3

        (3397) 0x4f6b7c HINT	#0

          (3399) 0x4f6b80 SUB	X1, X4, X12

          (3399) 0x4f6b84 ORR	X0, XZR, X12

          (3399) 0x4f6b88 SUB	X13, X1, #8

          (3399) 0x4f6b8c UBFM	X16, X13, #3, #63

          (3399) 0x4f6b90 ADD	X17, X16, #1

          (3399) 0x4f6b94 ANDS	X18, X17, #4224

          (3399) 0x4f6b98 B.EQ	4f6c70

          (3399) 0x4f6b9c CMP	X18, #1

          (3399) 0x4f6ba0 B.EQ	4f6c44

          (3399) 0x4f6ba4 CMP	X18, #2

          (3399) 0x4f6ba8 B.EQ	4f6c30

          (3399) 0x4f6bac CMP	X18, #3

          (3399) 0x4f6bb0 B.EQ	4f6c1c

          (3399) 0x4f6bb4 CMP	X18, #4

          (3399) 0x4f6bb8 B.EQ	4f6c08

          (3399) 0x4f6bbc CMP	X18, #5

          (3399) 0x4f6bc0 B.EQ	4f6bf4

          (3399) 0x4f6bc4 CMP	X18, #6

          (3399) 0x4f6bc8 B.EQ	4f6be0

          (3399) 0x4f6bcc LDR	X15, [X3]

          (3399) 0x4f6bd0 LDR	X28, [X12]

          (3399) 0x4f6bd4 CMP	X28, X15

          (3399) 0x4f6bd8 B.EQ	4f6df4

          (3399) 0x4f6bdc ADD	X0, X12, #8

          (3399) 0x4f6be0 LDR	X13, [X0]

          (3399) 0x4f6be4 LDR	X1, [X3]

          (3399) 0x4f6be8 CMP	X13, X1

          (3399) 0x4f6bec B.EQ	4f6de0

          (3399) 0x4f6bf0 ADD	X0, X0, #8

          (3399) 0x4f6bf4 LDR	X18, [X0]

          (3399) 0x4f6bf8 LDR	X15, [X3]

          (3399) 0x4f6bfc CMP	X18, X15

          (3399) 0x4f6c00 B.EQ	4f6dcc

          (3399) 0x4f6c04 ADD	X0, X0, #8

          (3399) 0x4f6c08 LDR	X13, [X0]

          (3399) 0x4f6c0c LDR	X1, [X3]

          (3399) 0x4f6c10 CMP	X13, X1

          (3399) 0x4f6c14 B.EQ	4f6db8

          (3399) 0x4f6c18 ADD	X0, X0, #8

          (3399) 0x4f6c1c LDR	X18, [X0]

          (3399) 0x4f6c20 LDR	X15, [X3]

          (3399) 0x4f6c24 CMP	X18, X15

          (3399) 0x4f6c28 B.EQ	4f6da4

          (3399) 0x4f6c2c ADD	X0, X0, #8

          (3399) 0x4f6c30 LDR	X13, [X0]

          (3399) 0x4f6c34 LDR	X1, [X3]

          (3399) 0x4f6c38 CMP	X13, X1

          (3399) 0x4f6c3c B.EQ	4f6d90

          (3399) 0x4f6c40 ADD	X0, X0, #8

          (3399) 0x4f6c44 LDR	X18, [X0]

          (3399) 0x4f6c48 LDR	X15, [X3]

          (3399) 0x4f6c4c CMP	X18, X15

          (3399) 0x4f6c50 B.NE	4f6c64

          (3399) 0x4f6c54 STR	X22, [X0]

          (3399) 0x4f6c58 LDR	X28, [X20, X19]

          (3399) 0x4f6c5c ADD	X30, X28, #1

          (3399) 0x4f6c60 STR	X30, [X20, X19]

          (3399) 0x4f6c64 ADD	X0, X0, #8

          (3399) 0x4f6c68 CMP	X4, X0

          (3399) 0x4f6c6c B.EQ	4f6d80

            (3398) 0x4f6c70 LDR	X13, [X0]

            (3398) 0x4f6c74 LDR	X1, [X3]

            (3398) 0x4f6c78 CMP	X13, X1

            (3398) 0x4f6c7c B.NE	4f6c90

            (3398) 0x4f6c80 STR	X22, [X0]

            (3398) 0x4f6c84 LDR	X16, [X20, X19]

            (3398) 0x4f6c88 ADD	X17, X16, #1

            (3398) 0x4f6c8c STR	X17, [X20, X19]

            (3398) 0x4f6c90 LDR	X28, [X3]

            (3398) 0x4f6c94 ADD	X18, X0, #8

            (3398) 0x4f6c98 LDR	X15, [X0, #8]

            (3398) 0x4f6c9c CMP	X15, X28

            (3398) 0x4f6ca0 B.NE	4f6cb4

            (3398) 0x4f6ca4 STR	X22, [X0, #8]

            (3398) 0x4f6ca8 LDR	X0, [X20, X19]

            (3398) 0x4f6cac ADD	X30, X0, #1

            (3398) 0x4f6cb0 STR	X30, [X20, X19]

            (3398) 0x4f6cb4 LDR	X1, [X3]

            (3398) 0x4f6cb8 LDR	X13, [X18, #8]

            (3398) 0x4f6cbc CMP	X13, X1

            (3398) 0x4f6cc0 B.NE	4f6cd4

            (3398) 0x4f6cc4 STR	X22, [X18, #8]

            (3398) 0x4f6cc8 LDR	X16, [X20, X19]

            (3398) 0x4f6ccc ADD	X17, X16, #1

            (3398) 0x4f6cd0 STR	X17, [X20, X19]

            (3398) 0x4f6cd4 LDR	X28, [X3]

            (3398) 0x4f6cd8 LDR	X15, [X18, #16]

            (3398) 0x4f6cdc CMP	X15, X28

            (3398) 0x4f6ce0 B.NE	4f6cf4

            (3398) 0x4f6ce4 STR	X22, [X18, #16]

            (3398) 0x4f6ce8 LDR	X0, [X20, X19]

            (3398) 0x4f6cec ADD	X30, X0, #1

            (3398) 0x4f6cf0 STR	X30, [X20, X19]

            (3398) 0x4f6cf4 LDR	X1, [X3]

            (3398) 0x4f6cf8 LDR	X13, [X18, #24]

            (3398) 0x4f6cfc CMP	X13, X1

            (3398) 0x4f6d00 B.NE	4f6d14

            (3398) 0x4f6d04 STR	X22, [X18, #24]

            (3398) 0x4f6d08 LDR	X16, [X20, X19]

            (3398) 0x4f6d0c ADD	X17, X16, #1

            (3398) 0x4f6d10 STR	X17, [X20, X19]

            (3398) 0x4f6d14 LDR	X28, [X3]

            (3398) 0x4f6d18 LDR	X15, [X18, #32]

            (3398) 0x4f6d1c CMP	X15, X28

            (3398) 0x4f6d20 B.NE	4f6d34

            (3398) 0x4f6d24 STR	X22, [X18, #32]

            (3398) 0x4f6d28 LDR	X0, [X20, X19]

            (3398) 0x4f6d2c ADD	X30, X0, #1

            (3398) 0x4f6d30 STR	X30, [X20, X19]

            (3398) 0x4f6d34 LDR	X1, [X3]

            (3398) 0x4f6d38 LDR	X13, [X18, #40]

            (3398) 0x4f6d3c CMP	X13, X1

            (3398) 0x4f6d40 B.NE	4f6d54

            (3398) 0x4f6d44 STR	X22, [X18, #40]

            (3398) 0x4f6d48 LDR	X16, [X20, X19]

            (3398) 0x4f6d4c ADD	X17, X16, #1

            (3398) 0x4f6d50 STR	X17, [X20, X19]

            (3398) 0x4f6d54 LDR	X28, [X3]

            (3398) 0x4f6d58 LDR	X15, [X18, #48]

            (3398) 0x4f6d5c CMP	X15, X28

            (3398) 0x4f6d60 B.NE	4f6d74

            (3398) 0x4f6d64 STR	X22, [X18, #48]

            (3398) 0x4f6d68 LDR	X0, [X20, X19]

            (3398) 0x4f6d6c ADD	X30, X0, #1

            (3398) 0x4f6d70 STR	X30, [X20, X19]

            (3398) 0x4f6d74 ADD	X0, X18, #56

            (3398) 0x4f6d78 CMP	X4, X0

            (3398) 0x4f6d7c B.NE	4f6c70

          (3399) 0x4f6d80 ADD	X3, X3, #8

          (3399) 0x4f6d84 CMP	X14, X3

          (3399) 0x4f6d88 B.NE	4f6b80

        (3397) 0x4f6d8c B	4f6b40

          (3399) 0x4f6d90 STR	X22, [X0]

          (3399) 0x4f6d94 LDR	X16, [X20, X19]

          (3399) 0x4f6d98 ADD	X17, X16, #1

          (3399) 0x4f6d9c STR	X17, [X20, X19]

          (3399) 0x4f6da0 B	4f6c40

          (3399) 0x4f6da4 STR	X22, [X0]

          (3399) 0x4f6da8 LDR	X28, [X20, X19]

          (3399) 0x4f6dac ADD	X30, X28, #1

          (3399) 0x4f6db0 STR	X30, [X20, X19]

          (3399) 0x4f6db4 B	4f6c2c

          (3399) 0x4f6db8 STR	X22, [X0]

          (3399) 0x4f6dbc LDR	X16, [X20, X19]

          (3399) 0x4f6dc0 ADD	X17, X16, #1

          (3399) 0x4f6dc4 STR	X17, [X20, X19]

          (3399) 0x4f6dc8 B	4f6c18

          (3399) 0x4f6dcc STR	X22, [X0]

          (3399) 0x4f6dd0 LDR	X28, [X20, X19]

          (3399) 0x4f6dd4 ADD	X30, X28, #1

          (3399) 0x4f6dd8 STR	X30, [X20, X19]

          (3399) 0x4f6ddc B	4f6c04

          (3399) 0x4f6de0 STR	X22, [X0]

          (3399) 0x4f6de4 LDR	X16, [X20, X19]

          (3399) 0x4f6de8 ADD	X17, X16, #1

          (3399) 0x4f6dec STR	X17, [X20, X19]

          (3399) 0x4f6df0 B	4f6bf0

          (3399) 0x4f6df4 STR	X22, [X12]

          (3399) 0x4f6df8 LDR	X30, [X20, X19]

          (3399) 0x4f6dfc ADD	X0, X30, #1

          (3399) 0x4f6e00 STR	X0, [X20, X19]

          (3399) 0x4f6e04 B	4f6bdc

      (3406) 0x4f6e08 LDR	D3, [X5, X21,LSL #3]

      (3406) 0x4f6e0c STR	D3, [X19, X2]

      (3406) 0x4f6e10 B	4f6910

  (3404) 0x4f6e14 LDR	D1, [X5, X21,LSL #3]

  (3404) 0x4f6e18 STR	D1, [X7, X2]

  (3404) 0x4f6e1c B	4f6910

      (3396) 0x4f6e20 LDR	X1, [SP, #200]

      (3396) 0x4f6e24 LDR	X0, [SP, #240]

      (3396) 0x4f6e28 LDR	X11, [SP, #248]

      (3396) 0x4f6e2c LDR	X28, [X1, X14,LSL #3]

      (3396) 0x4f6e30 LDR	X30, [X0, X14,LSL #3]

      (3396) 0x4f6e34 LDR	X12, [X11, X14,LSL #3]

      (3396) 0x4f6e38 LDR	X4, [SP, #256]

      (3396) 0x4f6e3c SUB	X17, X30, X28

      (3396) 0x4f6e40 STP	X12, X30, [SP, #208]

      (3396) 0x4f6e44 LDR	X25, [X4, X14,LSL #3]

      (3396) 0x4f6e48 CMP	X2, X17

      (3396) 0x4f6e4c B.GT	4f72b8

      (3396) 0x4f6e50 CMP	X2, #0

      (3396) 0x4f6e54 B.LE	4f6940

      (3396) 0x4f6e58 MOVZ	X7, #0

      (3396) 0x4f6e5c ADD	X3, X21, X2

      (3396) 0x4f6e60 STR	X20, [SP, #264]

      (3396) 0x4f6e64 ORR	X11, XZR, X28

      (3396) 0x4f6e68 ORR	X20, XZR, X3

      (3396) 0x4f6e6c MOVZ	X13, #0

      (3396) 0x4f6e70 LDR	X30, [SP, #208]

      (3396) 0x4f6e74 STR	X3, [SP, #168]

      (3396) 0x4f6e78 LDR	X3, [SP, #216]

      (3396) 0x4f6e7c STR	X14, [SP, #208]

        (3400) 0x4f6e80 MOVZ	X0, #0

        (3400) 0x4f6e84 LDR	X1, [X27, X21,LSL #3]

        (3400) 0x4f6e88 CMP	X28, #0

        (3400) 0x4f6e8c B.LE	4f7004

        (3400) 0x4f6e90 ANDS	X6, X28, #4224

        (3400) 0x4f6e94 B.EQ	4f6f5c

        (3400) 0x4f6e98 CMP	X6, #1

        (3400) 0x4f6e9c B.EQ	4f6f40

        (3400) 0x4f6ea0 CMP	X6, #2

        (3400) 0x4f6ea4 B.EQ	4f6f2c

        (3400) 0x4f6ea8 CMP	X6, #3

        (3400) 0x4f6eac B.EQ	4f6f18

        (3400) 0x4f6eb0 CMP	X6, #4

        (3400) 0x4f6eb4 B.EQ	4f6f04

        (3400) 0x4f6eb8 CMP	X6, #5

        (3400) 0x4f6ebc B.EQ	4f6ef0

        (3400) 0x4f6ec0 CMP	X6, #6

        (3400) 0x4f6ec4 B.EQ	4f6edc

        (3400) 0x4f6ec8 LDR	X16, [X25]

        (3400) 0x4f6ecc MOVZ	X2, #0

        (3400) 0x4f6ed0 CMP	X16, X1

        (3400) 0x4f6ed4 B.EQ	4f7268

        (3400) 0x4f6ed8 MOVZ	X0, #1

        (3400) 0x4f6edc LDR	X18, [X25, X0,LSL #3]

        (3400) 0x4f6ee0 UBFM	X2, X0, #61, #60

        (3400) 0x4f6ee4 CMP	X18, X1

        (3400) 0x4f6ee8 B.EQ	4f7268

        (3400) 0x4f6eec ADD	X0, X0, #1

        (3400) 0x4f6ef0 LDR	X10, [X25, X0,LSL #3]

        (3400) 0x4f6ef4 UBFM	X2, X0, #61, #60

        (3400) 0x4f6ef8 CMP	X10, X1

        (3400) 0x4f6efc B.EQ	4f7268

        (3400) 0x4f6f00 ADD	X0, X0, #1

        (3400) 0x4f6f04 LDR	X17, [X25, X0,LSL #3]

        (3400) 0x4f6f08 UBFM	X2, X0, #61, #60

        (3400) 0x4f6f0c CMP	X17, X1

        (3400) 0x4f6f10 B.EQ	4f7268

        (3400) 0x4f6f14 ADD	X0, X0, #1

        (3400) 0x4f6f18 LDR	X4, [X25, X0,LSL #3]

        (3400) 0x4f6f1c UBFM	X2, X0, #61, #60

        (3400) 0x4f6f20 CMP	X4, X1

        (3400) 0x4f6f24 B.EQ	4f7268

        (3400) 0x4f6f28 ADD	X0, X0, #1

        (3400) 0x4f6f2c LDR	X12, [X25, X0,LSL #3]

        (3400) 0x4f6f30 UBFM	X2, X0, #61, #60

        (3400) 0x4f6f34 CMP	X12, X1

        (3400) 0x4f6f38 B.EQ	4f7268

        (3400) 0x4f6f3c ADD	X0, X0, #1

        (3400) 0x4f6f40 LDR	X14, [X25, X0,LSL #3]

        (3400) 0x4f6f44 UBFM	X2, X0, #61, #60

        (3400) 0x4f6f48 CMP	X14, X1

        (3400) 0x4f6f4c B.EQ	4f7268

        (3400) 0x4f6f50 ADD	X0, X0, #1

        (3400) 0x4f6f54 CMP	X28, X0

        (3400) 0x4f6f58 B.EQ	4f7004

          (3402) 0x4f6f5c LDR	X18, [X25, X0,LSL #3]

          (3402) 0x4f6f60 ADD	X4, X0, #1

          (3402) 0x4f6f64 ADD	X10, X0, #3

          (3402) 0x4f6f68 ADD	X6, X0, #2

          (3402) 0x4f6f6c ADD	X12, X0, #4

          (3402) 0x4f6f70 ADD	X15, X0, #5

          (3402) 0x4f6f74 ADD	X16, X0, #6

          (3402) 0x4f6f78 ADD	X17, X0, #7

          (3402) 0x4f6f7c UBFM	X2, X0, #61, #60

          (3402) 0x4f6f80 ADD	X0, X0, #8

          (3402) 0x4f6f84 CMP	X18, X1

          (3402) 0x4f6f88 B.EQ	4f7268

          (3402) 0x4f6f8c LDR	X14, [X25, X4,LSL #3]

          (3402) 0x4f6f90 UBFM	X2, X4, #61, #60

          (3402) 0x4f6f94 CMP	X14, X1

          (3402) 0x4f6f98 B.EQ	4f7268

          (3402) 0x4f6f9c LDR	X4, [X25, X6,LSL #3]

          (3402) 0x4f6fa0 UBFM	X2, X6, #61, #60

          (3402) 0x4f6fa4 CMP	X4, X1

          (3402) 0x4f6fa8 B.EQ	4f7268

          (3402) 0x4f6fac LDR	X18, [X25, X10,LSL #3]

          (3402) 0x4f6fb0 UBFM	X2, X10, #61, #60

          (3402) 0x4f6fb4 CMP	X18, X1

          (3402) 0x4f6fb8 B.EQ	4f7268

          (3402) 0x4f6fbc LDR	X10, [X25, X12,LSL #3]

          (3402) 0x4f6fc0 UBFM	X2, X12, #61, #60

          (3402) 0x4f6fc4 CMP	X10, X1

          (3402) 0x4f6fc8 B.EQ	4f7268

          (3402) 0x4f6fcc LDR	X6, [X25, X15,LSL #3]

          (3402) 0x4f6fd0 UBFM	X2, X15, #61, #60

          (3402) 0x4f6fd4 CMP	X6, X1

          (3402) 0x4f6fd8 B.EQ	4f7268

          (3402) 0x4f6fdc LDR	X12, [X25, X16,LSL #3]

          (3402) 0x4f6fe0 UBFM	X2, X16, #61, #60

          (3402) 0x4f6fe4 CMP	X12, X1

          (3402) 0x4f6fe8 B.EQ	4f7268

          (3402) 0x4f6fec LDR	X15, [X25, X17,LSL #3]

          (3402) 0x4f6ff0 UBFM	X2, X17, #61, #60

          (3402) 0x4f6ff4 CMP	X15, X1

          (3402) 0x4f6ff8 B.EQ	4f7268

          (3402) 0x4f6ffc CMP	X28, X0

          (3402) 0x4f7000 B.NE	4f6f5c

        (3400) 0x4f7004 LDR	D4, [X5, X21,LSL #3]

        (3400) 0x4f7008 CMP	X3, X11

        (3400) 0x4f700c B.LE	4f7274

        (3400) 0x4f7010 UBFM	X17, X11, #61, #60

        (3400) 0x4f7014 STR	X1, [X25, X11,LSL #3]

        (3400) 0x4f7018 ADD	X11, X11, #1

        (3400) 0x4f701c STR	D4, [X30, X17]

        (3400) 0x4f7020 ADD	X21, X21, #1

        (3400) 0x4f7024 CMP	X21, X20

        (3400) 0x4f7028 B.NE	4f6e80

      (3396) 0x4f702c LDP	X0, X14, [SP, #200]

      (3396) 0x4f7030 ADD	X21, X11, X13

      (3396) 0x4f7034 LDR	X20, [SP, #264]

      (3396) 0x4f7038 STR	X21, [X0, X14,LSL #3]

      (3396) 0x4f703c CBNZ	X13, 4f704c

      (3396) 0x4f7040 CBNZ	X7, 4f723c

      (3396) 0x4f7044 LDR	X21, [SP, #168]

      (3396) 0x4f7048 B	4f6940

      (3396) 0x4f704c LDR	X28, [SP, #256]

      (3396) 0x4f7050 UBFM	X25, X21, #61, #60

      (3396) 0x4f7054 ORR	X1, XZR, X25

      (3396) 0x4f7058 STP	X14, X7, [SP, #208]

      (3396) 0x4f705c STP	X11, X13, [SP, #264]

      (3396) 0x4f7060 LDR	X0, [X28, X14,LSL #3]

      (3396) 0x4f7064 STR	X8, [SP, #280]

      (3396) 0x4f7068 STP	X9, X5, [SP, #304]

      (3396) 0x4f706c BL	51678c

      (3396) 0x4f7070 ORR	X1, XZR, X25

      (3396) 0x4f7074 LDR	X8, [SP, #208]

      (3396) 0x4f7078 ORR	X7, XZR, X0

      (3396) 0x4f707c LDR	X25, [SP, #248]

      (3396) 0x4f7080 LDR	X0, [X25, X8,LSL #3]

      (3396) 0x4f7084 STR	X7, [X28, X8,LSL #3]

      (3396) 0x4f7088 BL	51678c

      (3396) 0x4f708c LDP	X6, X7, [SP, #208]

      (3396) 0x4f7090 ORR	X18, XZR, X0

      (3396) 0x4f7094 MOVZ	X0, #0

      (3396) 0x4f7098 LDP	X4, X13, [SP, #264]

      (3396) 0x4f709c LDP	X9, X5, [SP, #304]

      (3396) 0x4f70a0 UBFM	X15, X4, #61, #60

      (3396) 0x4f70a4 ANDS	X11, X13, #4224

      (3396) 0x4f70a8 ADD	X1, X18, X15

      (3396) 0x4f70ac LDR	X12, [SP, #240]

      (3396) 0x4f70b0 LDR	X10, [X28, X6,LSL #3]

      (3396) 0x4f70b4 STR	X18, [X25, X6,LSL #3]

      (3396) 0x4f70b8 LDR	X8, [SP, #280]

      (3396) 0x4f70bc STR	X21, [X12, X6,LSL #3]

      (3396) 0x4f70c0 ADD	X2, X10, X15

      (3396) 0x4f70c4 B.EQ	4f7478

      (3396) 0x4f70c8 CMP	X11, #1

      (3396) 0x4f70cc B.EQ	4f7170

      (3396) 0x4f70d0 CMP	X11, #2

      (3396) 0x4f70d4 B.EQ	4f7158

      (3396) 0x4f70d8 CMP	X11, #3

      (3396) 0x4f70dc B.EQ	4f7140

      (3396) 0x4f70e0 CMP	X11, #4

      (3396) 0x4f70e4 B.EQ	4f7128

      (3396) 0x4f70e8 CMP	X11, #5

      (3396) 0x4f70ec B.EQ	4f7110

      (3396) 0x4f70f0 CMP	X11, #6

      (3396) 0x4f70f4 B.NE	4f738c

      (3396) 0x4f70f8 LDR	X30, [SP, #136]

      (3396) 0x4f70fc LDR	X3, [X7, X0,LSL #3]

      (3396) 0x4f7100 LDR	D7, [X30, X0,LSL #3]

      (3396) 0x4f7104 STR	X3, [X2, X0,LSL #3]

      (3396) 0x4f7108 STR	D7, [X1, X0,LSL #3]

      (3396) 0x4f710c ADD	X0, X0, #1

      (3396) 0x4f7110 LDR	X21, [SP, #136]

      (3396) 0x4f7114 LDR	X14, [X7, X0,LSL #3]

      (3396) 0x4f7118 LDR	D16, [X21, X0,LSL #3]

      (3396) 0x4f711c STR	X14, [X2, X0,LSL #3]

      (3396) 0x4f7120 STR	D16, [X1, X0,LSL #3]

      (3396) 0x4f7124 ADD	X0, X0, #1

      (3396) 0x4f7128 LDR	X25, [SP, #136]

      (3396) 0x4f712c LDR	X28, [X7, X0,LSL #3]

      (3396) 0x4f7130 LDR	D17, [X25, X0,LSL #3]

      (3396) 0x4f7134 STR	X28, [X2, X0,LSL #3]

      (3396) 0x4f7138 STR	D17, [X1, X0,LSL #3]

      (3396) 0x4f713c ADD	X0, X0, #1

      (3396) 0x4f7140 LDR	X6, [SP, #136]

      (3396) 0x4f7144 LDR	X18, [X7, X0,LSL #3]

      (3396) 0x4f7148 LDR	D18, [X6, X0,LSL #3]

      (3396) 0x4f714c STR	X18, [X2, X0,LSL #3]

      (3396) 0x4f7150 STR	D18, [X1, X0,LSL #3]

      (3396) 0x4f7154 ADD	X0, X0, #1

      (3396) 0x4f7158 LDR	X4, [SP, #136]

      (3396) 0x4f715c LDR	X12, [X7, X0,LSL #3]

      (3396) 0x4f7160 LDR	D19, [X4, X0,LSL #3]

      (3396) 0x4f7164 STR	X12, [X2, X0,LSL #3]

      (3396) 0x4f7168 STR	D19, [X1, X0,LSL #3]

      (3396) 0x4f716c ADD	X0, X0, #1

      (3396) 0x4f7170 LDR	X3, [SP, #136]

      (3396) 0x4f7174 LDR	X10, [X7, X0,LSL #3]

      (3396) 0x4f7178 LDR	D20, [X3, X0,LSL #3]

      (3396) 0x4f717c ORR	X16, XZR, X3

      (3396) 0x4f7180 STR	X10, [X2, X0,LSL #3]

      (3396) 0x4f7184 STR	D20, [X1, X0,LSL #3]

      (3396) 0x4f7188 ADD	X0, X0, #1

      (3396) 0x4f718c CMP	X13, X0

      (3396) 0x4f7190 B.EQ	4f723c

        (3401) 0x4f7194 LDR	X17, [X7, X0,LSL #3]

        (3401) 0x4f7198 ADD	X30, X0, #1

        (3401) 0x4f719c ADD	X15, X0, #2

        (3401) 0x4f71a0 ADD	X14, X0, #3

        (3401) 0x4f71a4 ADD	X11, X0, #4

        (3401) 0x4f71a8 LDR	D21, [X16, X0,LSL #3]

        (3401) 0x4f71ac ADD	X18, X0, #5

        (3401) 0x4f71b0 ADD	X6, X0, #6

        (3401) 0x4f71b4 ADD	X4, X0, #7

        (3401) 0x4f71b8 STR	X17, [X2, X0,LSL #3]

        (3401) 0x4f71bc LDR	X21, [X7, X30,LSL #3]

        (3401) 0x4f71c0 STR	D21, [X1, X0,LSL #3]

        (3401) 0x4f71c4 ADD	X0, X0, #8

        (3401) 0x4f71c8 LDR	D22, [X16, X30,LSL #3]

        (3401) 0x4f71cc STR	X21, [X2, X30,LSL #3]

        (3401) 0x4f71d0 LDR	X28, [X7, X15,LSL #3]

        (3401) 0x4f71d4 STR	D22, [X1, X30,LSL #3]

        (3401) 0x4f71d8 LDR	D23, [X16, X15,LSL #3]

        (3401) 0x4f71dc STR	X28, [X2, X15,LSL #3]

        (3401) 0x4f71e0 LDR	X25, [X7, X14,LSL #3]

        (3401) 0x4f71e4 STR	D23, [X1, X15,LSL #3]

        (3401) 0x4f71e8 LDR	D24, [X16, X14,LSL #3]

        (3401) 0x4f71ec STR	X25, [X2, X14,LSL #3]

        (3401) 0x4f71f0 LDR	X12, [X7, X11,LSL #3]

        (3401) 0x4f71f4 STR	D24, [X1, X14,LSL #3]

        (3401) 0x4f71f8 LDR	D25, [X16, X11,LSL #3]

        (3401) 0x4f71fc STR	X12, [X2, X11,LSL #3]

        (3401) 0x4f7200 LDR	X10, [X7, X18,LSL #3]

        (3401) 0x4f7204 STR	D25, [X1, X11,LSL #3]

        (3401) 0x4f7208 LDR	D26, [X16, X18,LSL #3]

        (3401) 0x4f720c STR	X10, [X2, X18,LSL #3]

        (3401) 0x4f7210 LDR	X3, [X7, X6,LSL #3]

        (3401) 0x4f7214 STR	D26, [X1, X18,LSL #3]

        (3401) 0x4f7218 LDR	D27, [X16, X6,LSL #3]

        (3401) 0x4f721c STR	X3, [X2, X6,LSL #3]

        (3401) 0x4f7220 LDR	X17, [X7, X4,LSL #3]

        (3401) 0x4f7224 STR	D27, [X1, X6,LSL #3]

        (3401) 0x4f7228 LDR	D28, [X16, X4,LSL #3]

        (3401) 0x4f722c STR	X17, [X2, X4,LSL #3]

        (3401) 0x4f7230 STR	D28, [X1, X4,LSL #3]

        (3401) 0x4f7234 CMP	X13, X0

        (3401) 0x4f7238 B.NE	4f7194

      (3396) 0x4f723c ORR	X0, XZR, X7

      (3396) 0x4f7240 STP	X8, X9, [SP, #208]

      (3396) 0x4f7244 STR	X5, [SP, #264]

      (3396) 0x4f7248 LDR	X21, [SP, #168]

      (3396) 0x4f724c BL	516820

      (3396) 0x4f7250 LDR	X0, [SP, #136]

      (3396) 0x4f7254 STR	XZR, [SP, #136]

      (3396) 0x4f7258 BL	516820

      (3396) 0x4f725c LDP	X8, X9, [SP, #208]

      (3396) 0x4f7260 LDR	X5, [SP, #264]

      (3396) 0x4f7264 B	4f6940

        (3400) 0x4f7268 LDR	D5, [X5, X21,LSL #3]

        (3400) 0x4f726c STR	D5, [X30, X2]

        (3400) 0x4f7270 B	4f7020

        (3400) 0x4f7274 STR	X1, [X7, X13,LSL #3]

        (3400) 0x4f7278 UBFM	X16, X13, #61, #60

        (3400) 0x4f727c ADD	X13, X13, #1

        (3400) 0x4f7280 LDR	X1, [SP, #136]

        (3400) 0x4f7284 STR	D4, [X1, X16]

        (3400) 0x4f7288 B	4f7020

0x4f728c STR	X15, [SP, #136]

0x4f7290 BL	40f590

0x4f7294 LDUR	X21, [X27, #504]

0x4f7298 LDR	X27, [SP, #136]

0x4f729c B	4f6654

0x4f72a0 MADD	X30, X0, X1, XZR

0x4f72a4 ADD	X3, X1, X30

0x4f72a8 ADD	X26, X2, X30

0x4f72ac ADD	X5, X3, X2

0x4f72b0 STR	X5, [SP, #96]

0x4f72b4 B	4f63cc

      (3396) 0x4f72b8 SUB	X13, X2, X17

      (3396) 0x4f72bc MOVZ	X1, #8

      (3396) 0x4f72c0 STP	X2, X14, [SP, #264]

      (3396) 0x4f72c4 ORR	X0, XZR, X13

      (3396) 0x4f72c8 STR	X13, [SP, #136]

      (3396) 0x4f72cc STR	X8, [SP, #280]

      (3396) 0x4f72d0 STP	X9, X5, [SP, #304]

      (3396) 0x4f72d4 BL	51674c

      (3396) 0x4f72d8 ORR	X9, XZR, X0

      (3396) 0x4f72dc MOVZ	X1, #8

      (3396) 0x4f72e0 LDR	X0, [SP, #136]

      (3396) 0x4f72e4 STR	X9, [SP, #168]

      (3396) 0x4f72e8 BL	51674c

      (3396) 0x4f72ec LDP	X2, X14, [SP, #264]

      (3396) 0x4f72f0 STR	X0, [SP, #136]

      (3396) 0x4f72f4 LDR	X7, [SP, #168]

      (3396) 0x4f72f8 CMP	X2, #0

      (3396) 0x4f72fc LDP	X9, X5, [SP, #304]

      (3396) 0x4f7300 LDR	X8, [SP, #280]

      (3396) 0x4f7304 B.GT	4f6e5c

      (3396) 0x4f7308 STR	X21, [SP, #168]

      (3396) 0x4f730c LDR	X15, [SP, #200]

      (3396) 0x4f7310 STR	X28, [X15, X14,LSL #3]

      (3396) 0x4f7314 B	4f7040

    (3403) 0x4f7318 ADRP	X26,

    (3403) 0x4f731c MOVZ	X3, #0

    (3403) 0x4f7320 STR	X6, [SP, #168]

    (3403) 0x4f7324 ADD	X0, X26, #3560

    (3403) 0x4f7328 MOVZ	X2, #1

    (3403) 0x4f732c STP	X5, X9, [SP, #208]

    (3403) 0x4f7330 MOVZ	X1, #3406

    (3403) 0x4f7334 STR	X10, [SP, #312]

    (3403) 0x4f7338 LDP	X20, X19, [SP, #264]

    (3403) 0x4f733c STR	X8, [SP, #264]

    (3403) 0x4f7340 LDR	X26, [SP, #280]

    (3403) 0x4f7344 LDR	X25, [SP, #304]

    (3403) 0x4f7348 BL	51a420

    (3403) 0x4f734c LDR	X7, [SP, #328]

    (3403) 0x4f7350 MOVZ	X18, #1

    (3403) 0x4f7354 LDR	X1, [X7, #224]

    (3403) 0x4f7358 LDADD	X18, X1, [X1]

    (3403) 0x4f735c LDP	X10, X3, [SP, #312]

    (3403) 0x4f7360 LDP	X5, X9, [SP, #208]

    (3403) 0x4f7364 LDR	X6, [SP, #168]

    (3403) 0x4f7368 LDR	X8, [SP, #264]

    (3403) 0x4f736c CBNZ	X3, 4f73b4

    (3405) 0x4f7370 ORR	X17, XZR, X21

    (3405) 0x4f7374 LDR	X21, [SP, #128]

    (3405) 0x4f7378 LDP	X16, X0, [X21, #56]

    (3405) 0x4f737c ADD	X30, X16, X6

    (3405) 0x4f7380 ADD	X6, X0, X6

    (3405) 0x4f7384 STP	X6, X30, [SP, #208]

    (3405) 0x4f7388 B	4f6924

      (3396) 0x4f738c LDR	X17, [SP, #136]

      (3396) 0x4f7390 MOVZ	X0, #1

      (3396) 0x4f7394 LDR	X16, [X7]

      (3396) 0x4f7398 LDR	D6, [X17]

      (3396) 0x4f739c STR	X16, [X10, X15]

      (3396) 0x4f73a0 STR	D6, [X18, X15]

      (3396) 0x4f73a4 B	4f70f8

0x4f73a8 LDR	X0, [X2], #8

0x4f73ac STR	X0, [X27]

0x4f73b0 B	4f6438

    (3403) 0x4f73b4 ADRP	X17,

    (3403) 0x4f73b8 ORR	X1, XZR, X25

    (3403) 0x4f73bc STR	X10, [SP, #168]

    (3403) 0x4f73c0 ADD	X0, X17, #3712

    (3403) 0x4f73c4 STR	X6, [SP, #208]

    (3403) 0x4f73c8 STP	X8, X9, [SP, #264]

    (3403) 0x4f73cc STR	X5, [SP, #280]

    (3403) 0x4f73d0 BL	5169a0

    (3403) 0x4f73d4 LDR	X4, [SP, #128]

    (3403) 0x4f73d8 ORR	X17, XZR, X21

    (3403) 0x4f73dc LDP	X8, X9, [SP, #264]

    (3403) 0x4f73e0 LDP	X12, X13, [X4, #56]

    (3403) 0x4f73e4 LDR	X11, [SP, #208]

    (3403) 0x4f73e8 LDR	X10, [SP, #168]

    (3403) 0x4f73ec LDR	X5, [SP, #280]

    (3403) 0x4f73f0 ADD	X14, X12, X11

    (3403) 0x4f73f4 ADD	X15, X13, X11

    (3403) 0x4f73f8 STP	X15, X14, [SP, #208]

    (3403) 0x4f73fc B	4f6924

  (3404) 0x4f7400 ADRP	X20,

  (3404) 0x4f7404 MOVZ	X3, #0

  (3404) 0x4f7408 STR	X6, [SP, #168]

  (3404) 0x4f740c ADD	X0, X20, #3560

  (3404) 0x4f7410 MOVZ	X2, #1

  (3404) 0x4f7414 STP	X5, X9, [SP, #208]

  (3404) 0x4f7418 MOVZ	X1, #3440

  (3404) 0x4f741c STR	X10, [SP, #312]

  (3404) 0x4f7420 LDP	X20, X19, [SP, #264]

  (3404) 0x4f7424 STR	X8, [SP, #264]

  (3404) 0x4f7428 LDR	X26, [SP, #280]

  (3404) 0x4f742c LDR	X25, [SP, #304]

  (3404) 0x4f7430 BL	51a420

  (3404) 0x4f7434 LDR	X8, [SP, #328]

  (3404) 0x4f7438 MOVZ	X9, #1

  (3404) 0x4f743c LDR	X5, [X8, #224]

  (3404) 0x4f7440 LDADD	X9, X1, [X5]

  (3404) 0x4f7444 LDP	X10, X3, [SP, #312]

  (3404) 0x4f7448 LDP	X5, X9, [SP, #208]

  (3404) 0x4f744c LDR	X6, [SP, #168]

  (3404) 0x4f7450 LDR	X8, [SP, #264]

  (3404) 0x4f7454 CBZ	X3, 4f7370

  (3404) 0x4f7458 ADRP	X17,

  (3404) 0x4f745c ORR	X1, XZR, X25

  (3404) 0x4f7460 STR	X10, [SP, #168]

  (3404) 0x4f7464 ADD	X0, X17, #3752

  (3404) 0x4f7468 STR	X6, [SP, #208]

  (3404) 0x4f746c STP	X8, X9, [SP, #264]

  (3404) 0x4f7470 STR	X5, [SP, #280]

  (3404) 0x4f7474 B	4f73d0

      (3396) 0x4f7478 LDR	X16, [SP, #136]

      (3396) 0x4f747c B	4f7194

    (3403) 0x4f7480 ORR	X17, XZR, X21

    (3403) 0x4f7484 B	4f6924

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	IJMatrix_parcsr.c:3240-3500
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:3240,3256-3353,3359-3368,3376-3412,3422-3446,3454-3458,3466-3484,3500.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 34.50 to 10.00 cycles (3.45x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 34.50 to 2.50 cycles (13.80x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 448 bytes. The binary function is storing 464 bytes.

General properties

nb instructions	202
loop length	808
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

25.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	14.50	14.50	20.75	20.75	20.75	20.75	0.00	0.00	0.00	0.00	34.50	34.17	34.33	25.50	25.50
cycles	14.50	14.50	20.75	20.75	20.75	20.75	0.00	0.00	0.00	0.00	34.50	34.17	34.33	25.50	25.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	25.25
Overall L1	34.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 34.50 cycles. At this rate:

13% of peak load performance is reached (12.99 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
28% of peak store performance is reached (13.45 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4f62c8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #688]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X26, X1, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X15, X28, [X0, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X2, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X0, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [X0, #56]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X15, X1, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X5, [X0, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X2, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X6, [X0, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X3, [SP, #128]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X7, [X0, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X5, [SP, #168]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [SP, #208]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X6, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X0, [SP, #328]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X25, [X0, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X7, [SP, #248]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X0, #88]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X22, X20, [X0, #192]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X9, [X0, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #200]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X0, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X0, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X9, [SP, #240]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X24, [X0, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #192]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X0, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X11, [SP, #232]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [X0, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X0, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X12, [SP, #296]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X0, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X13, [SP, #224]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X0, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X0, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X14, [SP, #288]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X0, #176]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X16, [SP, #120]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X19, [X0, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X21, X0, [X0, #208]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X17, [SP, #152]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X18, [SP, #160]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X0, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X19, [SP, #184]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X21, [SP, #320]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 519560 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR X27, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 519580 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SDIV X1, X26, X27	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X15, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MSUB X2, X1, X27, X26	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4f72a0 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xfd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MADD X26, X1, X0, X0	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD X4, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X5, X4, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X5, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X19, X21, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X22, X21,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X27, X22, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X26, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4f64f8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x230>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X7, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X2, X7, X26,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X8, X7, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X9, X8, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X10, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X11, X10, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X12, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ANDS X13, X12, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4f6488 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4f6474 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4f6468 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X13, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4f645c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x194>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X13, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4f6450 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X13, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4f6444 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x17c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X13, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 4f73a8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x10e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [X2], #8	1	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X0, [X27]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X2], #8	1	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X0, [X27]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X17, [X2], #8	1	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X0, [X27]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X2], #8	1	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X0, [X27]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X1, [X2], #8	1	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X0, [X27]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X30, [X2], #8	1	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X0, [X27]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X8, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4f64f8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x230>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X15, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f590 <@plt_start@+0x3a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X15, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X21, 4f728c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xfc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4f6648 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x380>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X0, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X9, X22, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X1, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X3, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X16, [X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X4, X3, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X5, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ANDS X6, X5, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4f65c4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x2fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4f65b0 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x2e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4f65a4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x2dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4f6598 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4f658c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x2c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4f6580 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x2b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4f6574 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x2ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X22, [X22, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X16, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X16, [X1, #8]!	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X7, [X1, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X16, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X16, [X1, #8]!	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X1, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X16, [X1, #8]!	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X11, [X1, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X16, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X16, [X1, #8]!	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X1, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X16, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X16, [X1, #8]!	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [X1, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X16, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X16, [X1, #8]!	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X1, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X16, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X16, [X1, #8]!	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X9, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4f6648 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x380>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X15, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f590 <@plt_start@+0x3a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X27, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X26, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4f6950 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x688>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X30, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X5, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVN X22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X28, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [SP, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X4, X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X8, [SP, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X0, X4, #1, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X2, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X9, [SP, #208]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X10, X25, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X6, X1, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X25, X25, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X7, X6, X0,LSL #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [SP, #120]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X25, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X7, [SP, #176]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X15, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f590 <@plt_start@+0x3a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDUR X21, [X27, #504]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4f6654 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x38c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MADD X30, X0, X1, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD X3, X1, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X26, X2, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X5, X3, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X5, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4f63cc <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x104>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X2], #8	1	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X27]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4f6438 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x170>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	IJMatrix_parcsr.c:3240-3500
Module	exec

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 34.50 to 2.50 cycles (13.80x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 448 bytes. The binary function is storing 464 bytes.

General properties

nb instructions	202
loop length	808
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

25.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	14.50	14.50	20.75	20.75	20.75	20.75	0.00	0.00	0.00	0.00	34.50	34.17	34.33	25.50	25.50
cycles	14.50	14.50	20.75	20.75	20.75	20.75	0.00	0.00	0.00	0.00	34.50	34.17	34.33	25.50	25.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	25.25
Overall L1	34.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 34.50 cycles. At this rate:

13% of peak load performance is reached (12.99 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
28% of peak store performance is reached (13.45 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4f62c8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #688]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X26, X1, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X15, X28, [X0, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X2, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X0, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [X0, #56]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X15, X1, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X5, [X0, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X2, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X6, [X0, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X3, [SP, #128]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X7, [X0, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X5, [SP, #168]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [SP, #208]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X6, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X0, [SP, #328]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X25, [X0, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X7, [SP, #248]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X0, #88]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X22, X20, [X0, #192]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X9, [X0, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #200]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X0, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X0, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X9, [SP, #240]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X24, [X0, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #192]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X0, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X11, [SP, #232]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [X0, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X0, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X12, [SP, #296]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X0, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X13, [SP, #224]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X0, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X0, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X14, [SP, #288]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X0, #176]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X16, [SP, #120]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X19, [X0, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X21, X0, [X0, #208]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X17, [SP, #152]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X18, [SP, #160]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X0, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X19, [SP, #184]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X21, [SP, #320]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 519560 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR X27, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 519580 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SDIV X1, X26, X27	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X15, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MSUB X2, X1, X27, X26	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4f72a0 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xfd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MADD X26, X1, X0, X0	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD X4, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X5, X4, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X5, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X19, X21, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [X22, X21,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X27, X22, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X26, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4f64f8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x230>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X7, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X2, X7, X26,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X8, X7, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X9, X8, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X10, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X11, X10, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X12, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ANDS X13, X12, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4f6488 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4f6474 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4f6468 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X13, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4f645c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x194>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X13, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4f6450 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X13, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4f6444 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x17c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X13, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 4f73a8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x10e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [X2], #8	1	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X0, [X27]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X2], #8	1	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X0, [X27]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X17, [X2], #8	1	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X0, [X27]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X2], #8	1	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X0, [X27]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X1, [X2], #8	1	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X0, [X27]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X30, [X2], #8	1	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X0, [X27]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X8, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4f64f8 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x230>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X15, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f590 <@plt_start@+0x3a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X15, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X21, 4f728c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0xfc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4f6648 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x380>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X0, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X9, X22, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X1, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X3, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X16, [X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X4, X3, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X5, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ANDS X6, X5, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4f65c4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x2fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4f65b0 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x2e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4f65a4 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x2dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4f6598 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4f658c <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x2c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4f6580 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x2b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4f6574 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x2ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X22, [X22, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X16, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X16, [X1, #8]!	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X7, [X1, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X16, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X16, [X1, #8]!	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X1, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X16, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X16, [X1, #8]!	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X11, [X1, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X16, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X16, [X1, #8]!	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X1, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X16, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X16, [X1, #8]!	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [X1, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X16, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X16, [X1, #8]!	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X1, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X16, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X16, [X1, #8]!	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X9, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4f6648 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x380>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X15, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f590 <@plt_start@+0x3a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X27, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X26, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4f6950 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x688>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X30, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X5, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVN X22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X28, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [SP, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X4, X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X8, [SP, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X0, X4, #1, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X2, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X9, [SP, #208]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X10, X25, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X6, X1, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X25, X25, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X7, X6, X0,LSL #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X10, [SP, #120]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X25, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X7, [SP, #176]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X15, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f590 <@plt_start@+0x3a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDUR X21, [X27, #504]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4f6654 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x38c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MADD X30, X0, X1, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD X3, X1, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X26, X2, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X5, X3, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X5, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4f63cc <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x104>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X2], #8	1	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X27]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4f6438 <hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1+0x170>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼hypre_IJMatrixSetValuesOMPParCSR._omp_fn.1–	3.61	1.37
○Loop 3411 - IJMatrix_parcsr.c:3274-3275 - exec	0.01	0
▼Loop 3408 - IJMatrix_parcsr.c:3240-3500 - exec–	0	0
▼Loop 3404 - IJMatrix_parcsr.c:3291-3500 - exec–	3.54	1.17
▼Loop 3403 - IJMatrix_parcsr.c:3291-3500 - exec–	0.02	0.01
▼Loop 3406 - IJMatrix_parcsr.c:3383-3454 - exec–	0.03	0.01
○Loop 3407 - IJMatrix_parcsr.c:3388-3390 - exec	0	0
▼Loop 3396 - IJMatrix_parcsr.c:3291-3500 - exec–	0.01	0.01
○Loop 3401 - IJMatrix_parcsr.c:3359-3362 - exec	0	0
▼Loop 3397 - IJMatrix_parcsr.c:3470-3500 - exec–	0	0
▼Loop 3399 - IJMatrix_parcsr.c:3475-3484 - exec–	0	0
○Loop 3398 - IJMatrix_parcsr.c:3478-3484 - exec	0	0
▼Loop 3400 - IJMatrix_parcsr.c:3316-3341 - exec–	0	0
○Loop 3402 - IJMatrix_parcsr.c:3318-3320 - exec	0	0
○Loop 3409 - IJMatrix_parcsr.c:3422-3424 - exec	0	0
○Loop 3405 - IJMatrix_parcsr.c:3457-3458 - exec	0	0
○Loop 3410 - IJMatrix_parcsr.c:3282-3283 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code