OV - exec - Function hypre_IJMatrixAssembleParCSR._omp

	Function: hypre_IJMatrixAssembleParCSR._omp_fn.1	Module: exec	Source: IJMatrix_parcsr.c:2798-2812	Coverage: 0.35%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 2798 - 2812

--------------------------------------------------------------------------------

2798: #pragma omp parallel for private (i,j,j0,temp)

2799: #endif

2800:          for (i=0; i < num_rows; i++)

2801:          {

2802:    	    j0 = diag_i[i];

2803:    	    for (j=j0; j < diag_i[i+1]; j++)

2804:    	    {

2805:    	       diag_j[j] -= col_0;

2806:    	       if (diag_j[j] == i)

2807:    	       {

2808:    	          temp = diag_data[j0];

2809:    	          diag_data[j0] = diag_data[j];

2810:    	          diag_data[j] = temp;

2811:    	          diag_j[j] = diag_j[j0];

2812:    	          diag_j[j0] = i;

0x4f4ce4 STP	X29, X30, [SP, #976]!

0x4f4ce8 ADD	X29, SP, #0

0x4f4cec STR	X21, [SP, #32]

0x4f4cf0 LDR	X21, [X0, #24]

0x4f4cf4 STP	X19, X20, [SP, #16]

0x4f4cf8 ORR	X20, XZR, X0

0x4f4cfc BL	40f6a0

0x4f4d00 SBFM	X19, X0, #0, #31

0x4f4d04 BL	40f540

0x4f4d08 SDIV	X9, X21, X19

0x4f4d0c SBFM	X2, X0, #0, #31

0x4f4d10 MSUB	X1, X9, X19, X21

0x4f4d14 CMP	X2, X1

0x4f4d18 B.LT	4f4ddc

0x4f4d1c MADD	X30, X9, X2, X1

0x4f4d20 ADD	X11, X9, X30

0x4f4d24 CMP	X30, X11

0x4f4d28 B.GE	4f4d90

0x4f4d2c LDP	X10, X3, [X20]

0x4f4d30 LDR	X7, [X20, #16]

0x4f4d34 ADD	X5, X10, #8

0x4f4d38 LDR	X6, [X20, #32]

0x4f4d3c HINT	#0

      (3376) 0x4f4d40 LDR	X0, [X10, X30,LSL #3]

      (3376) 0x4f4d44 LDR	X12, [X5, X30,LSL #3]

      (3376) 0x4f4d48 UBFM	X4, X0, #61, #60

      (3376) 0x4f4d4c ADD	X8, X7, X4

      (3376) 0x4f4d50 ADD	X13, X3, X4

      (3376) 0x4f4d54 CMP	X0, X12

      (3376) 0x4f4d58 B.GE	4f4d84

    (3375) 0x4f4d5c HINT	#0

    (3375) 0x4f4d60 LDR	X14, [X3, X0,LSL #3]

    (3375) 0x4f4d64 SUB	X15, X14, X6

    (3375) 0x4f4d68 STR	X15, [X3, X0,LSL #3]

    (3375) 0x4f4d6c CMP	X30, X15

    (3375) 0x4f4d70 B.EQ	4f4da0

    (3375) 0x4f4d74 LDR	X16, [X5, X30,LSL #3]

    (3375) 0x4f4d78 ADD	X0, X0, #1

    (3375) 0x4f4d7c CMP	X16, X0

    (3375) 0x4f4d80 B.GT	4f4d60

      (3376) 0x4f4d84 ADD	X30, X30, #1

      (3376) 0x4f4d88 CMP	X11, X30

      (3376) 0x4f4d8c B.NE	4f4d40

(3377) 0x4f4d90 LDP	X19, X20, [SP, #16]

(3377) 0x4f4d94 LDR	X21, [SP, #32]

(3377) 0x4f4d98 LDP	X29, X30, [SP], #48

(3377) 0x4f4d9c RET

  (3374) 0x4f4da0 LDR	D1, [X7, X0,LSL #3]

  (3374) 0x4f4da4 LDR	D0, [X8]

  (3374) 0x4f4da8 LDR	X17, [X13]

  (3374) 0x4f4dac STR	D1, [X8]

  (3374) 0x4f4db0 STR	D0, [X7, X0,LSL #3]

  (3374) 0x4f4db4 STR	X17, [X3, X0,LSL #3]

  (3374) 0x4f4db8 ADD	X0, X0, #1

  (3374) 0x4f4dbc STR	X30, [X13]

  (3374) 0x4f4dc0 LDR	X18, [X5, X30,LSL #3]

  (3374) 0x4f4dc4 CMP	X18, X0

  (3374) 0x4f4dc8 B.GT	4f4d60

  (3374) 0x4f4dcc ADD	X30, X30, #1

  (3374) 0x4f4dd0 CMP	X11, X30

  (3374) 0x4f4dd4 B.NE	4f4d40

(3377) 0x4f4dd8 B	4f4d90

0x4f4ddc ADD	X9, X9, #1

0x4f4de0 MOVZ	X1, #0

0x4f4de4 B	4f4d1c

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	IJMatrix_parcsr.c:2798-2812
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:2798-2812.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 20.00 to 10.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	26
loop length	104
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	2.50	2.17	2.33	1.50	1.50
cycles	2.50	2.50	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	2.50	2.17	2.33	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	3.13
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

2% of peak load performance is reached (2.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4f4ce4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f6a0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f540 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SDIV X9, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
SBFM X2, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MSUB X1, X9, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4f4ddc <hypre_IJMatrixAssembleParCSR._omp_fn.1+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X30, X9, X2, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X11, X9, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X30, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4f4d90 <hypre_IJMatrixAssembleParCSR._omp_fn.1+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X10, X3, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X7, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X6, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
HINT #0
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4f4d1c <hypre_IJMatrixAssembleParCSR._omp_fn.1+0x38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	IJMatrix_parcsr.c:2798-2812
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:2798-2812.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 40 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	26
loop length	104
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	2.50	2.17	2.33	1.50	1.50
cycles	2.50	2.50	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	2.50	2.17	2.33	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	3.13
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

2% of peak load performance is reached (2.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4f4ce4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f6a0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f540 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SDIV X9, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
SBFM X2, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MSUB X1, X9, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4f4ddc <hypre_IJMatrixAssembleParCSR._omp_fn.1+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X30, X9, X2, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X11, X9, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X30, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4f4d90 <hypre_IJMatrixAssembleParCSR._omp_fn.1+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X10, X3, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X7, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X6, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
HINT #0
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4f4d1c <hypre_IJMatrixAssembleParCSR._omp_fn.1+0x38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼hypre_IJMatrixAssembleParCSR._omp_fn.1–	0.35	0.13
▼Loop 3377 - IJMatrix_parcsr.c:2798-2812 - exec–	0	0
▼Loop 3374 - IJMatrix_parcsr.c:2802-2812 - exec–	0.09	0.03
▼Loop 3375 - IJMatrix_parcsr.c:2802-2811 - exec–	0.25	0.08
○Loop 3376 - IJMatrix_parcsr.c:2802-2811 - exec	0	0.01

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code