OV - exec - Function hypre_IJMatrixInitializeParCSR._omp

	Function: hypre_IJMatrixInitializeParCSR._omp_fn.0	Module: exec	Source: IJMatrix_parcsr.c:302-307	Coverage: 0.13%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 302 - 307

--------------------------------------------------------------------------------

302: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

303: #endif

304:          for (i=0; i < local_num_rows; i++)

305:          {

306: 	    indx_diag[i] = diag_i[i];

307: 	    indx_offd[i] = offd_i[i];

0x4f4320 STP	X29, X30, [SP, #976]!

0x4f4324 ADD	X29, SP, #0

0x4f4328 STR	X21, [SP, #32]

0x4f432c LDR	X21, [X0]

0x4f4330 STP	X19, X20, [SP, #16]

0x4f4334 ORR	X20, XZR, X0

0x4f4338 BL	40f6a0

0x4f433c SBFM	X19, X0, #0, #31

0x4f4340 BL	40f540

0x4f4344 SDIV	X3, X21, X19

0x4f4348 SBFM	X1, X0, #0, #31

0x4f434c MSUB	X2, X3, X19, X21

0x4f4350 CMP	X1, X2

0x4f4354 B.LT	4f44f8

(3368) 0x4f4358 MADD	X1, X3, X1, X2

(3368) 0x4f435c ADD	X5, X3, X1

(3368) 0x4f4360 CMP	X1, X5

(3368) 0x4f4364 B.GE	4f44e8

(3368) 0x4f4368 SUB	X4, X5, X1

(3368) 0x4f436c LDP	X6, X14, [X20, #8]

(3368) 0x4f4370 ANDS	X7, X4, #4224

(3368) 0x4f4374 LDP	X15, X0, [X20, #24]

(3368) 0x4f4378 B.EQ	4f4440

(3368) 0x4f437c CMP	X7, #1

(3368) 0x4f4380 B.EQ	4f4424

(3368) 0x4f4384 CMP	X7, #2

(3368) 0x4f4388 B.EQ	4f4410

(3368) 0x4f438c CMP	X7, #3

(3368) 0x4f4390 B.EQ	4f43fc

(3368) 0x4f4394 CMP	X7, #4

(3368) 0x4f4398 B.EQ	4f43e8

(3368) 0x4f439c CMP	X7, #5

(3368) 0x4f43a0 B.EQ	4f43d4

(3368) 0x4f43a4 CMP	X7, #6

(3368) 0x4f43a8 B.EQ	4f43c0

(3368) 0x4f43ac LDR	X8, [X15, X1,LSL #3]

(3368) 0x4f43b0 STR	X8, [X6, X1,LSL #3]

(3368) 0x4f43b4 LDR	X9, [X0, X1,LSL #3]

(3368) 0x4f43b8 STR	X9, [X14, X1,LSL #3]

(3368) 0x4f43bc ADD	X1, X1, #1

(3368) 0x4f43c0 LDR	X10, [X15, X1,LSL #3]

(3368) 0x4f43c4 STR	X10, [X6, X1,LSL #3]

(3368) 0x4f43c8 LDR	X11, [X0, X1,LSL #3]

(3368) 0x4f43cc STR	X11, [X14, X1,LSL #3]

(3368) 0x4f43d0 ADD	X1, X1, #1

(3368) 0x4f43d4 LDR	X12, [X15, X1,LSL #3]

(3368) 0x4f43d8 STR	X12, [X6, X1,LSL #3]

(3368) 0x4f43dc LDR	X13, [X0, X1,LSL #3]

(3368) 0x4f43e0 STR	X13, [X14, X1,LSL #3]

(3368) 0x4f43e4 ADD	X1, X1, #1

(3368) 0x4f43e8 LDR	X16, [X15, X1,LSL #3]

(3368) 0x4f43ec STR	X16, [X6, X1,LSL #3]

(3368) 0x4f43f0 LDR	X17, [X0, X1,LSL #3]

(3368) 0x4f43f4 STR	X17, [X14, X1,LSL #3]

(3368) 0x4f43f8 ADD	X1, X1, #1

(3368) 0x4f43fc LDR	X18, [X15, X1,LSL #3]

(3368) 0x4f4400 STR	X18, [X6, X1,LSL #3]

(3368) 0x4f4404 LDR	X30, [X0, X1,LSL #3]

(3368) 0x4f4408 STR	X30, [X14, X1,LSL #3]

(3368) 0x4f440c ADD	X1, X1, #1

(3368) 0x4f4410 LDR	X20, [X15, X1,LSL #3]

(3368) 0x4f4414 STR	X20, [X6, X1,LSL #3]

(3368) 0x4f4418 LDR	X21, [X0, X1,LSL #3]

(3368) 0x4f441c STR	X21, [X14, X1,LSL #3]

(3368) 0x4f4420 ADD	X1, X1, #1

(3368) 0x4f4424 LDR	X19, [X15, X1,LSL #3]

(3368) 0x4f4428 STR	X19, [X6, X1,LSL #3]

(3368) 0x4f442c LDR	X3, [X0, X1,LSL #3]

(3368) 0x4f4430 STR	X3, [X14, X1,LSL #3]

(3368) 0x4f4434 ADD	X1, X1, #1

(3368) 0x4f4438 CMP	X5, X1

(3368) 0x4f443c B.EQ	4f44e8

  (3369) 0x4f4440 LDR	X2, [X15, X1,LSL #3]

  (3369) 0x4f4444 ADD	X4, X1, #1

  (3369) 0x4f4448 ADD	X12, X1, #2

  (3369) 0x4f444c ADD	X11, X1, #3

  (3369) 0x4f4450 ADD	X10, X1, #4

  (3369) 0x4f4454 ADD	X9, X1, #5

  (3369) 0x4f4458 ADD	X8, X1, #6

  (3369) 0x4f445c ADD	X7, X1, #7

  (3369) 0x4f4460 STR	X2, [X6, X1,LSL #3]

  (3369) 0x4f4464 LDR	X13, [X0, X1,LSL #3]

  (3369) 0x4f4468 STR	X13, [X14, X1,LSL #3]

  (3369) 0x4f446c ADD	X1, X1, #8

  (3369) 0x4f4470 LDR	X16, [X15, X4,LSL #3]

  (3369) 0x4f4474 STR	X16, [X6, X4,LSL #3]

  (3369) 0x4f4478 LDR	X17, [X0, X4,LSL #3]

  (3369) 0x4f447c STR	X17, [X14, X4,LSL #3]

  (3369) 0x4f4480 LDR	X18, [X15, X12,LSL #3]

  (3369) 0x4f4484 STR	X18, [X6, X12,LSL #3]

  (3369) 0x4f4488 LDR	X30, [X0, X12,LSL #3]

  (3369) 0x4f448c STR	X30, [X14, X12,LSL #3]

  (3369) 0x4f4490 LDR	X20, [X15, X11,LSL #3]

  (3369) 0x4f4494 STR	X20, [X6, X11,LSL #3]

  (3369) 0x4f4498 LDR	X21, [X0, X11,LSL #3]

  (3369) 0x4f449c STR	X21, [X14, X11,LSL #3]

  (3369) 0x4f44a0 LDR	X19, [X15, X10,LSL #3]

  (3369) 0x4f44a4 STR	X19, [X6, X10,LSL #3]

  (3369) 0x4f44a8 LDR	X3, [X0, X10,LSL #3]

  (3369) 0x4f44ac STR	X3, [X14, X10,LSL #3]

  (3369) 0x4f44b0 LDR	X2, [X15, X9,LSL #3]

  (3369) 0x4f44b4 STR	X2, [X6, X9,LSL #3]

  (3369) 0x4f44b8 LDR	X4, [X0, X9,LSL #3]

  (3369) 0x4f44bc STR	X4, [X14, X9,LSL #3]

  (3369) 0x4f44c0 LDR	X11, [X15, X8,LSL #3]

  (3369) 0x4f44c4 STR	X11, [X6, X8,LSL #3]

  (3369) 0x4f44c8 LDR	X12, [X0, X8,LSL #3]

  (3369) 0x4f44cc STR	X12, [X14, X8,LSL #3]

  (3369) 0x4f44d0 LDR	X10, [X15, X7,LSL #3]

  (3369) 0x4f44d4 STR	X10, [X6, X7,LSL #3]

  (3369) 0x4f44d8 LDR	X9, [X0, X7,LSL #3]

  (3369) 0x4f44dc STR	X9, [X14, X7,LSL #3]

  (3369) 0x4f44e0 CMP	X5, X1

  (3369) 0x4f44e4 B.NE	4f4440

(3368) 0x4f44e8 LDP	X19, X20, [SP, #16]

(3368) 0x4f44ec LDR	X21, [SP, #32]

(3368) 0x4f44f0 LDP	X29, X30, [SP], #48

(3368) 0x4f44f4 RET

(3368) 0x4f44f8 ADD	X3, X3, #1

(3368) 0x4f44fc MOVZ	X2, #0

(3368) 0x4f4500 B	4f4358

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	IJMatrix_parcsr.c:302-307
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:302-307.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 20.00 to 10.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4f4320

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X21, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40f6a0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40f540 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SDIV X3, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MSUB X2, X3, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP X1, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 4f44f8 <hypre_IJMatrixInitializeParCSR._omp_fn.0+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	IJMatrix_parcsr.c:302-307
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:302-307.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4f4320

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X21, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40f6a0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40f540 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SDIV X3, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MSUB X2, X3, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP X1, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 4f44f8 <hypre_IJMatrixInitializeParCSR._omp_fn.0+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼hypre_IJMatrixInitializeParCSR._omp_fn.0–	0.13	0.05
▼Loop 3368 - IJMatrix_parcsr.c:302-307 - exec–	0	0
○Loop 3369 - IJMatrix_parcsr.c:306-307 - exec	0.13	0.04

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code