OV - exec - Function hypre_ParMatmul._omp

	Function: hypre_ParMatmul._omp_fn.3	Module: exec	Source: par_csr_matop.c:829-995 [...]	Coverage: 0.99%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 829 - 995

--------------------------------------------------------------------------------

829: #pragma omp parallel

830: #endif

831:    {

832:     HYPRE_Int *B_marker = NULL;

[...]

840:     ii = hypre_GetThreadNum();

841:     num_threads = hypre_NumActiveThreads();

842:     size = num_rows_diag_A/num_threads;

843:     rest = num_rows_diag_A - size*num_threads;

844:     if (ii < rest)

845:     {

846:        ns = ii*size+ii;

847:        ne = (ii+1)*size+ii+1;

848:     }

849:     else

850:     {

851:        ns = ii*size+rest;

852:        ne = (ii+1)*size+rest;

853:     }

854:     jj_count_diag = C_diag_i[ns];

855:     jj_count_offd = C_offd_i[ns];

856:     if (num_cols_diag_B || num_cols_offd_C)

857:     B_marker = hypre_CTAlloc(HYPRE_Int, num_cols_diag_B+num_cols_offd_C);

858:     for (i1 = 0; i1 < num_cols_diag_B+num_cols_offd_C; i1++)

859:       B_marker[i1] = -1;

[...]

865:     for (i1 = ns; i1 < ne; i1++)

[...]

874:       if ( allsquare )

875:       {

876:          B_marker[i1] = jj_count_diag;

877:          C_diag_data[jj_count_diag] = zero;

878:          C_diag_j[jj_count_diag] = i1;

879:          jj_count_diag++;

[...]

886:       if (num_cols_offd_A)

887:       {

888:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

889:          {

890:             i2 = A_offd_j[jj2];

891:             a_entry = A_offd_data[jj2];

[...]

897:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

898:             {

899:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

907:                if (B_marker[i3] < jj_row_begin_offd)

908:                {

909:                   B_marker[i3] = jj_count_offd;

910:                   C_offd_data[jj_count_offd] = a_entry*B_ext_offd_data[jj3];

911:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

912:                   jj_count_offd++;

913:                }

914:                else

915:                   C_offd_data[B_marker[i3]] += a_entry*B_ext_offd_data[jj3];

916:             }

917:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

918:             {

919:                i3 = B_ext_diag_j[jj3];

920:                if (B_marker[i3] < jj_row_begin_diag)

921:                {

922:                   B_marker[i3] = jj_count_diag;

923:                   C_diag_data[jj_count_diag] = a_entry*B_ext_diag_data[jj3];

924:                   C_diag_j[jj_count_diag] = i3;

925:                   jj_count_diag++;

926:                }

927:                else

928:                   C_diag_data[B_marker[i3]] += a_entry*B_ext_diag_data[jj3];

[...]

937:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

938:       {

939:          i2 = A_diag_j[jj2];

940:          a_entry = A_diag_data[jj2];

[...]

946:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

947:          {

948:             i3 = B_diag_j[jj3];

[...]

956:             if (B_marker[i3] < jj_row_begin_diag)

957:             {

958:                B_marker[i3] = jj_count_diag;

959:                C_diag_data[jj_count_diag] = a_entry*B_diag_data[jj3];

960:                C_diag_j[jj_count_diag] = i3;

961:                jj_count_diag++;

962:             }

963:             else

964:             {

965:                C_diag_data[B_marker[i3]] += a_entry*B_diag_data[jj3];

966:             }

967:          }

968:          if (num_cols_offd_B)

969:          {

970:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

971:             {

972:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

980:                if (B_marker[i3] < jj_row_begin_offd)

981:                {

982:                   B_marker[i3] = jj_count_offd;

983:                   C_offd_data[jj_count_offd] = a_entry*B_offd_data[jj3];

984:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

985:                   jj_count_offd++;

986:                }

987:                else

988:                {

989:                   C_offd_data[B_marker[i3]] += a_entry*B_offd_data[jj3];

[...]

995:     hypre_TFree(B_marker);

0x4db010 STP	X29, X30, [SP, #720]!

0x4db014 ORR	X2, XZR, X0

0x4db018 ADD	X29, SP, #0

0x4db01c STP	X19, X20, [SP, #16]

0x4db020 LDR	X1, [X2, #8]

0x4db024 STP	X21, X22, [SP, #32]

0x4db028 LDR	X3, [X2, #16]

0x4db02c STP	X23, X24, [SP, #48]

0x4db030 LDR	X4, [X2, #24]

0x4db034 STP	X25, X26, [SP, #64]

0x4db038 LDR	X5, [X2, #32]

0x4db03c STP	X27, X28, [SP, #80]

0x4db040 LDR	X6, [X2, #40]

0x4db044 STR	X5, [SP, #128]

0x4db048 LDR	X20, [X0, #48]

0x4db04c STR	X3, [SP, #176]

0x4db050 LDR	X0, [X0]

0x4db054 STR	X1, [SP, #192]

0x4db058 LDR	X7, [X2, #56]

0x4db05c STR	X6, [SP, #248]

0x4db060 STR	X4, [SP, #256]

0x4db064 STR	X0, [SP, #184]

0x4db068 LDP	X22, X27, [X2, #64]

0x4db06c STR	X7, [SP, #152]

0x4db070 LDR	X21, [X2, #80]

0x4db074 STR	D8, [SP, #96]

0x4db078 LDP	X14, X15, [X2, #88]

0x4db07c LDP	X13, X26, [X2, #104]

0x4db080 LDP	X12, X19, [X2, #128]

0x4db084 LDP	X9, X8, [X2, #208]

0x4db088 STR	X2, [SP, #120]

0x4db08c LDR	X16, [X2, #120]

0x4db090 STR	X8, [SP, #136]

0x4db094 LDR	X11, [X2, #176]

0x4db098 STR	X15, [SP, #168]

0x4db09c LDR	X10, [X2, #192]

0x4db0a0 STR	X16, [SP, #160]

0x4db0a4 LDR	X17, [X2, #200]

0x4db0a8 STP	X11, X12, [SP, #216]

0x4db0ac LDR	X18, [X2, #224]

0x4db0b0 STP	X9, X10, [SP, #200]

0x4db0b4 LDR	X25, [X2, #240]

0x4db0b8 STR	X18, [SP, #232]

0x4db0bc LDR	D8, [X2, #248]

0x4db0c0 STR	X17, [SP, #240]

0x4db0c4 STP	X13, X14, [SP, #264]

0x4db0c8 STR	X25, [SP, #144]

0x4db0cc LDP	X24, X23, [X2, #152]

0x4db0d0 LDR	X28, [X2, #232]

0x4db0d4 BL	519580

0x4db0d8 ORR	X25, XZR, X0

0x4db0dc BL	519560

0x4db0e0 ORR	X2, XZR, X0

0x4db0e4 SDIV	X0, X20, X0

0x4db0e8 LDR	X7, [SP, #120]

0x4db0ec LDP	X9, X10, [SP, #200]

0x4db0f0 LDP	X11, X12, [SP, #216]

0x4db0f4 LDP	X13, X14, [SP, #264]

0x4db0f8 MSUB	X20, X0, X2, X20

0x4db0fc LDR	X15, [SP, #136]

0x4db100 CMP	X20, X25

0x4db104 B.LE	4db500

0x4db108 MADD	X5, X25, X0, XZR

0x4db10c ADD	X6, X0, X5

0x4db110 ADD	X8, X25, X5

0x4db114 ADD	X16, X6, X25

0x4db118 ORR	X18, XZR, X8

0x4db11c ADD	X17, X16, #1

0x4db120 STR	X8, [SP, #120]

0x4db124 STR	X17, [SP, #136]

0x4db128 LDR	X0, [X7, #184]

0x4db12c UBFM	X3, X18, #61, #60

0x4db130 LDR	X25, [X7, #144]

0x4db134 LDR	X2, [X7, #168]

0x4db138 LDR	X30, [X0]

0x4db13c LDR	X20, [X25]

0x4db140 LDR	X4, [X2]

0x4db144 ORR	X1, X26, X30

0x4db148 LDR	X20, [X20, X18,LSL #3]

0x4db14c LDR	X25, [X4, X18,LSL #3]

0x4db150 CBNZ	X1, 4db494

0x4db154 MOVZ	X0, #0

0x4db158 LDR	X1, [SP, #128]

0x4db15c LDR	X5, [SP, #120]

0x4db160 LDR	X30, [SP, #136]

0x4db164 ADD	X7, X1, X3

0x4db168 LDR	X4, [SP, #192]

0x4db16c STR	X7, [SP, #128]

0x4db170 ADD	X16, X4, X3

0x4db174 CMP	X5, X30

0x4db178 B.GE	4db474

0x4db17c STP	X28, X15, [SP, #264]

0x4db180 STR	X9, [SP, #280]

0x4db184 LDR	X28, [SP, #144]

0x4db188 CBNZ	X28, 4db254

  (2970) 0x4db18c LDR	X9, [SP, #152]

  (2970) 0x4db190 ORR	X1, XZR, X20

  (2970) 0x4db194 ORR	X3, XZR, X25

  (2970) 0x4db198 CBNZ	X9, 4db274

  (2970) 0x4db19c LDP	X15, X30, [X16]

  (2970) 0x4db1a0 CMP	X15, X30

  (2970) 0x4db1a4 B.GE	4db224

  (2970) 0x4db1a8 LDP	X18, X9, [SP, #160]

  (2970) 0x4db1ac LDP	X28, X30, [SP, #176]

    (2975) 0x4db1b0 LDR	X17, [X28, X15,LSL #3]

    (2975) 0x4db1b4 LDR	D17, [X30, X15,LSL #3]

    (2975) 0x4db1b8 UBFM	X8, X17, #61, #60

    (2975) 0x4db1bc LDR	X2, [X27, X17,LSL #3]

    (2975) 0x4db1c0 ADD	X7, X8, #8

    (2975) 0x4db1c4 LDR	X6, [X27, X7]

    (2975) 0x4db1c8 ADD	X8, X27, X7

    (2975) 0x4db1cc CMP	X2, X6

    (2975) 0x4db1d0 B.GE	4db210

    (2975) 0x4db1d4 HINT	#0

    (2975) 0x4db1d8 HINT	#0

    (2975) 0x4db1dc HINT	#0

      (2978) 0x4db1e0 LDR	X4, [X21, X2,LSL #3]

      (2978) 0x4db1e4 LDR	D18, [X22, X2,LSL #3]

      (2978) 0x4db1e8 LDR	X5, [X0, X4,LSL #3]

      (2978) 0x4db1ec FMUL	D19, D17, D18

      (2978) 0x4db1f0 CMP	X5, X20

      (2978) 0x4db1f4 B.LT	4db35c

      (2978) 0x4db1f8 LDR	D20, [X19, X5,LSL #3]

      (2978) 0x4db1fc ADD	X2, X2, #1

      (2978) 0x4db200 FADD	D21, D20, D19

      (2978) 0x4db204 STR	D21, [X19, X5,LSL #3]

      (2978) 0x4db208 CMP	X6, X2

      (2978) 0x4db20c B.GT	4db1e0

    (2975) 0x4db210 CBNZ	X18, 4db380

    (2975) 0x4db214 LDR	X17, [X16, #8]

    (2975) 0x4db218 ADD	X15, X15, #1

    (2975) 0x4db21c CMP	X17, X15

    (2975) 0x4db220 B.GT	4db1b0

  (2970) 0x4db224 LDP	X20, X25, [SP, #120]

  (2970) 0x4db228 ADD	X16, X16, #8

  (2970) 0x4db22c LDR	X28, [SP, #136]

  (2970) 0x4db230 ADD	X18, X20, #1

  (2970) 0x4db234 ADD	X9, X25, #8

  (2970) 0x4db238 STP	X18, X9, [SP, #120]

  (2970) 0x4db23c CMP	X28, X18

  (2970) 0x4db240 B.EQ	4db474

  (2970) 0x4db244 LDR	X28, [SP, #144]

  (2970) 0x4db248 ORR	X25, XZR, X3

  (2970) 0x4db24c ORR	X20, XZR, X1

  (2970) 0x4db250 CBZ	X28, 4db18c

(2974) 0x4db254 LDR	X15, [SP, #120]

(2974) 0x4db258 ADD	X1, X20, #1

(2974) 0x4db25c ORR	X3, XZR, X25

(2974) 0x4db260 LDR	X9, [SP, #152]

(2974) 0x4db264 STR	X20, [X0, X15,LSL #3]

(2974) 0x4db268 STR	D8, [X19, X20,LSL #3]

(2974) 0x4db26c STR	X15, [X24, X20,LSL #3]

(2974) 0x4db270 CBZ	X9, 4db19c

  (2970) 0x4db274 LDR	X30, [SP, #128]

  (2970) 0x4db278 LDP	X17, X6, [X30]

  (2970) 0x4db27c CMP	X17, X6

  (2970) 0x4db280 B.GE	4db19c

  (2970) 0x4db284 STP	X14, X21, [SP, #208]

  (2970) 0x4db288 STR	X27, [SP, #224]

  (2970) 0x4db28c LDP	X15, X18, [SP, #232]

  (2970) 0x4db290 LDP	X21, X27, [SP, #248]

  (2970) 0x4db294 LDP	X28, X8, [SP, #264]

  (2970) 0x4db298 STP	X12, X13, [SP, #192]

  (2970) 0x4db29c LDR	X9, [SP, #280]

    (2971) 0x4db2a0 LDR	X14, [X21, X17,LSL #3]

    (2971) 0x4db2a4 LDR	D1, [X27, X17,LSL #3]

    (2971) 0x4db2a8 UBFM	X12, X14, #61, #60

    (2971) 0x4db2ac LDR	X2, [X15, X14,LSL #3]

    (2971) 0x4db2b0 ADD	X12, X12, #8

    (2971) 0x4db2b4 LDR	X7, [X15, X12]

    (2971) 0x4db2b8 ADD	X13, X15, X12

    (2971) 0x4db2bc CMP	X2, X7

    (2971) 0x4db2c0 B.GE	4db2f8

      (2973) 0x4db2c4 LDR	X5, [X28, X2,LSL #3]

      (2973) 0x4db2c8 LDR	D0, [X8, X2,LSL #3]

      (2973) 0x4db2cc ADD	X6, X26, X5

      (2973) 0x4db2d0 LDR	X4, [X0, X6,LSL #3]

      (2973) 0x4db2d4 FMUL	D3, D1, D0

      (2973) 0x4db2d8 CMP	X4, X25

      (2973) 0x4db2dc B.LT	4db450

      (2973) 0x4db2e0 LDR	D2, [X23, X4,LSL #3]

      (2973) 0x4db2e4 ADD	X2, X2, #1

      (2973) 0x4db2e8 FADD	D4, D2, D3

      (2973) 0x4db2ec STR	D4, [X23, X4,LSL #3]

      (2973) 0x4db2f0 CMP	X7, X2

      (2973) 0x4db2f4 B.GT	4db2c4

    (2971) 0x4db2f8 LDR	X5, [X18, X14,LSL #3]

    (2971) 0x4db2fc ADD	X14, X18, X12

    (2971) 0x4db300 LDR	X6, [X18, X12]

    (2971) 0x4db304 CMP	X5, X6

    (2971) 0x4db308 B.GE	4db33c

      (2972) 0x4db30c LDR	X12, [X9, X5,LSL #3]

      (2972) 0x4db310 LDR	D5, [X10, X5,LSL #3]

      (2972) 0x4db314 LDR	X13, [X0, X12,LSL #3]

      (2972) 0x4db318 FMUL	D6, D1, D5

      (2972) 0x4db31c CMP	X13, X20

      (2972) 0x4db320 B.LT	4db41c

      (2972) 0x4db324 LDR	D7, [X19, X13,LSL #3]

      (2972) 0x4db328 ADD	X5, X5, #1

      (2972) 0x4db32c FADD	D16, D7, D6

      (2972) 0x4db330 STR	D16, [X19, X13,LSL #3]

      (2972) 0x4db334 CMP	X6, X5

      (2972) 0x4db338 B.GT	4db30c

    (2971) 0x4db33c LDR	X4, [X30, #8]

    (2971) 0x4db340 ADD	X17, X17, #1

    (2971) 0x4db344 CMP	X4, X17

    (2971) 0x4db348 B.GT	4db2a0

  (2970) 0x4db34c LDP	X12, X13, [SP, #192]

  (2970) 0x4db350 LDP	X14, X21, [SP, #208]

  (2970) 0x4db354 LDR	X27, [SP, #224]

  (2970) 0x4db358 B	4db19c

      (2978) 0x4db35c STR	X1, [X0, X4,LSL #3]

      (2978) 0x4db360 ADD	X2, X2, #1

      (2978) 0x4db364 STR	D19, [X19, X1,LSL #3]

      (2978) 0x4db368 STR	X4, [X24, X1,LSL #3]

      (2978) 0x4db36c ADD	X1, X1, #1

      (2978) 0x4db370 LDR	X6, [X8]

      (2978) 0x4db374 CMP	X2, X6

      (2978) 0x4db378 B.LT	4db1e0

    (2975) 0x4db37c CBZ	X18, 4db214

    (2975) 0x4db380 LDR	X2, [X9, X17,LSL #3]

    (2975) 0x4db384 ADD	X17, X9, X7

    (2975) 0x4db388 LDR	X7, [X9, X7]

    (2975) 0x4db38c CMP	X2, X7

    (2975) 0x4db390 B.GE	4db214

    (2975) 0x4db394 HINT	#0

    (2975) 0x4db398 HINT	#0

    (2975) 0x4db39c HINT	#0

      (2976) 0x4db3a0 LDR	X8, [X13, X2,LSL #3]

      (2976) 0x4db3a4 LDR	D22, [X14, X2,LSL #3]

      (2976) 0x4db3a8 LDR	X5, [X12, X8,LSL #3]

      (2976) 0x4db3ac FMUL	D23, D17, D22

      (2976) 0x4db3b0 ADD	X6, X26, X5

      (2976) 0x4db3b4 LDR	X4, [X0, X6,LSL #3]

      (2976) 0x4db3b8 CMP	X4, X25

      (2976) 0x4db3bc B.LT	4db3f8

      (2977) 0x4db3c0 LDR	D24, [X23, X4,LSL #3]

      (2977) 0x4db3c4 ADD	X2, X2, #1

      (2977) 0x4db3c8 FADD	D25, D24, D23

      (2977) 0x4db3cc STR	D25, [X23, X4,LSL #3]

      (2977) 0x4db3d0 CMP	X7, X2

      (2977) 0x4db3d4 B.LE	4db214

      (2977) 0x4db3d8 LDR	X8, [X13, X2,LSL #3]

      (2977) 0x4db3dc LDR	D22, [X14, X2,LSL #3]

      (2977) 0x4db3e0 LDR	X5, [X12, X8,LSL #3]

      (2977) 0x4db3e4 FMUL	D23, D17, D22

      (2977) 0x4db3e8 ADD	X6, X26, X5

      (2977) 0x4db3ec LDR	X4, [X0, X6,LSL #3]

      (2977) 0x4db3f0 CMP	X4, X25

      (2977) 0x4db3f4 B.GE	4db3c0

      (2976) 0x4db3f8 STR	X3, [X0, X6,LSL #3]

      (2976) 0x4db3fc ADD	X2, X2, #1

      (2976) 0x4db400 STR	D23, [X23, X3,LSL #3]

      (2976) 0x4db404 STR	X5, [X11, X3,LSL #3]

      (2976) 0x4db408 ADD	X3, X3, #1

      (2976) 0x4db40c LDR	X7, [X17]

      (2976) 0x4db410 CMP	X2, X7

      (2976) 0x4db414 B.LT	4db3a0

    (2975) 0x4db418 B	4db214

      (2972) 0x4db41c STR	X1, [X0, X12,LSL #3]

      (2972) 0x4db420 ADD	X5, X5, #1

      (2972) 0x4db424 STR	D6, [X19, X1,LSL #3]

      (2972) 0x4db428 STR	X12, [X24, X1,LSL #3]

      (2972) 0x4db42c ADD	X1, X1, #1

      (2972) 0x4db430 LDR	X6, [X14]

      (2972) 0x4db434 CMP	X5, X6

      (2972) 0x4db438 B.LT	4db30c

    (2971) 0x4db43c LDR	X4, [X30, #8]

    (2971) 0x4db440 ADD	X17, X17, #1

    (2971) 0x4db444 CMP	X4, X17

    (2971) 0x4db448 B.GT	4db2a0

  (2970) 0x4db44c B	4db34c

      (2973) 0x4db450 STR	X3, [X0, X6,LSL #3]

      (2973) 0x4db454 ADD	X2, X2, #1

      (2973) 0x4db458 STR	D3, [X23, X3,LSL #3]

      (2973) 0x4db45c STR	X5, [X11, X3,LSL #3]

      (2973) 0x4db460 ADD	X3, X3, #1

      (2973) 0x4db464 LDR	X7, [X13]

      (2973) 0x4db468 CMP	X2, X7

      (2973) 0x4db46c B.LT	4db2c4

    (2971) 0x4db470 B	4db2f8

0x4db474 LDP	X19, X20, [SP, #16]

0x4db478 LDP	X21, X22, [SP, #32]

0x4db47c LDP	X23, X24, [SP, #48]

0x4db480 LDP	X25, X26, [SP, #64]

0x4db484 LDP	X27, X28, [SP, #80]

0x4db488 LDR	D8, [SP, #96]

0x4db48c LDP	X29, X30, [SP], #304

0x4db490 B	516820

0x4db494 ADD	X0, X26, X30

0x4db498 MOVZ	X1, #8

0x4db49c STP	X15, X9, [SP, #200]

0x4db4a0 STP	X10, X11, [SP, #216]

0x4db4a4 STP	X12, X13, [SP, #264]

0x4db4a8 STP	X14, X3, [SP, #280]

0x4db4ac STR	X7, [SP, #296]

0x4db4b0 BL	51674c

0x4db4b4 LDR	X6, [SP, #296]

0x4db4b8 MOVZ	X7, #0

0x4db4bc MOVN	X5, #0

0x4db4c0 LDP	X15, X9, [SP, #200]

0x4db4c4 LDP	X10, X11, [SP, #216]

0x4db4c8 LDP	X12, X13, [SP, #264]

0x4db4cc LDP	X14, X3, [SP, #280]

0x4db4d0 LDR	X8, [X6, #184]

0x4db4d4 LDR	X18, [X8]

0x4db4d8 ADD	X2, X26, X18

0x4db4dc CMP	X2, #0

0x4db4e0 B.LE	4db158

(2979) 0x4db4e4 STR	X5, [X0, X7,LSL #3]

(2979) 0x4db4e8 ADD	X7, X7, #1

(2979) 0x4db4ec LDR	X16, [X8]

(2979) 0x4db4f0 ADD	X17, X26, X16

(2979) 0x4db4f4 CMP	X17, X7

(2979) 0x4db4f8 B.GT	4db4e4

0x4db4fc B	4db158

0x4db500 MADD	X30, X25, X0, XZR

0x4db504 ADD	X1, X0, X30

0x4db508 ADD	X3, X20, X30

0x4db50c ADD	X4, X1, X20

0x4db510 ORR	X18, XZR, X3

0x4db514 STR	X3, [SP, #120]

0x4db518 STR	X4, [SP, #136]

0x4db51c B	4db128

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	par_csr_matop.c:829-995
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:829-832,840-859,865,874-879,886-891,897-899,907-928,937-940,946-948,956-972,980-989,995.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 30.33 to 4.17 cycles (7.28x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 30.33 to 10.00 cycles (3.03x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 30.33 to 1.50 cycles (20.22x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 592 bytes. The binary function is storing 400 bytes.

General properties

nb instructions	132
loop length	528
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

16.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	8.50	8.50	8.50	8.50	0.50	0.50	0.00	0.00	30.33	30.33	30.33	17.50	17.50
cycles	5.50	5.50	8.50	8.50	8.50	8.50	0.50	0.50	0.00	0.00	30.33	30.33	30.33	17.50	17.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	16.50
Overall L1	30.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 30.33 cycles. At this rate:

20% of peak load performance is reached (19.52 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
27% of peak store performance is reached (13.19 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4db010

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #720]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X2, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X1, [X2, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X2, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [X2, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X5, [X2, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X6, [X2, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X5, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X20, [X0, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X3, [SP, #176]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X1, [SP, #192]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X7, [X2, #56]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X6, [SP, #248]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [SP, #256]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X0, [SP, #184]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X22, X27, [X2, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X7, [SP, #152]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X2, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR D8, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
LDP X14, X15, [X2, #88]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X13, X26, [X2, #104]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X12, X19, [X2, #128]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X9, X8, [X2, #208]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X2, [SP, #120]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X2, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X11, [X2, #176]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X15, [SP, #168]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X2, #192]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X16, [SP, #160]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X17, [X2, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X11, X12, [SP, #216]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X2, #224]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X9, X10, [SP, #200]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X25, [X2, #240]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X18, [SP, #232]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR D8, [X2, #248]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR X17, [SP, #240]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X13, X14, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X25, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X24, X23, [X2, #152]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X28, [X2, #232]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 519580 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 519560 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SDIV X0, X20, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	5-20	5-20
LDR X7, [SP, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X9, X10, [SP, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X11, X12, [SP, #216]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X13, X14, [SP, #264]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MSUB X20, X0, X2, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR X15, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X20, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 4db500 <hypre_ParMatmul._omp_fn.3+0x4f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X5, X25, X0, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD X6, X0, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X8, X25, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X16, X6, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X18, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X17, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X17, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X7, #184]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X3, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X25, [X7, #144]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X7, #168]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X20, [X25]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X2]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X1, X26, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X20, [X20, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [X4, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X1, 4db494 <hypre_ParMatmul._omp_fn.3+0x484>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X1, [SP, #128]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [SP, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X7, X1, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X4, [SP, #192]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X7, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X16, X4, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X5, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 4db474 <hypre_ParMatmul._omp_fn.3+0x464>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X28, X15, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X9, [SP, #280]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X28, [SP, #144]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X28, 4db254 <hypre_ParMatmul._omp_fn.3+0x244>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR D8, [SP, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X29, X30, [SP], #304	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 516820 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X26, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STP X15, X9, [SP, #200]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X10, X11, [SP, #216]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X12, X13, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X14, X3, [SP, #280]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X7, [SP, #296]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 51674c <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X6, [SP, #296]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVN X5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP X15, X9, [SP, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X10, X11, [SP, #216]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X12, X13, [SP, #264]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X14, X3, [SP, #280]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X8, [X6, #184]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X26, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 4db158 <hypre_ParMatmul._omp_fn.3+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 4db158 <hypre_ParMatmul._omp_fn.3+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X30, X25, X0, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD X1, X0, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X3, X20, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X4, X1, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X18, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X3, [SP, #120]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4db128 <hypre_ParMatmul._omp_fn.3+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	par_csr_matop.c:829-995
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 30.33 to 4.17 cycles (7.28x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 30.33 to 1.50 cycles (20.22x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 592 bytes. The binary function is storing 400 bytes.

General properties

nb instructions	132
loop length	528
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

16.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	8.50	8.50	8.50	8.50	0.50	0.50	0.00	0.00	30.33	30.33	30.33	17.50	17.50
cycles	5.50	5.50	8.50	8.50	8.50	8.50	0.50	0.50	0.00	0.00	30.33	30.33	30.33	17.50	17.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	16.50
Overall L1	30.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 30.33 cycles. At this rate:

20% of peak load performance is reached (19.52 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
27% of peak store performance is reached (13.19 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4db010

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #720]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X2, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X1, [X2, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X2, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [X2, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X5, [X2, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X6, [X2, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X5, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X20, [X0, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X3, [SP, #176]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X1, [SP, #192]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X7, [X2, #56]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X6, [SP, #248]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [SP, #256]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X0, [SP, #184]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X22, X27, [X2, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X7, [SP, #152]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X2, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR D8, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
LDP X14, X15, [X2, #88]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X13, X26, [X2, #104]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X12, X19, [X2, #128]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X9, X8, [X2, #208]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X2, [SP, #120]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X2, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X11, [X2, #176]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X15, [SP, #168]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X2, #192]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X16, [SP, #160]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X17, [X2, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X11, X12, [SP, #216]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X2, #224]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X9, X10, [SP, #200]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X25, [X2, #240]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X18, [SP, #232]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR D8, [X2, #248]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR X17, [SP, #240]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X13, X14, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X25, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X24, X23, [X2, #152]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X28, [X2, #232]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 519580 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 519560 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR X2, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SDIV X0, X20, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	5-20	5-20
LDR X7, [SP, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X9, X10, [SP, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X11, X12, [SP, #216]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X13, X14, [SP, #264]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MSUB X20, X0, X2, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR X15, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X20, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 4db500 <hypre_ParMatmul._omp_fn.3+0x4f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X5, X25, X0, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD X6, X0, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X8, X25, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X16, X6, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X18, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X17, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X17, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X7, #184]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X3, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X25, [X7, #144]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X7, #168]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X20, [X25]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X2]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X1, X26, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X20, [X20, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [X4, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X1, 4db494 <hypre_ParMatmul._omp_fn.3+0x484>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X1, [SP, #128]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [SP, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X7, X1, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X4, [SP, #192]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X7, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X16, X4, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X5, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 4db474 <hypre_ParMatmul._omp_fn.3+0x464>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X28, X15, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X9, [SP, #280]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X28, [SP, #144]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X28, 4db254 <hypre_ParMatmul._omp_fn.3+0x244>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR D8, [SP, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X29, X30, [SP], #304	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 516820 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X26, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STP X15, X9, [SP, #200]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X10, X11, [SP, #216]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X12, X13, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X14, X3, [SP, #280]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X7, [SP, #296]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 51674c <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X6, [SP, #296]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVN X5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP X15, X9, [SP, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X10, X11, [SP, #216]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X12, X13, [SP, #264]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X14, X3, [SP, #280]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X8, [X6, #184]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X26, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 4db158 <hypre_ParMatmul._omp_fn.3+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 4db158 <hypre_ParMatmul._omp_fn.3+0x148>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X30, X25, X0, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD X1, X0, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X3, X20, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X4, X1, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X18, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X3, [SP, #120]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4db128 <hypre_ParMatmul._omp_fn.3+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼hypre_ParMatmul._omp_fn.3–	0.99	0.37
○Loop 2979 - par_csr_matop.c:858-859 - exec	0.01	0
▼Loop 2974 - par_csr_matop.c:865-989 - exec–	0	0
▼Loop 2970 - par_csr_matop.c:865-989 - exec–	0.01	0.01
▼Loop 2975 - par_csr_matop.c:937-989 - exec–	0.23	0.08
○Loop 2978 - par_csr_matop.c:946-965 - exec	0.74	0.24
○Loop 2976 - par_csr_matop.c:970-989 - exec	0	0
○Loop 2977 - par_csr_matop.c:970-989 - exec	0	0
▼Loop 2971 - par_csr_matop.c:888-928 - exec–	0	0
○Loop 2972 - par_csr_matop.c:917-928 - exec	0	0
○Loop 2973 - par_csr_matop.c:897-915 - exec	0	0

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

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Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code