OV - exec - Function hypre_ParMatmul_RowSizes._omp

	Function: hypre_ParMatmul_RowSizes._omp_fn.0	Module: exec	Source: par_csr_matop.c:102-276 [...]	Coverage: 0.74%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 102 - 276

--------------------------------------------------------------------------------

102: #pragma omp parallel private(ii, i1, jj_row_begin_diag, jj_row_begin_offd, jj_count_diag, jj_count_offd, jj2, i2, jj3, i3)

103: #endif

104:    /*for (ii=0; ii < num_threads; ii++)*/

105:    {

106:     HYPRE_Int *B_marker = NULL;

107:     HYPRE_Int ns, ne;

108:     ii = hypre_GetThreadNum();

109:     if (ii < rest)

110:     {

111:        ns = ii*size+ii;

112:        ne = (ii+1)*size+ii+1;

113:     }

114:     else

115:     {

116:        ns = ii*size+rest;

117:        ne = (ii+1)*size+rest;

118:     }

119:     jj_count_diag = start_indexing;

120:     jj_count_offd = start_indexing;

121:

122:     if (num_cols_diag_B || num_cols_offd_C)

123:     B_marker = hypre_CTAlloc(HYPRE_Int, num_cols_diag_B+num_cols_offd_C);

124:     for (i1 = 0; i1 < num_cols_diag_B+num_cols_offd_C; i1++)

125:       B_marker[i1] = -1;

126:

127:     for (i1 = ns; i1 < ne; i1++)

[...]

135:       if ( allsquare ) {

136:          B_marker[i1] = jj_count_diag;

137:          jj_count_diag++;

[...]

144:       if (num_cols_offd_A)

145:       {

146:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

[...]

154:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

155:             {

156:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

164:                if (B_marker[i3] < jj_row_begin_offd)

165:                {

166:                   B_marker[i3] = jj_count_offd;

167:                   jj_count_offd++;

168:                }

169:             }

170:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

171:             {

172:                i3 = B_ext_diag_j[jj3];

173:

174:                if (B_marker[i3] < jj_row_begin_diag)

175:                {

176:                   B_marker[i3] = jj_count_diag;

177:                   jj_count_diag++;

[...]

187:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

[...]

195:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

[...]

205:             if (B_marker[i3] < jj_row_begin_diag)

206:             {

207:                B_marker[i3] = jj_count_diag;

208:                jj_count_diag++;

[...]

216:          if (num_cols_offd_B)

217:          {

218:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

219:             {

220:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

228:                if (B_marker[i3] < jj_row_begin_offd)

229:                {

230:                   B_marker[i3] = jj_count_offd;

231:                   jj_count_offd++;

[...]

241:       (*C_diag_i)[i1] = jj_row_begin_diag;

242:       (*C_offd_i)[i1] = jj_row_begin_offd;

243:

244:     }

245:     jj_count_diag_array[ii] = jj_count_diag;

246:     jj_count_offd_array[ii] = jj_count_offd;

247:

248:     hypre_TFree(B_marker);

249: #ifdef HYPRE_USING_OPENMP

250: #pragma omp barrier

251: #endif

252:

253:     if (ii)

254:     {

255:        jj_count_diag = jj_count_diag_array[0];

256:        jj_count_offd = jj_count_offd_array[0];

257:        for (i1 = 1; i1 < ii; i1++)

258:        {

259:           jj_count_diag += jj_count_diag_array[i1];

260:           jj_count_offd += jj_count_offd_array[i1];

261:        }

262:

263:        for (i1 = ns; i1 < ne; i1++)

264:        {

265:           (*C_diag_i)[i1] += jj_count_diag;

266:           (*C_offd_i)[i1] += jj_count_offd;

267:        }

268:     }

269:     else

270:     {

271:        (*C_diag_i)[num_rows_diag_A] = 0;

272:        (*C_offd_i)[num_rows_diag_A] = 0;

273:        for (i1 = 0; i1 < num_threads; i1++)

274:        {

275:           (*C_diag_i)[num_rows_diag_A] += jj_count_diag_array[i1];

276:           (*C_offd_i)[num_rows_diag_A] += jj_count_offd_array[i1];

0x4da520 STP	X29, X30, [SP, #768]!

0x4da524 ADD	X29, SP, #0

0x4da528 STP	X27, X28, [SP, #80]

0x4da52c LDR	X2, [X0]

0x4da530 LDP	X28, X6, [X0, #16]

0x4da534 LDP	X9, X27, [X0, #64]

0x4da538 STP	X19, X20, [SP, #16]

0x4da53c LDR	X3, [X0, #8]

0x4da540 STP	X21, X22, [SP, #32]

0x4da544 LDR	X11, [X0, #32]

0x4da548 STP	X23, X24, [SP, #48]

0x4da54c LDR	X4, [X0, #40]

0x4da550 STP	X25, X26, [SP, #64]

0x4da554 LDR	X1, [X0, #208]

0x4da558 STR	X4, [SP, #104]

0x4da55c LDR	X8, [X0, #80]

0x4da560 STR	X3, [SP, #176]

0x4da564 STR	X2, [SP, #184]

0x4da568 STP	X9, X11, [SP, #216]

0x4da56c STP	X6, X1, [SP, #232]

0x4da570 LDP	X23, X21, [X0, #48]

0x4da574 STR	X8, [SP, #208]

0x4da578 LDP	X26, X7, [X0, #88]

0x4da57c LDP	X25, X24, [X0, #104]

0x4da580 LDP	X22, X5, [X0, #144]

0x4da584 LDP	X19, X20, [X0, #160]

0x4da588 STR	X5, [SP, #160]

0x4da58c LDR	X10, [X0, #120]

0x4da590 LDR	X13, [X0, #128]

0x4da594 LDR	X14, [X0, #136]

0x4da598 STP	X10, X7, [SP, #192]

0x4da59c LDR	X15, [X0, #176]

0x4da5a0 STR	X14, [SP, #136]

0x4da5a4 LDR	X16, [X0, #184]

0x4da5a8 STR	X13, [SP, #144]

0x4da5ac LDR	X12, [X0, #200]

0x4da5b0 STR	X15, [SP, #168]

0x4da5b4 LDR	X0, [X0, #192]

0x4da5b8 STR	X16, [SP, #128]

0x4da5bc STR	X12, [SP, #112]

0x4da5c0 STR	X0, [SP, #120]

0x4da5c4 BL	519580

0x4da5c8 LDP	X6, X1, [SP, #232]

0x4da5cc STR	X0, [SP, #152]

0x4da5d0 LDR	X18, [SP, #112]

0x4da5d4 CMP	X1, X0

0x4da5d8 LDP	X7, X8, [SP, #200]

0x4da5dc LDP	X9, X11, [SP, #216]

0x4da5e0 LDR	X5, [SP, #160]

0x4da5e4 B.LE	4daadc

0x4da5e8 MADD	X4, X18, X0, XZR

0x4da5ec ADD	X12, X18, X4

0x4da5f0 ADD	X10, X0, X4

0x4da5f4 ADD	X13, X12, X0

0x4da5f8 ADD	X14, X13, #1

0x4da5fc STR	X14, [SP, #112]

0x4da600 ORR	X15, X19, X22

0x4da604 CBNZ	X15, 4daa54

0x4da608 MOVZ	X19, #0

(2955) 0x4da60c LDR	X16, [SP, #112]

(2955) 0x4da610 CMP	X10, X16

(2955) 0x4da614 B.GE	4daad0

(2955) 0x4da618 LDR	X1, [SP, #184]

(2955) 0x4da61c ADD	X0, X10, #1

(2955) 0x4da620 ORR	X17, XZR, X10

(2955) 0x4da624 STR	X10, [SP, #200]

(2955) 0x4da628 UBFM	X16, X0, #61, #60

(2955) 0x4da62c ORR	X15, XZR, X20

(2955) 0x4da630 LDR	X2, [SP, #176]

(2955) 0x4da634 LDR	X3, [SP, #136]

(2955) 0x4da638 LDR	X30, [X1]

(2955) 0x4da63c LDR	X2, [X2]

(2955) 0x4da640 LDR	X14, [SP, #104]

(2955) 0x4da644 STR	X30, [SP, #160]

(2955) 0x4da648 CBNZ	X3, 4da708

  (2959) 0x4da64c LDR	X4, [SP, #144]

  (2959) 0x4da650 ORR	X3, XZR, X20

  (2959) 0x4da654 ORR	X12, XZR, X15

  (2959) 0x4da658 CBNZ	X4, 4da71c

  (2959) 0x4da65c LDR	X18, [X28, X17,LSL #3]

  (2959) 0x4da660 ORR	X4, XZR, X25

  (2959) 0x4da664 LDR	X30, [X28, X16]

  (2959) 0x4da668 CMP	X18, X30

  (2959) 0x4da66c B.GE	4da6d8

    (2964) 0x4da670 LDR	X30, [X6, X18,LSL #3]

    (2964) 0x4da674 UBFM	X25, X30, #61, #60

    (2964) 0x4da678 LDR	X0, [X23, X30,LSL #3]

    (2964) 0x4da67c ADD	X13, X25, #8

    (2964) 0x4da680 LDR	X10, [X23, X13]

    (2964) 0x4da684 ADD	X25, X23, X13

    (2964) 0x4da688 CMP	X0, X10

    (2964) 0x4da68c B.GE	4da6c0

    (2964) 0x4da690 STR	X2, [SP, #104]

    (2964) 0x4da694 HINT	#0

    (2964) 0x4da698 HINT	#0

    (2964) 0x4da69c HINT	#0

      (2967) 0x4da6a0 LDR	X1, [X21, X0,LSL #3]

      (2967) 0x4da6a4 LDR	X2, [X19, X1,LSL #3]

      (2967) 0x4da6a8 CMP	X2, X20

      (2967) 0x4da6ac B.LT	4da7d4

      (2967) 0x4da6b0 ADD	X0, X0, #1

      (2967) 0x4da6b4 CMP	X0, X10

      (2967) 0x4da6b8 B.LT	4da6a0

    (2964) 0x4da6bc LDR	X2, [SP, #104]

    (2964) 0x4da6c0 CBNZ	X5, 4da7f4

    (2964) 0x4da6c4 LDR	X30, [X28, X16]

    (2964) 0x4da6c8 ADD	X18, X18, #1

    (2964) 0x4da6cc CMP	X30, X18

    (2964) 0x4da6d0 B.GT	4da670

  (2959) 0x4da6d4 ORR	X25, XZR, X4

  (2959) 0x4da6d8 LDR	X4, [SP, #160]

  (2959) 0x4da6dc ADD	X16, X16, #8

  (2959) 0x4da6e0 STR	X20, [X4, X17,LSL #3]

  (2959) 0x4da6e4 LDR	X20, [SP, #112]

  (2959) 0x4da6e8 STR	X15, [X2, X17,LSL #3]

  (2959) 0x4da6ec ADD	X17, X17, #1

  (2959) 0x4da6f0 CMP	X20, X17

  (2959) 0x4da6f4 B.EQ	4da8a8

  (2959) 0x4da6f8 ORR	X20, XZR, X3

  (2959) 0x4da6fc LDR	X3, [SP, #136]

  (2959) 0x4da700 ORR	X15, XZR, X12

  (2959) 0x4da704 CBZ	X3, 4da64c

  (2963) 0x4da708 STR	X20, [X19, X17,LSL #3]

  (2963) 0x4da70c ADD	X3, X20, #1

  (2963) 0x4da710 ORR	X12, XZR, X15

  (2963) 0x4da714 LDR	X4, [SP, #144]

  (2963) 0x4da718 CBZ	X4, 4da65c

  (2959) 0x4da71c LDR	X18, [X11, X17,LSL #3]

  (2959) 0x4da720 LDR	X10, [X11, X16]

  (2959) 0x4da724 CMP	X18, X10

  (2959) 0x4da728 B.GE	4da65c

  (2959) 0x4da72c ORR	X4, XZR, X5

    (2960) 0x4da730 LDR	X30, [X14, X18,LSL #3]

    (2960) 0x4da734 UBFM	X5, X30, #61, #60

    (2960) 0x4da738 LDR	X1, [X7, X30,LSL #3]

    (2960) 0x4da73c ADD	X10, X5, #8

    (2960) 0x4da740 LDR	X5, [X7, X10]

    (2960) 0x4da744 ADD	X13, X7, X10

    (2960) 0x4da748 CMP	X1, X5

    (2960) 0x4da74c B.GE	4da784

    (2960) 0x4da750 STR	X2, [SP, #104]

    (2960) 0x4da754 HINT	#0

    (2960) 0x4da758 HINT	#0

    (2960) 0x4da75c HINT	#0

      (2962) 0x4da760 LDR	X0, [X25, X1,LSL #3]

      (2962) 0x4da764 ADD	X0, X22, X0

      (2962) 0x4da768 LDR	X2, [X19, X0,LSL #3]

      (2962) 0x4da76c CMP	X2, X15

      (2962) 0x4da770 B.LT	4da88c

      (2962) 0x4da774 ADD	X1, X1, #1

      (2962) 0x4da778 CMP	X1, X5

      (2962) 0x4da77c B.LT	4da760

    (2960) 0x4da780 LDR	X2, [SP, #104]

    (2960) 0x4da784 LDR	X0, [X8, X30,LSL #3]

    (2960) 0x4da788 ADD	X30, X8, X10

    (2960) 0x4da78c LDR	X1, [X8, X10]

    (2960) 0x4da790 CMP	X0, X1

    (2960) 0x4da794 B.GE	4da7bc

    (2960) 0x4da798 HINT	#0

    (2960) 0x4da79c HINT	#0

      (2961) 0x4da7a0 LDR	X13, [X26, X0,LSL #3]

      (2961) 0x4da7a4 LDR	X10, [X19, X13,LSL #3]

      (2961) 0x4da7a8 CMP	X10, X20

      (2961) 0x4da7ac B.LT	4da860

      (2961) 0x4da7b0 ADD	X0, X0, #1

      (2961) 0x4da7b4 CMP	X0, X1

      (2961) 0x4da7b8 B.LT	4da7a0

    (2960) 0x4da7bc LDR	X5, [X11, X16]

    (2960) 0x4da7c0 ADD	X18, X18, #1

    (2960) 0x4da7c4 CMP	X5, X18

    (2960) 0x4da7c8 B.GT	4da730

  (2959) 0x4da7cc ORR	X5, XZR, X4

  (2959) 0x4da7d0 B	4da65c

      (2967) 0x4da7d4 STR	X3, [X19, X1,LSL #3]

      (2967) 0x4da7d8 ADD	X0, X0, #1

      (2967) 0x4da7dc ADD	X3, X3, #1

      (2967) 0x4da7e0 LDR	X10, [X25]

      (2967) 0x4da7e4 CMP	X10, X0

      (2967) 0x4da7e8 B.GT	4da6a0

    (2964) 0x4da7ec LDR	X2, [SP, #104]

    (2964) 0x4da7f0 B	4da6c0

    (2964) 0x4da7f4 LDR	X1, [X9, X30,LSL #3]

    (2964) 0x4da7f8 ADD	X30, X9, X13

    (2964) 0x4da7fc LDR	X13, [X9, X13]

    (2964) 0x4da800 CMP	X1, X13

    (2964) 0x4da804 B.GE	4da6c4

      (2965) 0x4da808 LDR	X25, [X27, X1,LSL #3]

      (2965) 0x4da80c LDR	X0, [X24, X25,LSL #3]

      (2965) 0x4da810 ADD	X10, X22, X0

      (2965) 0x4da814 LDR	X25, [X19, X10,LSL #3]

      (2965) 0x4da818 CMP	X25, X15

      (2965) 0x4da81c B.LT	4da844

      (2966) 0x4da820 ADD	X1, X1, #1

      (2966) 0x4da824 CMP	X1, X13

      (2966) 0x4da828 B.GE	4da6c4

      (2966) 0x4da82c LDR	X25, [X27, X1,LSL #3]

      (2966) 0x4da830 LDR	X0, [X24, X25,LSL #3]

      (2966) 0x4da834 ADD	X10, X22, X0

      (2966) 0x4da838 LDR	X25, [X19, X10,LSL #3]

      (2966) 0x4da83c CMP	X25, X15

      (2966) 0x4da840 B.GE	4da820

      (2965) 0x4da844 STR	X12, [X19, X10,LSL #3]

      (2965) 0x4da848 ADD	X1, X1, #1

      (2965) 0x4da84c ADD	X12, X12, #1

      (2965) 0x4da850 LDR	X13, [X30]

      (2965) 0x4da854 CMP	X13, X1

      (2965) 0x4da858 B.GT	4da808

    (2964) 0x4da85c B	4da6c4

      (2961) 0x4da860 STR	X3, [X19, X13,LSL #3]

      (2961) 0x4da864 ADD	X0, X0, #1

      (2961) 0x4da868 ADD	X3, X3, #1

      (2961) 0x4da86c LDR	X1, [X30]

      (2961) 0x4da870 CMP	X1, X0

      (2961) 0x4da874 B.GT	4da7a0

    (2960) 0x4da878 LDR	X5, [X11, X16]

    (2960) 0x4da87c ADD	X18, X18, #1

    (2960) 0x4da880 CMP	X5, X18

    (2960) 0x4da884 B.GT	4da730

  (2959) 0x4da888 B	4da7cc

      (2962) 0x4da88c STR	X12, [X19, X0,LSL #3]

      (2962) 0x4da890 ADD	X1, X1, #1

      (2962) 0x4da894 ADD	X12, X12, #1

      (2962) 0x4da898 LDR	X5, [X13]

      (2962) 0x4da89c CMP	X5, X1

      (2962) 0x4da8a0 B.GT	4da760

    (2960) 0x4da8a4 B	4da780

(2955) 0x4da8a8 LDR	X10, [SP, #200]

(2955) 0x4da8ac ORR	X0, XZR, X19

(2955) 0x4da8b0 STR	X10, [SP, #104]

(2955) 0x4da8b4 LDR	X28, [SP, #128]

(2955) 0x4da8b8 LDR	X23, [SP, #152]

(2955) 0x4da8bc LDR	X26, [SP, #120]

(2955) 0x4da8c0 STR	X3, [X28, X23,LSL #3]

(2955) 0x4da8c4 STR	X12, [X26, X23,LSL #3]

(2955) 0x4da8c8 BL	516820

(2955) 0x4da8cc BL	40f590

(2955) 0x4da8d0 LDR	X10, [SP, #104]

(2955) 0x4da8d4 CBNZ	X23, 4daaf4

(2955) 0x4da8d8 LDP	X22, X7, [SP, #184]

(2955) 0x4da8dc LDR	X11, [SP, #176]

(2955) 0x4da8e0 UBFM	X8, X7, #61, #60

(2955) 0x4da8e4 LDR	X9, [X22]

(2955) 0x4da8e8 LDR	X14, [SP, #168]

(2955) 0x4da8ec LDR	X6, [X11]

(2955) 0x4da8f0 STR	XZR, [X9, X7,LSL #3]

(2955) 0x4da8f4 ADD	X1, X9, X8

(2955) 0x4da8f8 STR	XZR, [X6, X7,LSL #3]

(2955) 0x4da8fc ADD	X0, X6, X8

(2955) 0x4da900 CMP	X14, #0

(2955) 0x4da904 B.LE	4daa38

(2955) 0x4da908 ANDS	X15, X14, #4160

(2955) 0x4da90c B.EQ	4daf14

(2955) 0x4da910 CMP	X15, #1

(2955) 0x4da914 B.EQ	4da954

(2955) 0x4da918 CMP	X15, #2

(2955) 0x4da91c B.NE	4daee0

(2955) 0x4da920 LDR	X16, [SP, #128]

(2955) 0x4da924 LDR	X4, [SP, #152]

(2955) 0x4da928 LDR	X18, [X1]

(2955) 0x4da92c LDR	X28, [SP, #120]

(2955) 0x4da930 ADD	X21, X4, #1

(2955) 0x4da934 LDR	X17, [X16, X4,LSL #3]

(2955) 0x4da938 STR	X21, [SP, #152]

(2955) 0x4da93c ADD	X20, X18, X17

(2955) 0x4da940 STR	X20, [X1]

(2955) 0x4da944 LDR	X23, [X28, X4,LSL #3]

(2955) 0x4da948 LDR	X27, [X0]

(2955) 0x4da94c ADD	X26, X27, X23

(2955) 0x4da950 STR	X26, [X0]

(2955) 0x4da954 LDR	X22, [SP, #128]

(2955) 0x4da958 LDR	X7, [SP, #152]

(2955) 0x4da95c LDR	X24, [X1]

(2955) 0x4da960 LDR	X11, [SP, #120]

(2955) 0x4da964 ADD	X14, X7, #1

(2955) 0x4da968 LDR	X8, [X22, X7,LSL #3]

(2955) 0x4da96c STR	X14, [SP, #152]

(2955) 0x4da970 LDR	X12, [SP, #168]

(2955) 0x4da974 ADD	X9, X24, X8

(2955) 0x4da978 STR	X9, [X1]

(2955) 0x4da97c LDR	X6, [X11, X7,LSL #3]

(2955) 0x4da980 LDR	X15, [X0]

(2955) 0x4da984 ADD	X19, X15, X6

(2955) 0x4da988 STR	X19, [X0]

(2955) 0x4da98c CMP	X12, X14

(2955) 0x4da990 B.EQ	4daa38

(2955) 0x4da994 LDP	X3, X10, [SP, #120]

(2955) 0x4da998 ORR	X2, XZR, X14

  (2958) 0x4da99c ADD	X25, X2, #1

  (2958) 0x4da9a0 ADD	X30, X2, #2

  (2958) 0x4da9a4 ADD	X13, X2, #3

  (2958) 0x4da9a8 LDR	X18, [X10, X2,LSL #3]

  (2958) 0x4da9ac LDR	X5, [X1]

  (2958) 0x4da9b0 ADD	X16, X5, X18

  (2958) 0x4da9b4 STR	X16, [X1]

  (2958) 0x4da9b8 LDR	X4, [X3, X2,LSL #3]

  (2958) 0x4da9bc ADD	X2, X2, #4

  (2958) 0x4da9c0 LDR	X17, [X0]

  (2958) 0x4da9c4 ADD	X20, X17, X4

  (2958) 0x4da9c8 STR	X20, [X0]

  (2958) 0x4da9cc LDR	X28, [X10, X25,LSL #3]

  (2958) 0x4da9d0 LDR	X23, [X1]

  (2958) 0x4da9d4 ADD	X21, X23, X28

  (2958) 0x4da9d8 STR	X21, [X1]

  (2958) 0x4da9dc LDR	X27, [X3, X25,LSL #3]

  (2958) 0x4da9e0 LDR	X26, [X0]

  (2958) 0x4da9e4 ADD	X24, X26, X27

  (2958) 0x4da9e8 STR	X24, [X0]

  (2958) 0x4da9ec LDR	X22, [X10, X30,LSL #3]

  (2958) 0x4da9f0 LDR	X7, [X1]

  (2958) 0x4da9f4 ADD	X8, X7, X22

  (2958) 0x4da9f8 STR	X8, [X1]

  (2958) 0x4da9fc LDR	X9, [X3, X30,LSL #3]

  (2958) 0x4daa00 LDR	X11, [X0]

  (2958) 0x4daa04 LDR	X30, [SP, #168]

  (2958) 0x4daa08 ADD	X6, X11, X9

  (2958) 0x4daa0c STR	X6, [X0]

  (2958) 0x4daa10 LDR	X14, [X10, X13,LSL #3]

  (2958) 0x4daa14 LDR	X15, [X1]

  (2958) 0x4daa18 ADD	X19, X15, X14

  (2958) 0x4daa1c STR	X19, [X1]

  (2958) 0x4daa20 LDR	X12, [X3, X13,LSL #3]

  (2958) 0x4daa24 LDR	X25, [X0]

  (2958) 0x4daa28 ADD	X13, X25, X12

  (2958) 0x4daa2c STR	X13, [X0]

  (2958) 0x4daa30 CMP	X30, X2

  (2958) 0x4daa34 B.NE	4da99c

(2955) 0x4daa38 LDP	X19, X20, [SP, #16]

(2955) 0x4daa3c LDP	X21, X22, [SP, #32]

(2955) 0x4daa40 LDP	X23, X24, [SP, #48]

(2955) 0x4daa44 LDP	X25, X26, [SP, #64]

(2955) 0x4daa48 LDP	X27, X28, [SP, #80]

(2955) 0x4daa4c LDP	X29, X30, [SP], #256

(2955) 0x4daa50 RET

(2955) 0x4daa54 ADD	X19, X19, X22

(2955) 0x4daa58 MOVZ	X1, #8

(2955) 0x4daa5c STP	X10, X5, [SP, #200]

(2955) 0x4daa60 ORR	X0, XZR, X19

(2955) 0x4daa64 STR	X19, [SP, #160]

(2955) 0x4daa68 STP	X7, X8, [SP, #216]

(2955) 0x4daa6c STP	X9, X11, [SP, #232]

(2955) 0x4daa70 STR	X6, [SP, #248]

(2955) 0x4daa74 BL	51674c

(2955) 0x4daa78 LDR	X18, [SP, #160]

(2955) 0x4daa7c ORR	X19, XZR, X0

(2955) 0x4daa80 LDP	X10, X5, [SP, #200]

(2955) 0x4daa84 LDP	X7, X8, [SP, #216]

(2955) 0x4daa88 LDP	X9, X11, [SP, #232]

(2955) 0x4daa8c LDR	X6, [SP, #248]

(2955) 0x4daa90 CMP	X18, #0

(2955) 0x4daa94 B.LE	4da60c

(2955) 0x4daa98 UBFM	X2, X18, #61, #60

(2955) 0x4daa9c MOVZ	W1, #255

(2955) 0x4daaa0 STR	X10, [SP, #160]

(2955) 0x4daaa4 STP	X5, X7, [SP, #200]

(2955) 0x4daaa8 STP	X8, X9, [SP, #216]

(2955) 0x4daaac STP	X11, X6, [SP, #232]

(2955) 0x4daab0 BL	40f370

(2955) 0x4daab4 LDR	X16, [SP, #112]

(2955) 0x4daab8 LDP	X5, X7, [SP, #200]

(2955) 0x4daabc LDP	X8, X9, [SP, #216]

(2955) 0x4daac0 LDP	X11, X6, [SP, #232]

(2955) 0x4daac4 LDR	X10, [SP, #160]

(2955) 0x4daac8 CMP	X10, X16

(2955) 0x4daacc B.LT	4da618

(2955) 0x4daad0 ORR	X12, XZR, X20

(2955) 0x4daad4 ORR	X3, XZR, X20

(2955) 0x4daad8 B	4da8ac

0x4daadc MADD	X17, X18, X0, XZR

0x4daae0 ADD	X30, X18, X17

0x4daae4 ADD	X10, X1, X17

0x4daae8 ADD	X2, X30, X1

0x4daaec STR	X2, [SP, #112]

0x4daaf0 B	4da600

(2955) 0x4daaf4 LDP	X3, X0, [SP, #120]

(2955) 0x4daaf8 MOVZ	X1, #1

(2955) 0x4daafc LDR	X18, [SP, #152]

(2955) 0x4dab00 LDR	X0, [X0]

(2955) 0x4dab04 LDR	X5, [X3]

(2955) 0x4dab08 CMP	X18, X1

(2955) 0x4dab0c B.LE	4dacc8

(2955) 0x4dab10 SUB	X16, X18, X1

(2955) 0x4dab14 ANDS	X4, X16, #4224

(2955) 0x4dab18 B.EQ	4dac18

(2955) 0x4dab1c CMP	X4, X1

(2955) 0x4dab20 B.EQ	4dabf0

(2955) 0x4dab24 CMP	X4, #2

(2955) 0x4dab28 B.EQ	4dabd4

(2955) 0x4dab2c CMP	X4, #3

(2955) 0x4dab30 B.EQ	4dabb8

(2955) 0x4dab34 CMP	X4, #4

(2955) 0x4dab38 B.EQ	4dab9c

(2955) 0x4dab3c CMP	X4, #5

(2955) 0x4dab40 B.EQ	4dab80

(2955) 0x4dab44 CMP	X4, #6

(2955) 0x4dab48 B.EQ	4dab64

(2955) 0x4dab4c LDP	X2, X1, [SP, #120]

(2955) 0x4dab50 LDR	X17, [X1, #8]

(2955) 0x4dab54 MOVZ	X1, #2

(2955) 0x4dab58 LDR	X20, [X2, #8]

(2955) 0x4dab5c ADD	X0, X0, X17

(2955) 0x4dab60 ADD	X5, X5, X20

(2955) 0x4dab64 LDR	X21, [SP, #120]

(2955) 0x4dab68 LDR	X28, [SP, #128]

(2955) 0x4dab6c LDR	X27, [X21, X1,LSL #3]

(2955) 0x4dab70 LDR	X23, [X28, X1,LSL #3]

(2955) 0x4dab74 ADD	X1, X1, #1

(2955) 0x4dab78 ADD	X5, X5, X27

(2955) 0x4dab7c ADD	X0, X0, X23

(2955) 0x4dab80 LDR	X22, [SP, #120]

(2955) 0x4dab84 LDR	X26, [SP, #128]

(2955) 0x4dab88 LDR	X7, [X22, X1,LSL #3]

(2955) 0x4dab8c LDR	X24, [X26, X1,LSL #3]

(2955) 0x4dab90 ADD	X1, X1, #1

(2955) 0x4dab94 ADD	X5, X5, X7

(2955) 0x4dab98 ADD	X0, X0, X24

(2955) 0x4dab9c LDR	X11, [SP, #120]

(2955) 0x4daba0 LDR	X8, [SP, #128]

(2955) 0x4daba4 LDR	X6, [X11, X1,LSL #3]

(2955) 0x4daba8 LDR	X9, [X8, X1,LSL #3]

(2955) 0x4dabac ADD	X1, X1, #1

(2955) 0x4dabb0 ADD	X5, X5, X6

(2955) 0x4dabb4 ADD	X0, X0, X9

(2955) 0x4dabb8 LDR	X19, [SP, #120]

(2955) 0x4dabbc LDR	X14, [SP, #128]

(2955) 0x4dabc0 LDR	X12, [X19, X1,LSL #3]

(2955) 0x4dabc4 LDR	X15, [X14, X1,LSL #3]

(2955) 0x4dabc8 ADD	X1, X1, #1

(2955) 0x4dabcc ADD	X5, X5, X12

(2955) 0x4dabd0 ADD	X0, X0, X15

(2955) 0x4dabd4 LDR	X30, [SP, #120]

(2955) 0x4dabd8 LDR	X25, [SP, #128]

(2955) 0x4dabdc LDR	X3, [X30, X1,LSL #3]

(2955) 0x4dabe0 LDR	X13, [X25, X1,LSL #3]

(2955) 0x4dabe4 ADD	X1, X1, #1

(2955) 0x4dabe8 ADD	X5, X5, X3

(2955) 0x4dabec ADD	X0, X0, X13

(2955) 0x4dabf0 LDR	X4, [SP, #120]

(2955) 0x4dabf4 LDR	X18, [SP, #128]

(2955) 0x4dabf8 LDR	X17, [SP, #152]

(2955) 0x4dabfc LDR	X2, [X4, X1,LSL #3]

(2955) 0x4dac00 LDR	X16, [X18, X1,LSL #3]

(2955) 0x4dac04 ADD	X1, X1, #1

(2955) 0x4dac08 ADD	X5, X5, X2

(2955) 0x4dac0c ADD	X0, X0, X16

(2955) 0x4dac10 CMP	X17, X1

(2955) 0x4dac14 B.EQ	4dacc8

(2955) 0x4dac18 LDP	X20, X28, [SP, #120]

  (2957) 0x4dac1c ADD	X23, X1, #1

  (2957) 0x4dac20 ADD	X26, X1, #2

  (2957) 0x4dac24 ADD	X27, X1, #3

  (2957) 0x4dac28 ADD	X24, X1, #4

  (2957) 0x4dac2c ADD	X8, X1, #5

  (2957) 0x4dac30 ADD	X7, X1, #6

  (2957) 0x4dac34 LDR	X21, [X28, X1,LSL #3]

  (2957) 0x4dac38 ADD	X6, X1, #7

  (2957) 0x4dac3c LDR	X22, [X20, X1,LSL #3]

  (2957) 0x4dac40 ADD	X1, X1, #8

  (2957) 0x4dac44 LDR	X9, [X28, X23,LSL #3]

  (2957) 0x4dac48 ADD	X11, X0, X21

  (2957) 0x4dac4c LDR	X14, [X20, X23,LSL #3]

  (2957) 0x4dac50 ADD	X15, X5, X22

  (2957) 0x4dac54 LDR	X19, [X28, X26,LSL #3]

  (2957) 0x4dac58 ADD	X25, X11, X9

  (2957) 0x4dac5c LDR	X12, [X20, X26,LSL #3]

  (2957) 0x4dac60 ADD	X13, X15, X14

  (2957) 0x4dac64 LDR	X30, [X28, X27,LSL #3]

  (2957) 0x4dac68 ADD	X3, X25, X19

  (2957) 0x4dac6c LDR	X18, [X20, X27,LSL #3]

  (2957) 0x4dac70 ADD	X16, X13, X12

  (2957) 0x4dac74 LDR	X2, [X28, X24,LSL #3]

  (2957) 0x4dac78 ADD	X0, X3, X30

  (2957) 0x4dac7c LDR	X4, [X20, X24,LSL #3]

  (2957) 0x4dac80 ADD	X5, X16, X18

  (2957) 0x4dac84 LDR	X17, [X28, X8,LSL #3]

  (2957) 0x4dac88 ADD	X23, X0, X2

  (2957) 0x4dac8c LDR	X21, [X20, X8,LSL #3]

  (2957) 0x4dac90 ADD	X27, X5, X4

  (2957) 0x4dac94 LDR	X26, [X28, X7,LSL #3]

  (2957) 0x4dac98 ADD	X24, X23, X17

  (2957) 0x4dac9c LDR	X22, [X20, X7,LSL #3]

  (2957) 0x4daca0 ADD	X8, X27, X21

  (2957) 0x4daca4 LDR	X7, [X28, X6,LSL #3]

  (2957) 0x4daca8 ADD	X9, X24, X26

  (2957) 0x4dacac LDR	X6, [X20, X6,LSL #3]

  (2957) 0x4dacb0 ADD	X11, X8, X22

  (2957) 0x4dacb4 LDR	X14, [SP, #152]

  (2957) 0x4dacb8 ADD	X0, X9, X7

  (2957) 0x4dacbc ADD	X5, X11, X6

  (2957) 0x4dacc0 CMP	X14, X1

  (2957) 0x4dacc4 B.NE	4dac1c

(2955) 0x4dacc8 LDR	X1, [SP, #112]

(2955) 0x4daccc CMP	X10, X1

(2955) 0x4dacd0 B.GE	4daa38

(2955) 0x4dacd4 LDR	X25, [SP, #176]

(2955) 0x4dacd8 SUB	X20, X1, X10

(2955) 0x4dacdc ANDS	X28, X20, #4224

(2955) 0x4dace0 LDR	X15, [SP, #184]

(2955) 0x4dace4 LDR	X13, [X25]

(2955) 0x4dace8 LDR	X19, [X15]

(2955) 0x4dacec B.EQ	4dadf0

(2955) 0x4dacf0 CMP	X28, #1

(2955) 0x4dacf4 B.EQ	4dadc8

(2955) 0x4dacf8 CMP	X28, #2

(2955) 0x4dacfc B.EQ	4dadac

(2955) 0x4dad00 CMP	X28, #3

(2955) 0x4dad04 B.EQ	4dad90

(2955) 0x4dad08 CMP	X28, #4

(2955) 0x4dad0c B.EQ	4dad74

(2955) 0x4dad10 CMP	X28, #5

(2955) 0x4dad14 B.EQ	4dad58

(2955) 0x4dad18 CMP	X28, #6

(2955) 0x4dad1c B.EQ	4dad3c

(2955) 0x4dad20 LDR	X12, [X19, X10,LSL #3]

(2955) 0x4dad24 ADD	X30, X12, X0

(2955) 0x4dad28 STR	X30, [X19, X10,LSL #3]

(2955) 0x4dad2c LDR	X3, [X13, X10,LSL #3]

(2955) 0x4dad30 ADD	X18, X3, X5

(2955) 0x4dad34 STR	X18, [X13, X10,LSL #3]

(2955) 0x4dad38 ADD	X10, X10, #1

(2955) 0x4dad3c LDR	X16, [X19, X10,LSL #3]

(2955) 0x4dad40 ADD	X2, X16, X0

(2955) 0x4dad44 STR	X2, [X19, X10,LSL #3]

(2955) 0x4dad48 LDR	X4, [X13, X10,LSL #3]

(2955) 0x4dad4c ADD	X17, X4, X5

(2955) 0x4dad50 STR	X17, [X13, X10,LSL #3]

(2955) 0x4dad54 ADD	X10, X10, #1

(2955) 0x4dad58 LDR	X23, [X19, X10,LSL #3]

(2955) 0x4dad5c ADD	X21, X23, X0

(2955) 0x4dad60 STR	X21, [X19, X10,LSL #3]

(2955) 0x4dad64 LDR	X27, [X13, X10,LSL #3]

(2955) 0x4dad68 ADD	X26, X27, X5

(2955) 0x4dad6c STR	X26, [X13, X10,LSL #3]

(2955) 0x4dad70 ADD	X10, X10, #1

(2955) 0x4dad74 LDR	X24, [X19, X10,LSL #3]

(2955) 0x4dad78 ADD	X22, X24, X0

(2955) 0x4dad7c STR	X22, [X19, X10,LSL #3]

(2955) 0x4dad80 LDR	X8, [X13, X10,LSL #3]

(2955) 0x4dad84 ADD	X7, X8, X5

(2955) 0x4dad88 STR	X7, [X13, X10,LSL #3]

(2955) 0x4dad8c ADD	X10, X10, #1

(2955) 0x4dad90 LDR	X9, [X19, X10,LSL #3]

(2955) 0x4dad94 ADD	X6, X9, X0

(2955) 0x4dad98 STR	X6, [X19, X10,LSL #3]

(2955) 0x4dad9c LDR	X11, [X13, X10,LSL #3]

(2955) 0x4dada0 ADD	X14, X11, X5

(2955) 0x4dada4 STR	X14, [X13, X10,LSL #3]

(2955) 0x4dada8 ADD	X10, X10, #1

(2955) 0x4dadac LDR	X1, [X19, X10,LSL #3]

(2955) 0x4dadb0 ADD	X20, X1, X0

(2955) 0x4dadb4 STR	X20, [X19, X10,LSL #3]

(2955) 0x4dadb8 LDR	X28, [X13, X10,LSL #3]

(2955) 0x4dadbc ADD	X15, X28, X5

(2955) 0x4dadc0 STR	X15, [X13, X10,LSL #3]

(2955) 0x4dadc4 ADD	X10, X10, #1

(2955) 0x4dadc8 LDR	X25, [X19, X10,LSL #3]

(2955) 0x4dadcc LDR	X18, [SP, #112]

(2955) 0x4dadd0 ADD	X12, X25, X0

(2955) 0x4dadd4 STR	X12, [X19, X10,LSL #3]

(2955) 0x4dadd8 LDR	X30, [X13, X10,LSL #3]

(2955) 0x4daddc ADD	X3, X30, X5

(2955) 0x4dade0 STR	X3, [X13, X10,LSL #3]

(2955) 0x4dade4 ADD	X10, X10, #1

(2955) 0x4dade8 CMP	X18, X10

(2955) 0x4dadec B.EQ	4daa38

  (2956) 0x4dadf0 LDR	X16, [X19, X10,LSL #3]

  (2956) 0x4dadf4 ADD	X2, X10, #1

  (2956) 0x4dadf8 ADD	X23, X10, #2

  (2956) 0x4dadfc ADD	X17, X10, #3

  (2956) 0x4dae00 ADD	X21, X10, #4

  (2956) 0x4dae04 ADD	X27, X10, #5

  (2956) 0x4dae08 ADD	X26, X10, #6

  (2956) 0x4dae0c ADD	X4, X10, #7

  (2956) 0x4dae10 ADD	X24, X16, X0

  (2956) 0x4dae14 STR	X24, [X19, X10,LSL #3]

  (2956) 0x4dae18 LDR	X22, [X13, X10,LSL #3]

  (2956) 0x4dae1c ADD	X8, X22, X5

  (2956) 0x4dae20 STR	X8, [X13, X10,LSL #3]

  (2956) 0x4dae24 ADD	X10, X10, #8

  (2956) 0x4dae28 LDR	X7, [X19, X2,LSL #3]

  (2956) 0x4dae2c ADD	X9, X7, X0

  (2956) 0x4dae30 STR	X9, [X19, X2,LSL #3]

  (2956) 0x4dae34 LDR	X6, [X13, X2,LSL #3]

  (2956) 0x4dae38 ADD	X11, X6, X5

  (2956) 0x4dae3c STR	X11, [X13, X2,LSL #3]

  (2956) 0x4dae40 LDR	X14, [X19, X23,LSL #3]

  (2956) 0x4dae44 ADD	X1, X14, X0

  (2956) 0x4dae48 STR	X1, [X19, X23,LSL #3]

  (2956) 0x4dae4c LDR	X20, [X13, X23,LSL #3]

  (2956) 0x4dae50 ADD	X28, X20, X5

  (2956) 0x4dae54 STR	X28, [X13, X23,LSL #3]

  (2956) 0x4dae58 LDR	X15, [X19, X17,LSL #3]

  (2956) 0x4dae5c ADD	X25, X15, X0

  (2956) 0x4dae60 STR	X25, [X19, X17,LSL #3]

  (2956) 0x4dae64 LDR	X12, [X13, X17,LSL #3]

  (2956) 0x4dae68 ADD	X30, X12, X5

  (2956) 0x4dae6c STR	X30, [X13, X17,LSL #3]

  (2956) 0x4dae70 LDR	X3, [X19, X21,LSL #3]

  (2956) 0x4dae74 ADD	X18, X3, X0

  (2956) 0x4dae78 STR	X18, [X19, X21,LSL #3]

  (2956) 0x4dae7c LDR	X16, [X13, X21,LSL #3]

  (2956) 0x4dae80 ADD	X2, X16, X5

  (2956) 0x4dae84 STR	X2, [X13, X21,LSL #3]

  (2956) 0x4dae88 LDR	X17, [X19, X27,LSL #3]

  (2956) 0x4dae8c ADD	X23, X17, X0

  (2956) 0x4dae90 STR	X23, [X19, X27,LSL #3]

  (2956) 0x4dae94 LDR	X21, [X13, X27,LSL #3]

  (2956) 0x4dae98 ADD	X24, X21, X5

  (2956) 0x4dae9c STR	X24, [X13, X27,LSL #3]

  (2956) 0x4daea0 LDR	X27, [X19, X26,LSL #3]

  (2956) 0x4daea4 ADD	X22, X27, X0

  (2956) 0x4daea8 STR	X22, [X19, X26,LSL #3]

  (2956) 0x4daeac LDR	X8, [X13, X26,LSL #3]

  (2956) 0x4daeb0 ADD	X7, X8, X5

  (2956) 0x4daeb4 STR	X7, [X13, X26,LSL #3]

  (2956) 0x4daeb8 LDR	X26, [X19, X4,LSL #3]

  (2956) 0x4daebc ADD	X9, X26, X0

  (2956) 0x4daec0 STR	X9, [X19, X4,LSL #3]

  (2956) 0x4daec4 LDR	X6, [X13, X4,LSL #3]

  (2956) 0x4daec8 ADD	X11, X6, X5

  (2956) 0x4daecc STR	X11, [X13, X4,LSL #3]

  (2956) 0x4daed0 LDR	X4, [SP, #112]

  (2956) 0x4daed4 CMP	X4, X10

  (2956) 0x4daed8 B.NE	4dadf0

(2955) 0x4daedc B	4daa38

(2955) 0x4daee0 LDR	X3, [SP, #128]

(2955) 0x4daee4 MOVZ	X19, #1

(2955) 0x4daee8 LDR	X12, [X1]

(2955) 0x4daeec STR	X19, [SP, #152]

(2955) 0x4daef0 LDR	X10, [SP, #120]

(2955) 0x4daef4 LDR	X5, [X3]

(2955) 0x4daef8 ADD	X2, X12, X5

(2955) 0x4daefc STR	X2, [X1]

(2955) 0x4daf00 LDR	X25, [X0]

(2955) 0x4daf04 LDR	X13, [X10]

(2955) 0x4daf08 ADD	X30, X25, X13

(2955) 0x4daf0c STR	X30, [X0]

(2955) 0x4daf10 B	4da920

(2955) 0x4daf14 LDP	X3, X10, [SP, #120]

(2955) 0x4daf18 LDR	X2, [SP, #152]

(2955) 0x4daf1c B	4da99c

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	par_csr_matop.c:102-276
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:102-127,135-137,144-146,154-156,164-177,187,195,205-208,216-220,228-231,241-276.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 16.17 to 4.04 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 16.17 to 0.50 cycles (32.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 280 bytes. The binary function is storing 256 bytes.

General properties

nb instructions	65
loop length	260
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	16.17	15.83	16.00	11.50	11.50
cycles	2.00	2.00	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	16.17	15.83	16.00	11.50	11.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.13
Overall L1	16.17

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.17 cycles. At this rate:

18% of peak load performance is reached (17.32 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
32% of peak store performance is reached (15.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4da520

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #768]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X2, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X28, X6, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X9, X27, [X0, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X0, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X11, [X0, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [X0, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X1, [X0, #208]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X4, [SP, #104]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X0, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X3, [SP, #176]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X2, [SP, #184]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X9, X11, [SP, #216]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X6, X1, [SP, #232]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X23, X21, [X0, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X8, [SP, #208]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X26, X7, [X0, #88]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X24, [X0, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X5, [X0, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X19, X20, [X0, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X5, [SP, #160]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X0, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X0, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X0, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X10, X7, [SP, #192]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [X0, #176]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X14, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X0, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X13, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X0, #200]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X15, [SP, #168]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X0, #192]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X16, [SP, #128]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X12, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X0, [SP, #120]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 519580 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDP X6, X1, [SP, #232]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X0, [SP, #152]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
LDP X7, X8, [SP, #200]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X9, X11, [SP, #216]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X5, [SP, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.LE 4daadc <hypre_ParMatmul_RowSizes._omp_fn.0+0x5bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MADD X4, X18, X0, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD X12, X18, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X10, X0, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X13, X12, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X14, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X14, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X15, X19, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CBNZ X15, 4daa54 <hypre_ParMatmul_RowSizes._omp_fn.0+0x534>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X17, X18, X0, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD X30, X18, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X10, X1, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X2, X30, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X2, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4da600 <hypre_ParMatmul_RowSizes._omp_fn.0+0xe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	par_csr_matop.c:102-276
Module	exec

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 16.17 to 0.50 cycles (32.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 280 bytes. The binary function is storing 256 bytes.

General properties

nb instructions	65
loop length	260
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	16.17	15.83	16.00	11.50	11.50
cycles	2.00	2.00	3.75	3.75	3.75	3.75	0.00	0.00	0.00	0.00	16.17	15.83	16.00	11.50	11.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.13
Overall L1	16.17

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.17 cycles. At this rate:

18% of peak load performance is reached (17.32 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
32% of peak store performance is reached (15.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4da520

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #768]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X2, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X28, X6, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X9, X27, [X0, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X0, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X11, [X0, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [X0, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X1, [X0, #208]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X4, [SP, #104]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X0, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X3, [SP, #176]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X2, [SP, #184]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X9, X11, [SP, #216]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X6, X1, [SP, #232]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X23, X21, [X0, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X8, [SP, #208]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X26, X7, [X0, #88]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X24, [X0, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X5, [X0, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X19, X20, [X0, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X5, [SP, #160]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X0, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X0, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X0, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X10, X7, [SP, #192]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [X0, #176]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X14, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X0, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X13, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X0, #200]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X15, [SP, #168]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X0, #192]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X16, [SP, #128]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X12, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X0, [SP, #120]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 519580 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDP X6, X1, [SP, #232]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X0, [SP, #152]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
LDP X7, X8, [SP, #200]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X9, X11, [SP, #216]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X5, [SP, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.LE 4daadc <hypre_ParMatmul_RowSizes._omp_fn.0+0x5bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MADD X4, X18, X0, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD X12, X18, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X10, X0, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X13, X12, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X14, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X14, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X15, X19, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CBNZ X15, 4daa54 <hypre_ParMatmul_RowSizes._omp_fn.0+0x534>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X17, X18, X0, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
ADD X30, X18, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X10, X1, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X2, X30, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X2, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4da600 <hypre_ParMatmul_RowSizes._omp_fn.0+0xe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼hypre_ParMatmul_RowSizes._omp_fn.0–	0.74	0.28
▼Loop 2955 - par_csr_matop.c:102-276 - exec–	0	0
▼Loop 2959 - par_csr_matop.c:127-242 - exec–	0.04	0.01
▼Loop 2964 - par_csr_matop.c:187-231 - exec–	0.28	0.09
○Loop 2967 - par_csr_matop.c:195-208 - exec	0.4	0.13
○Loop 2965 - par_csr_matop.c:218-231 - exec	0	0
○Loop 2966 - par_csr_matop.c:218-228 - exec	0	0
▼Loop 2960 - par_csr_matop.c:146-177 - exec–	0	0
○Loop 2962 - par_csr_matop.c:154-167 - exec	0	0
○Loop 2961 - par_csr_matop.c:170-177 - exec	0	0
○Loop 2956 - par_csr_matop.c:263-266 - exec	0.01	0
○Loop 2957 - par_csr_matop.c:257-260 - exec	0	0
○Loop 2958 - par_csr_matop.c:273-276 - exec	0	0
○Loop 2963 - par_csr_matop.c:136-146 - exec	0	0

Report Configuration

Vectorization

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

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Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code