OV - exec - Function hypre_ParCSRRelaxThreads._omp

	Function: hypre_ParCSRRelaxThreads._omp_fn.1	Module: exec	Source: ams.c:3662-3682 [...]	Coverage: 30.97%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3662 - 3682

--------------------------------------------------------------------------------

3662: #pragma omp parallel for private(i,ii,jj,res) HYPRE_SMP_SCHEDULE

[...]

3669:          if (A_diag_data[A_diag_i[i]] != zero)

3670:          {

3671:             res = f_data[i];

3672:             for (jj = A_diag_i[i]; jj < A_diag_i[i+1]; jj++)

3673:             {

3674:                ii = A_diag_j[jj];

3675:                res -= A_diag_data[jj] * Vtemp_data[ii];

3676:             }

3677:             for (jj = A_offd_i[i]; jj < A_offd_i[i+1]; jj++)

3678:             {

3679:                ii = A_offd_j[jj];

3680:                res -= A_offd_data[jj] * Vext_data[ii];

3681:             }

3682:             u_data[i] += (relax_weight*res)/l1_norms[i];

0x4be5e0 STP	X29, X30, [SP, #960]!

0x4be5e4 ADD	X29, SP, #0

0x4be5e8 STP	X21, X22, [SP, #32]

0x4be5ec LDR	X21, [X0, #64]

0x4be5f0 STP	X19, X20, [SP, #16]

0x4be5f4 ORR	X19, XZR, X0

0x4be5f8 BL	40f6a0

0x4be5fc SBFM	X20, X0, #0, #31

0x4be600 BL	40f540

0x4be604 SDIV	X2, X21, X20

0x4be608 SBFM	X1, X0, #0, #31

0x4be60c MSUB	X0, X2, X20, X21

0x4be610 CMP	X1, X0

0x4be614 B.LT	4be994

(2581) 0x4be618 MADD	X1, X2, X1, X0

(2581) 0x4be61c ADD	X2, X2, X1

(2581) 0x4be620 CMP	X1, X2

(2581) 0x4be624 B.GE	4be984

(2581) 0x4be628 LDP	X4, X10, [X19, #16]

(2581) 0x4be62c LDP	X6, X16, [X19, #32]

(2581) 0x4be630 ADD	X30, X10, #8

(2581) 0x4be634 LDP	X9, X8, [X19, #48]

(2581) 0x4be638 ADD	X20, X16, #8

(2581) 0x4be63c LDP	X15, X17, [X19, #72]

(2581) 0x4be640 LDP	X5, X7, [X19, #88]

(2581) 0x4be644 LDR	X18, [X19]

(2581) 0x4be648 LDR	D6, [X19, #8]

(2581) 0x4be64c LDR	D4, [X19, #104]

(2581) 0x4be650 STR	X23, [SP, #48]

(2581) 0x4be654 B	4be664

  (2582) 0x4be658 ADD	X1, X1, #1

  (2582) 0x4be65c CMP	X2, X1

  (2582) 0x4be660 B.EQ	4be980

  (2582) 0x4be664 LDR	X0, [X10, X1,LSL #3]

  (2582) 0x4be668 LDR	D1, [X4, X0,LSL #3]

  (2582) 0x4be66c FCMP	D4, D1

  (2582) 0x4be670 B.EQ	4be658

  (2582) 0x4be674 LDR	X21, [X30, X1,LSL #3]

  (2582) 0x4be678 LDR	D0, [X17, X1,LSL #3]

  (2582) 0x4be67c CMP	X0, X21

  (2582) 0x4be680 B.GE	4be7e8

  (2582) 0x4be684 ORN	X3, XZR, X0

  (2582) 0x4be688 ADD	X11, X3, X21

  (2582) 0x4be68c ANDS	X12, X11, #4224

  (2582) 0x4be690 B.EQ	4be7b4

  (2582) 0x4be694 LDR	X13, [X6, X0,LSL #3]

  (2582) 0x4be698 ADD	X0, X0, #1

  (2582) 0x4be69c LDR	D2, [X5, X13,LSL #3]

  (2582) 0x4be6a0 FMSUB	D0, D2, D1, D0

  (2582) 0x4be6a4 LDR	D1, [X4, X0,LSL #3]

  (2582) 0x4be6a8 CMP	X12, #1

  (2582) 0x4be6ac B.EQ	4be7b4

  (2582) 0x4be6b0 CMP	X12, #2

  (2582) 0x4be6b4 B.EQ	4be728

  (2582) 0x4be6b8 CMP	X12, #3

  (2582) 0x4be6bc B.EQ	4be714

  (2582) 0x4be6c0 CMP	X12, #4

  (2582) 0x4be6c4 B.EQ	4be700

  (2582) 0x4be6c8 CMP	X12, #5

  (2582) 0x4be6cc B.EQ	4be6ec

  (2582) 0x4be6d0 CMP	X12, #6

  (2582) 0x4be6d4 B.NE	4be9a0

  (2582) 0x4be6d8 LDR	X22, [X6, X0,LSL #3]

  (2582) 0x4be6dc ADD	X0, X0, #1

  (2582) 0x4be6e0 LDR	D5, [X5, X22,LSL #3]

  (2582) 0x4be6e4 FMSUB	D0, D5, D1, D0

  (2582) 0x4be6e8 LDR	D1, [X4, X0,LSL #3]

  (2582) 0x4be6ec LDR	X23, [X6, X0,LSL #3]

  (2582) 0x4be6f0 ADD	X0, X0, #1

  (2582) 0x4be6f4 LDR	D7, [X5, X23,LSL #3]

  (2582) 0x4be6f8 FMSUB	D0, D7, D1, D0

  (2582) 0x4be6fc LDR	D1, [X4, X0,LSL #3]

  (2582) 0x4be700 LDR	X19, [X6, X0,LSL #3]

  (2582) 0x4be704 ADD	X0, X0, #1

  (2582) 0x4be708 LDR	D16, [X5, X19,LSL #3]

  (2582) 0x4be70c FMSUB	D0, D16, D1, D0

  (2582) 0x4be710 LDR	D1, [X4, X0,LSL #3]

  (2582) 0x4be714 LDR	X3, [X6, X0,LSL #3]

  (2582) 0x4be718 ADD	X0, X0, #1

  (2582) 0x4be71c LDR	D17, [X5, X3,LSL #3]

  (2582) 0x4be720 FMSUB	D0, D17, D1, D0

  (2582) 0x4be724 LDR	D1, [X4, X0,LSL #3]

  (2582) 0x4be728 LDR	X11, [X6, X0,LSL #3]

  (2582) 0x4be72c ADD	X0, X0, #1

  (2582) 0x4be730 LDR	D18, [X5, X11,LSL #3]

  (2582) 0x4be734 FMSUB	D0, D18, D1, D0

  (2582) 0x4be738 LDR	D1, [X4, X0,LSL #3]

  (2582) 0x4be73c B	4be7b4

    (2584) 0x4be740 LDR	X19, [X6, X3,LSL #3]

    (2584) 0x4be744 LDR	D19, [X4, X3,LSL #3]

    (2584) 0x4be748 LDR	X3, [X6, X14,LSL #3]

    (2584) 0x4be74c LDR	D1, [X5, X19,LSL #3]

    (2584) 0x4be750 LDR	D20, [X4, X14,LSL #3]

    (2584) 0x4be754 LDR	D21, [X5, X3,LSL #3]

    (2584) 0x4be758 LDR	X14, [X6, X13,LSL #3]

    (2584) 0x4be75c FMSUB	D22, D1, D19, D0

    (2584) 0x4be760 LDR	D23, [X4, X13,LSL #3]

    (2584) 0x4be764 LDR	X13, [X6, X12,LSL #3]

    (2584) 0x4be768 FMSUB	D24, D21, D20, D22

    (2584) 0x4be76c LDR	D25, [X5, X14,LSL #3]

    (2584) 0x4be770 LDR	D26, [X4, X12,LSL #3]

    (2584) 0x4be774 LDR	D27, [X5, X13,LSL #3]

    (2584) 0x4be778 LDR	X12, [X6, X11,LSL #3]

    (2584) 0x4be77c FMSUB	D28, D25, D23, D24

    (2584) 0x4be780 LDR	D29, [X4, X11,LSL #3]

    (2584) 0x4be784 LDR	X11, [X6, X23,LSL #3]

    (2584) 0x4be788 FMSUB	D30, D27, D26, D28

    (2584) 0x4be78c LDR	D31, [X5, X12,LSL #3]

    (2584) 0x4be790 LDR	D16, [X4, X23,LSL #3]

    (2584) 0x4be794 LDR	D5, [X5, X11,LSL #3]

    (2584) 0x4be798 LDR	X23, [X6, X22,LSL #3]

    (2584) 0x4be79c FMSUB	D2, D31, D29, D30

    (2584) 0x4be7a0 LDR	D3, [X4, X22,LSL #3]

    (2584) 0x4be7a4 LDR	D1, [X4, X0,LSL #3]

    (2584) 0x4be7a8 FMSUB	D7, D5, D16, D2

    (2584) 0x4be7ac LDR	D17, [X5, X23,LSL #3]

    (2584) 0x4be7b0 FMSUB	D0, D17, D3, D7

    (2584) 0x4be7b4 LDR	X19, [X6, X0,LSL #3]

    (2584) 0x4be7b8 ADD	X3, X0, #1

    (2584) 0x4be7bc ADD	X13, X0, #3

    (2584) 0x4be7c0 ADD	X12, X0, #4

    (2584) 0x4be7c4 ADD	X11, X0, #5

    (2584) 0x4be7c8 ADD	X23, X0, #6

    (2584) 0x4be7cc ADD	X22, X0, #7

    (2584) 0x4be7d0 ADD	X14, X0, #2

    (2584) 0x4be7d4 ADD	X0, X0, #8

    (2584) 0x4be7d8 LDR	D19, [X5, X19,LSL #3]

    (2584) 0x4be7dc FMSUB	D0, D19, D1, D0

    (2584) 0x4be7e0 CMP	X3, X21

    (2584) 0x4be7e4 B.NE	4be740

  (2582) 0x4be7e8 LDR	X14, [X16, X1,LSL #3]

  (2582) 0x4be7ec LDR	X19, [X20, X1,LSL #3]

  (2582) 0x4be7f0 CMP	X14, X19

  (2582) 0x4be7f4 B.GE	4be95c

  (2582) 0x4be7f8 SUB	X21, X19, X14

  (2582) 0x4be7fc ANDS	X0, X21, #4224

  (2582) 0x4be800 B.EQ	4be8b4

  (2582) 0x4be804 CMP	X0, #1

  (2582) 0x4be808 B.EQ	4be898

  (2582) 0x4be80c CMP	X0, #2

  (2582) 0x4be810 B.EQ	4be884

  (2582) 0x4be814 CMP	X0, #3

  (2582) 0x4be818 B.EQ	4be870

  (2582) 0x4be81c CMP	X0, #4

  (2582) 0x4be820 B.EQ	4be85c

  (2582) 0x4be824 CMP	X0, #5

  (2582) 0x4be828 B.EQ	4be848

  (2582) 0x4be82c CMP	X0, #6

  (2582) 0x4be830 B.NE	4be9b8

  (2582) 0x4be834 LDR	X12, [X8, X14,LSL #3]

  (2582) 0x4be838 LDR	D22, [X9, X14,LSL #3]

  (2582) 0x4be83c ADD	X14, X14, #1

  (2582) 0x4be840 LDR	D23, [X7, X12,LSL #3]

  (2582) 0x4be844 FMSUB	D0, D22, D23, D0

  (2582) 0x4be848 LDR	X11, [X8, X14,LSL #3]

  (2582) 0x4be84c LDR	D24, [X9, X14,LSL #3]

  (2582) 0x4be850 ADD	X14, X14, #1

  (2582) 0x4be854 LDR	D25, [X7, X11,LSL #3]

  (2582) 0x4be858 FMSUB	D0, D24, D25, D0

  (2582) 0x4be85c LDR	X23, [X8, X14,LSL #3]

  (2582) 0x4be860 LDR	D26, [X9, X14,LSL #3]

  (2582) 0x4be864 ADD	X14, X14, #1

  (2582) 0x4be868 LDR	D27, [X7, X23,LSL #3]

  (2582) 0x4be86c FMSUB	D0, D26, D27, D0

  (2582) 0x4be870 LDR	X22, [X8, X14,LSL #3]

  (2582) 0x4be874 LDR	D28, [X9, X14,LSL #3]

  (2582) 0x4be878 ADD	X14, X14, #1

  (2582) 0x4be87c LDR	D29, [X7, X22,LSL #3]

  (2582) 0x4be880 FMSUB	D0, D28, D29, D0

  (2582) 0x4be884 LDR	X3, [X8, X14,LSL #3]

  (2582) 0x4be888 LDR	D30, [X9, X14,LSL #3]

  (2582) 0x4be88c ADD	X14, X14, #1

  (2582) 0x4be890 LDR	D31, [X7, X3,LSL #3]

  (2582) 0x4be894 FMSUB	D0, D30, D31, D0

  (2582) 0x4be898 LDR	X21, [X8, X14,LSL #3]

  (2582) 0x4be89c LDR	D2, [X9, X14,LSL #3]

  (2582) 0x4be8a0 ADD	X14, X14, #1

  (2582) 0x4be8a4 LDR	D3, [X7, X21,LSL #3]

  (2582) 0x4be8a8 FMSUB	D0, D2, D3, D0

  (2582) 0x4be8ac CMP	X14, X19

  (2582) 0x4be8b0 B.EQ	4be95c

    (2583) 0x4be8b4 LDR	X11, [X8, X14,LSL #3]

    (2583) 0x4be8b8 ADD	X0, X14, #1

    (2583) 0x4be8bc ADD	X23, X14, #2

    (2583) 0x4be8c0 ADD	X13, X14, #3

    (2583) 0x4be8c4 ADD	X12, X14, #4

    (2583) 0x4be8c8 LDR	D5, [X9, X14,LSL #3]

    (2583) 0x4be8cc ADD	X22, X14, #5

    (2583) 0x4be8d0 LDR	X3, [X8, X0,LSL #3]

    (2583) 0x4be8d4 LDR	D7, [X7, X11,LSL #3]

    (2583) 0x4be8d8 LDR	D16, [X9, X0,LSL #3]

    (2583) 0x4be8dc ADD	X0, X14, #7

    (2583) 0x4be8e0 LDR	X21, [X8, X23,LSL #3]

    (2583) 0x4be8e4 FMSUB	D17, D5, D7, D0

    (2583) 0x4be8e8 LDR	D0, [X7, X3,LSL #3]

    (2583) 0x4be8ec LDR	D18, [X9, X23,LSL #3]

    (2583) 0x4be8f0 ADD	X23, X14, #6

    (2583) 0x4be8f4 ADD	X14, X14, #8

    (2583) 0x4be8f8 LDR	X11, [X8, X13,LSL #3]

    (2583) 0x4be8fc LDR	D19, [X7, X21,LSL #3]

    (2583) 0x4be900 FMSUB	D1, D16, D0, D17

    (2583) 0x4be904 LDR	D20, [X9, X13,LSL #3]

    (2583) 0x4be908 LDR	D22, [X7, X11,LSL #3]

    (2583) 0x4be90c LDR	X13, [X8, X12,LSL #3]

    (2583) 0x4be910 FMSUB	D23, D18, D19, D1

    (2583) 0x4be914 LDR	D21, [X9, X12,LSL #3]

    (2583) 0x4be918 LDR	X12, [X8, X22,LSL #3]

    (2583) 0x4be91c FMSUB	D24, D20, D22, D23

    (2583) 0x4be920 LDR	D26, [X7, X13,LSL #3]

    (2583) 0x4be924 LDR	D25, [X9, X22,LSL #3]

    (2583) 0x4be928 LDR	D27, [X7, X12,LSL #3]

    (2583) 0x4be92c LDR	X22, [X8, X23,LSL #3]

    (2583) 0x4be930 FMSUB	D28, D21, D26, D24

    (2583) 0x4be934 LDR	D29, [X9, X23,LSL #3]

    (2583) 0x4be938 LDR	X3, [X8, X0,LSL #3]

    (2583) 0x4be93c FMSUB	D31, D25, D27, D28

    (2583) 0x4be940 LDR	D30, [X7, X22,LSL #3]

    (2583) 0x4be944 LDR	D3, [X9, X0,LSL #3]

    (2583) 0x4be948 LDR	D2, [X7, X3,LSL #3]

    (2583) 0x4be94c FMSUB	D5, D29, D30, D31

    (2583) 0x4be950 FMSUB	D0, D3, D2, D5

    (2583) 0x4be954 CMP	X14, X19

    (2583) 0x4be958 B.NE	4be8b4

  (2582) 0x4be95c FMUL	D16, D6, D0

  (2582) 0x4be960 LDR	D7, [X18, X1,LSL #3]

  (2582) 0x4be964 LDR	D17, [X15, X1,LSL #3]

  (2582) 0x4be968 FDIV	D18, D16, D7

  (2582) 0x4be96c FADD	D0, D17, D18

  (2582) 0x4be970 STR	D0, [X15, X1,LSL #3]

  (2582) 0x4be974 ADD	X1, X1, #1

  (2582) 0x4be978 CMP	X2, X1

  (2582) 0x4be97c B.NE	4be664

(2581) 0x4be980 LDR	X23, [SP, #48]

(2581) 0x4be984 LDP	X19, X20, [SP, #16]

(2581) 0x4be988 LDP	X21, X22, [SP, #32]

(2581) 0x4be98c LDP	X29, X30, [SP], #64

(2581) 0x4be990 RET

(2581) 0x4be994 ADD	X2, X2, #1

(2581) 0x4be998 MOVZ	X0, #0

(2581) 0x4be99c B	4be618

  (2582) 0x4be9a0 LDR	X14, [X6, X0,LSL #3]

  (2582) 0x4be9a4 ADD	X0, X0, #1

  (2582) 0x4be9a8 LDR	D3, [X5, X14,LSL #3]

  (2582) 0x4be9ac FMSUB	D0, D3, D1, D0

  (2582) 0x4be9b0 LDR	D1, [X4, X0,LSL #3]

  (2582) 0x4be9b4 B	4be6d8

  (2582) 0x4be9b8 LDR	X13, [X8, X14,LSL #3]

  (2582) 0x4be9bc LDR	D20, [X9, X14,LSL #3]

  (2582) 0x4be9c0 ADD	X14, X14, #1

  (2582) 0x4be9c4 LDR	D21, [X7, X13,LSL #3]

  (2582) 0x4be9c8 FMSUB	D0, D20, D21, D0

  (2582) 0x4be9cc B	4be834

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	ams.c:3662-3682
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662,3669-3682.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 20.00 to 10.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4be5e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #960]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X0, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40f6a0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SBFM X20, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40f540 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SDIV X2, X21, X20	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MSUB X0, X2, X20, X21	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 4be994 <hypre_ParCSRRelaxThreads._omp_fn.1+0x3b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	ams.c:3662-3682
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662,3669-3682.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 48 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4be5e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #960]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X0, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40f6a0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SBFM X20, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40f540 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SDIV X2, X21, X20	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MSUB X0, X2, X20, X21	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 4be994 <hypre_ParCSRRelaxThreads._omp_fn.1+0x3b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼hypre_ParCSRRelaxThreads._omp_fn.1–	30.97	11.73
▼Loop 2581 - ams.c:3662-3682 - exec–	0	0
▼Loop 2582 - ams.c:3662-3682 - exec–	4.29	1.42
○Loop 2584 - ams.c:3672-3675 - exec	26.68	8.81
○Loop 2583 - ams.c:3677-3680 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code