OV - exec - Function hypre_ParCSRRelaxThreads._omp

	Function: hypre_ParCSRRelaxThreads._omp_fn.0	Module: exec	Source: ams.c:3655-3659	Coverage: 0.89%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3655 - 3659

--------------------------------------------------------------------------------

3655: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

3656: #endif

3657:       for (i = 0; i < n; i++)

3658:       {

3659:          Vtemp_data[i] = u_data[i];

0x4be470 STP	X29, X30, [SP, #976]!

0x4be474 ADD	X29, SP, #0

0x4be478 STR	X21, [SP, #32]

0x4be47c LDR	X21, [X0]

0x4be480 STP	X19, X20, [SP, #16]

0x4be484 ORR	X20, XZR, X0

0x4be488 BL	40f6a0

0x4be48c SBFM	X19, X0, #0, #31

0x4be490 BL	40f540

0x4be494 SDIV	X3, X21, X19

0x4be498 SBFM	X1, X0, #0, #31

0x4be49c MSUB	X2, X3, X19, X21

0x4be4a0 CMP	X1, X2

0x4be4a4 B.LT	4be5cc

(2579) 0x4be4a8 MADD	X13, X3, X1, X2

(2579) 0x4be4ac ADD	X11, X3, X13

(2579) 0x4be4b0 CMP	X13, X11

(2579) 0x4be4b4 B.GE	4be5bc

(2579) 0x4be4b8 SUB	X4, X11, X13

(2579) 0x4be4bc LDP	X12, X0, [X20, #8]

(2579) 0x4be4c0 ANDS	X5, X4, #4224

(2579) 0x4be4c4 B.EQ	4be554

(2579) 0x4be4c8 CMP	X5, #1

(2579) 0x4be4cc B.EQ	4be540

(2579) 0x4be4d0 CMP	X5, #2

(2579) 0x4be4d4 B.EQ	4be534

(2579) 0x4be4d8 CMP	X5, #3

(2579) 0x4be4dc B.EQ	4be528

(2579) 0x4be4e0 CMP	X5, #4

(2579) 0x4be4e4 B.EQ	4be51c

(2579) 0x4be4e8 CMP	X5, #5

(2579) 0x4be4ec B.EQ	4be510

(2579) 0x4be4f0 CMP	X5, #6

(2579) 0x4be4f4 B.EQ	4be504

(2579) 0x4be4f8 LDR	D0, [X12, X13,LSL #3]

(2579) 0x4be4fc STR	D0, [X0, X13,LSL #3]

(2579) 0x4be500 ADD	X13, X13, #1

(2579) 0x4be504 LDR	D1, [X12, X13,LSL #3]

(2579) 0x4be508 STR	D1, [X0, X13,LSL #3]

(2579) 0x4be50c ADD	X13, X13, #1

(2579) 0x4be510 LDR	D2, [X12, X13,LSL #3]

(2579) 0x4be514 STR	D2, [X0, X13,LSL #3]

(2579) 0x4be518 ADD	X13, X13, #1

(2579) 0x4be51c LDR	D3, [X12, X13,LSL #3]

(2579) 0x4be520 STR	D3, [X0, X13,LSL #3]

(2579) 0x4be524 ADD	X13, X13, #1

(2579) 0x4be528 LDR	D4, [X12, X13,LSL #3]

(2579) 0x4be52c STR	D4, [X0, X13,LSL #3]

(2579) 0x4be530 ADD	X13, X13, #1

(2579) 0x4be534 LDR	D5, [X12, X13,LSL #3]

(2579) 0x4be538 STR	D5, [X0, X13,LSL #3]

(2579) 0x4be53c ADD	X13, X13, #1

(2579) 0x4be540 LDR	D6, [X12, X13,LSL #3]

(2579) 0x4be544 STR	D6, [X0, X13,LSL #3]

(2579) 0x4be548 ADD	X13, X13, #1

(2579) 0x4be54c CMP	X11, X13

(2579) 0x4be550 B.EQ	4be5bc

  (2580) 0x4be554 LDR	D7, [X12, X13,LSL #3]

  (2580) 0x4be558 ADD	X14, X13, #1

  (2580) 0x4be55c ADD	X10, X13, #2

  (2580) 0x4be560 ADD	X9, X13, #3

  (2580) 0x4be564 ADD	X8, X13, #4

  (2580) 0x4be568 ADD	X7, X13, #5

  (2580) 0x4be56c ADD	X6, X13, #6

  (2580) 0x4be570 ADD	X15, X13, #7

  (2580) 0x4be574 STR	D7, [X0, X13,LSL #3]

  (2580) 0x4be578 ADD	X13, X13, #8

  (2580) 0x4be57c LDR	D16, [X12, X14,LSL #3]

  (2580) 0x4be580 STR	D16, [X0, X14,LSL #3]

  (2580) 0x4be584 LDR	D17, [X12, X10,LSL #3]

  (2580) 0x4be588 STR	D17, [X0, X10,LSL #3]

  (2580) 0x4be58c LDR	D18, [X12, X9,LSL #3]

  (2580) 0x4be590 STR	D18, [X0, X9,LSL #3]

  (2580) 0x4be594 LDR	D19, [X12, X8,LSL #3]

  (2580) 0x4be598 STR	D19, [X0, X8,LSL #3]

  (2580) 0x4be59c LDR	D20, [X12, X7,LSL #3]

  (2580) 0x4be5a0 STR	D20, [X0, X7,LSL #3]

  (2580) 0x4be5a4 LDR	D21, [X12, X6,LSL #3]

  (2580) 0x4be5a8 STR	D21, [X0, X6,LSL #3]

  (2580) 0x4be5ac LDR	D22, [X12, X15,LSL #3]

  (2580) 0x4be5b0 STR	D22, [X0, X15,LSL #3]

  (2580) 0x4be5b4 CMP	X11, X13

  (2580) 0x4be5b8 B.NE	4be554

(2579) 0x4be5bc LDP	X19, X20, [SP, #16]

(2579) 0x4be5c0 LDR	X21, [SP, #32]

(2579) 0x4be5c4 LDP	X29, X30, [SP], #48

(2579) 0x4be5c8 RET

(2579) 0x4be5cc ADD	X3, X3, #1

(2579) 0x4be5d0 MOVZ	X2, #0

(2579) 0x4be5d4 B	4be4a8

0x4be5d8 HINT	#0

0x4be5dc HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	ams.c:3655-3659
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3655-3659.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 20.00 to 10.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	16
loop length	64
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4be470

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f6a0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f540 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SDIV X3, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MSUB X2, X3, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X1, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4be5cc <hypre_ParCSRRelaxThreads._omp_fn.0+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Source file and lines	ams.c:3655-3659
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3655-3659.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	16
loop length	64
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4be470

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f6a0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f540 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SDIV X3, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MSUB X2, X3, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X1, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4be5cc <hypre_ParCSRRelaxThreads._omp_fn.0+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼hypre_ParCSRRelaxThreads._omp_fn.0–	0.89	0.34
▼Loop 2579 - ams.c:3655-3659 - exec–	0	0
○Loop 2580 - ams.c:3659-3659 - exec	0.89	0.29

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code