OV - exec - Function hypre_BoomerAMGCreate2ndS._omp

	Function: hypre_BoomerAMGCreate2ndS._omp_fn.0	Module: exec	Source: par_strength.c:1253-1278	Coverage: 0.08%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 1253 - 1278

--------------------------------------------------------------------------------

1253: #pragma omp parallel private(i)

1254: #endif

1255:    {

1256:       HYPRE_Int num_coarse_private = 0;

1257:

1258:       HYPRE_Int i_begin, i_end;

1259:       hypre_GetSimpleThreadPartition(&i_begin, &i_end, num_cols_diag_S);

1260:

1261:       for (i = i_begin; i < i_end; i++)

1262:       {

1263:          if (CF_marker[i] > 0) num_coarse_private++;

1264:       }

1265:

1266:       hypre_prefix_sum(&num_coarse_private, &num_coarse, num_coarse_prefix_sum);

1267:

1268:       for (i = i_begin; i < i_end; i++)

1269:       {

1270:          if (CF_marker[i] > 0)

1271:          {

1272:             fine_to_coarse[i] = num_coarse_private;

1273:             coarse_to_fine[num_coarse_private] = i;

1274:             num_coarse_private++;

1275:          }

1276:          else

1277:          {

1278:             fine_to_coarse[i] = -1;

0x4acc60 ADRP	X3,

0x4acc64 STP	X29, X30, [SP, #928]!

0x4acc68 ADD	X29, SP, #0

0x4acc6c ADD	X1, SP, #80

0x4acc70 LDR	X5, [X3, #3848]

0x4acc74 STP	X21, X22, [SP, #32]

0x4acc78 ORR	X21, XZR, X0

0x4acc7c ADD	X0, SP, #72

0x4acc80 STP	X19, X20, [SP, #16]

0x4acc84 LDP	X19, X2, [X21]

0x4acc88 LDR	X20, [X21, #16]

0x4acc8c LDR	X22, [X21, #40]

0x4acc90 STR	X23, [SP, #48]

0x4acc94 LDR	X4, [X5]

0x4acc98 STR	X4, [SP, #88]

0x4acc9c MOVZ	X4, #0

0x4acca0 STR	XZR, [SP, #64]

0x4acca4 LDR	X23, [X21, #32]

0x4acca8 BL	5195a0

0x4accac LDP	X1, X4, [SP, #72]

0x4accb0 CMP	X1, X4

0x4accb4 B.GE	4ace78

0x4accb8 ADD	X5, X19, X1,LSL #3

0x4accbc MOVZ	W0, #0

0x4accc0 ADD	X6, X19, X4,LSL #3

0x4accc4 SUB	X2, X6, X5

0x4accc8 SUB	X7, X2, #8

0x4acccc LDR	X2, [SP, #64]

0x4accd0 UBFM	X8, X7, #3, #63

0x4accd4 ADD	X9, X8, #1

0x4accd8 ANDS	X10, X9, #4224

0x4accdc B.EQ	4acdc0

0x4acce0 CMP	X10, #1

0x4acce4 B.EQ	4acda0

0x4acce8 CMP	X10, #2

0x4accec B.EQ	4acd88

0x4accf0 CMP	X10, #3

0x4accf4 B.EQ	4acd70

0x4accf8 CMP	X10, #4

0x4accfc B.EQ	4acd58

0x4acd00 CMP	X10, #5

0x4acd04 B.EQ	4acd40

0x4acd08 CMP	X10, #6

0x4acd0c B.EQ	4acd28

0x4acd10 LDR	X11, [X5]

0x4acd14 CMP	X11, #0

0x4acd18 B.LE	4acd24

0x4acd1c ADD	X2, X2, #1

0x4acd20 MOVZ	W0, #1

0x4acd24 ADD	X5, X5, #8

0x4acd28 LDR	X12, [X5]

0x4acd2c CMP	X12, #0

0x4acd30 B.LE	4acd3c

0x4acd34 ADD	X2, X2, #1

0x4acd38 MOVZ	W0, #1

0x4acd3c ADD	X5, X5, #8

0x4acd40 LDR	X13, [X5]

0x4acd44 CMP	X13, #0

0x4acd48 B.LE	4acd54

0x4acd4c ADD	X2, X2, #1

0x4acd50 MOVZ	W0, #1

0x4acd54 ADD	X5, X5, #8

0x4acd58 LDR	X14, [X5]

0x4acd5c CMP	X14, #0

0x4acd60 B.LE	4acd6c

0x4acd64 ADD	X2, X2, #1

0x4acd68 MOVZ	W0, #1

0x4acd6c ADD	X5, X5, #8

0x4acd70 LDR	X15, [X5]

0x4acd74 CMP	X15, #0

0x4acd78 B.LE	4acd84

0x4acd7c ADD	X2, X2, #1

0x4acd80 MOVZ	W0, #1

0x4acd84 ADD	X5, X5, #8

0x4acd88 LDR	X16, [X5]

0x4acd8c CMP	X16, #0

0x4acd90 B.LE	4acd9c

0x4acd94 ADD	X2, X2, #1

0x4acd98 MOVZ	W0, #1

0x4acd9c ADD	X5, X5, #8

0x4acda0 LDR	X17, [X5]

0x4acda4 CMP	X17, #0

0x4acda8 B.LE	4acdb4

0x4acdac ADD	X2, X2, #1

0x4acdb0 MOVZ	W0, #1

0x4acdb4 ADD	X5, X5, #8

0x4acdb8 CMP	X6, X5

0x4acdbc B.EQ	4ace70

(2347) 0x4acdc0 LDR	X18, [X5]

(2347) 0x4acdc4 CMP	X18, #0

(2347) 0x4acdc8 B.LE	4acdd4

(2347) 0x4acdcc ADD	X2, X2, #1

(2347) 0x4acdd0 MOVZ	W0, #1

(2347) 0x4acdd4 LDR	X30, [X5, #8]

(2347) 0x4acdd8 ADD	X5, X5, #8

(2347) 0x4acddc CMP	X30, #0

(2347) 0x4acde0 B.LE	4acdec

(2347) 0x4acde4 ADD	X2, X2, #1

(2347) 0x4acde8 MOVZ	W0, #1

(2347) 0x4acdec LDR	X3, [X5, #8]

(2347) 0x4acdf0 CMP	X3, #0

(2347) 0x4acdf4 B.LE	4ace00

(2347) 0x4acdf8 ADD	X2, X2, #1

(2347) 0x4acdfc MOVZ	W0, #1

(2347) 0x4ace00 LDR	X1, [X5, #16]

(2347) 0x4ace04 CMP	X1, #0

(2347) 0x4ace08 B.LE	4ace14

(2347) 0x4ace0c ADD	X2, X2, #1

(2347) 0x4ace10 MOVZ	W0, #1

(2347) 0x4ace14 LDR	X4, [X5, #24]

(2347) 0x4ace18 CMP	X4, #0

(2347) 0x4ace1c B.LE	4ace28

(2347) 0x4ace20 ADD	X2, X2, #1

(2347) 0x4ace24 MOVZ	W0, #1

(2347) 0x4ace28 LDR	X7, [X5, #32]

(2347) 0x4ace2c CMP	X7, #0

(2347) 0x4ace30 B.LE	4ace3c

(2347) 0x4ace34 ADD	X2, X2, #1

(2347) 0x4ace38 MOVZ	W0, #1

(2347) 0x4ace3c LDR	X8, [X5, #40]

(2347) 0x4ace40 CMP	X8, #0

(2347) 0x4ace44 B.LE	4ace50

(2347) 0x4ace48 ADD	X2, X2, #1

(2347) 0x4ace4c MOVZ	W0, #1

(2347) 0x4ace50 LDR	X9, [X5, #48]

(2347) 0x4ace54 CMP	X9, #0

(2347) 0x4ace58 B.LE	4ace64

(2347) 0x4ace5c ADD	X2, X2, #1

(2347) 0x4ace60 MOVZ	W0, #1

(2347) 0x4ace64 ADD	X5, X5, #56

(2347) 0x4ace68 CMP	X6, X5

(2347) 0x4ace6c B.NE	4acdc0

0x4ace70 CBZ	W0, 4ace78

0x4ace74 STR	X2, [SP, #64]

0x4ace78 ORR	X2, XZR, X23

0x4ace7c ADD	X0, SP, #64

0x4ace80 LDR	X1, [X21, #24]

0x4ace84 BL	51a560

0x4ace88 LDP	X4, X6, [SP, #72]

0x4ace8c CMP	X4, X6

0x4ace90 B.GE	4acfa4

0x4ace94 SUB	X10, X6, X4

0x4ace98 MOVN	X11, #0

0x4ace9c LDR	X1, [SP, #64]

0x4acea0 ANDS	X12, X10, #4224

0x4acea4 B.EQ	4ad0b0

0x4acea8 CMP	X12, #1

0x4aceac B.EQ	4acf80

0x4aceb0 CMP	X12, #2

0x4aceb4 B.EQ	4acf64

0x4aceb8 CMP	X12, #3

0x4acebc B.EQ	4acf48

0x4acec0 CMP	X12, #4

0x4acec4 B.EQ	4acf2c

0x4acec8 CMP	X12, #5

0x4acecc B.EQ	4acf10

0x4aced0 CMP	X12, #6

0x4aced4 B.EQ	4acef4

0x4aced8 LDR	X13, [X19, X4,LSL #3]

0x4acedc CMP	X13, #0

0x4acee0 B.LE	4ad194

0x4acee4 STR	X1, [X20, X4,LSL #3]

0x4acee8 STR	X4, [X22, X1,LSL #3]

0x4aceec ADD	X1, X1, #1

0x4acef0 ADD	X4, X4, #1

0x4acef4 LDR	X14, [X19, X4,LSL #3]

0x4acef8 CMP	X14, #0

0x4acefc B.LE	4ad17c

0x4acf00 STR	X1, [X20, X4,LSL #3]

0x4acf04 STR	X4, [X22, X1,LSL #3]

0x4acf08 ADD	X1, X1, #1

0x4acf0c ADD	X4, X4, #1

0x4acf10 LDR	X15, [X19, X4,LSL #3]

0x4acf14 CMP	X15, #0

0x4acf18 B.LE	4ad170

0x4acf1c STR	X1, [X20, X4,LSL #3]

0x4acf20 STR	X4, [X22, X1,LSL #3]

0x4acf24 ADD	X1, X1, #1

0x4acf28 ADD	X4, X4, #1

0x4acf2c LDR	X16, [X19, X4,LSL #3]

0x4acf30 CMP	X16, #0

0x4acf34 B.LE	4ad188

0x4acf38 STR	X1, [X20, X4,LSL #3]

0x4acf3c STR	X4, [X22, X1,LSL #3]

0x4acf40 ADD	X1, X1, #1

0x4acf44 ADD	X4, X4, #1

0x4acf48 LDR	X17, [X19, X4,LSL #3]

0x4acf4c CMP	X17, #0

0x4acf50 B.LE	4ad164

0x4acf54 STR	X1, [X20, X4,LSL #3]

0x4acf58 STR	X4, [X22, X1,LSL #3]

0x4acf5c ADD	X1, X1, #1

0x4acf60 ADD	X4, X4, #1

0x4acf64 LDR	X18, [X19, X4,LSL #3]

0x4acf68 CMP	X18, #0

0x4acf6c B.LE	4ad158

0x4acf70 STR	X1, [X20, X4,LSL #3]

0x4acf74 STR	X4, [X22, X1,LSL #3]

0x4acf78 ADD	X1, X1, #1

0x4acf7c ADD	X4, X4, #1

0x4acf80 LDR	X30, [X19, X4,LSL #3]

0x4acf84 CMP	X30, #0

0x4acf88 B.LE	4ad150

0x4acf8c STR	X1, [X20, X4,LSL #3]

0x4acf90 STR	X4, [X22, X1,LSL #3]

0x4acf94 ADD	X1, X1, #1

0x4acf98 ADD	X4, X4, #1

0x4acf9c CMP	X4, X6

0x4acfa0 B.NE	4ad0b0

(2337) 0x4acfa4 ADRP	X19,

(2337) 0x4acfa8 LDR	X20, [X19, #3848]

(2337) 0x4acfac LDR	X2, [SP, #88]

(2337) 0x4acfb0 LDR	X1, [X20]

(2337) 0x4acfb4 SUBS	X2, X2, X1

(2337) 0x4acfb8 MOVZ	X1, #0

(2337) 0x4acfbc B.NE	4ad1a0

(2337) 0x4acfc0 LDP	X19, X20, [SP, #16]

(2337) 0x4acfc4 LDP	X21, X22, [SP, #32]

(2337) 0x4acfc8 LDR	X23, [SP, #48]

(2337) 0x4acfcc LDP	X29, X30, [SP], #96

(2337) 0x4acfd0 RET

  (2338) 0x4acfd4 STR	X1, [X20, X4,LSL #3]

  (2338) 0x4acfd8 STR	X4, [X22, X1,LSL #3]

  (2338) 0x4acfdc ADD	X4, X4, #1

  (2338) 0x4acfe0 ADD	X1, X1, #1

  (2338) 0x4acfe4 LDR	X7, [X19, X4,LSL #3]

  (2338) 0x4acfe8 CMP	X7, #0

  (2338) 0x4acfec B.LE	4ad0d0

    (2339) 0x4acff0 ADD	X8, X4, #1

    (2339) 0x4acff4 STR	X1, [X20, X4,LSL #3]

    (2339) 0x4acff8 STR	X4, [X22, X1,LSL #3]

    (2339) 0x4acffc ADD	X1, X1, #1

    (2339) 0x4ad000 LDR	X9, [X19, X8,LSL #3]

    (2339) 0x4ad004 CMP	X9, #0

    (2339) 0x4ad008 B.LE	4ad0e4

  (2345) 0x4ad00c ADD	X2, X4, #2

  (2345) 0x4ad010 STR	X1, [X20, X8,LSL #3]

  (2345) 0x4ad014 STR	X8, [X22, X1,LSL #3]

  (2345) 0x4ad018 ADD	X1, X1, #1

  (2345) 0x4ad01c LDR	X0, [X19, X2,LSL #3]

  (2345) 0x4ad020 CMP	X0, #0

  (2345) 0x4ad024 B.LE	4ad0f8

    (2339) 0x4ad028 ADD	X21, X4, #3

    (2339) 0x4ad02c STR	X1, [X20, X2,LSL #3]

    (2339) 0x4ad030 STR	X2, [X22, X1,LSL #3]

    (2339) 0x4ad034 ADD	X1, X1, #1

    (2339) 0x4ad038 LDR	X5, [X19, X21,LSL #3]

    (2339) 0x4ad03c CMP	X5, #0

    (2339) 0x4ad040 B.LE	4ad10c

  (2343) 0x4ad044 ADD	X23, X4, #4

  (2343) 0x4ad048 STR	X1, [X20, X21,LSL #3]

  (2343) 0x4ad04c STR	X21, [X22, X1,LSL #3]

  (2343) 0x4ad050 ADD	X1, X1, #1

  (2343) 0x4ad054 LDR	X10, [X19, X23,LSL #3]

  (2343) 0x4ad058 CMP	X10, #0

  (2343) 0x4ad05c B.LE	4ad120

    (2339) 0x4ad060 ADD	X12, X4, #5

    (2339) 0x4ad064 STR	X1, [X20, X23,LSL #3]

    (2339) 0x4ad068 STR	X23, [X22, X1,LSL #3]

    (2339) 0x4ad06c ADD	X1, X1, #1

    (2339) 0x4ad070 LDR	X13, [X19, X12,LSL #3]

    (2339) 0x4ad074 CMP	X13, #0

    (2339) 0x4ad078 B.LE	4ad134

  (2341) 0x4ad07c ADD	X14, X4, #6

  (2341) 0x4ad080 STR	X1, [X20, X12,LSL #3]

  (2341) 0x4ad084 STR	X12, [X22, X1,LSL #3]

  (2341) 0x4ad088 ADD	X1, X1, #1

  (2341) 0x4ad08c LDR	X15, [X19, X14,LSL #3]

  (2341) 0x4ad090 CMP	X15, #0

  (2341) 0x4ad094 B.LE	4ad148

    (2339) 0x4ad098 STR	X1, [X20, X14,LSL #3]

    (2339) 0x4ad09c STR	X14, [X22, X1,LSL #3]

    (2339) 0x4ad0a0 ADD	X1, X1, #1

    (2339) 0x4ad0a4 ADD	X4, X4, #7

    (2339) 0x4ad0a8 CMP	X4, X6

    (2339) 0x4ad0ac B.EQ	4acfa4

    (2339) 0x4ad0b0 LDR	X3, [X19, X4,LSL #3]

    (2339) 0x4ad0b4 CMP	X3, #0

    (2339) 0x4ad0b8 B.GT	4acfd4

    (2339) 0x4ad0bc STR	X11, [X20, X4,LSL #3]

    (2339) 0x4ad0c0 ADD	X4, X4, #1

    (2339) 0x4ad0c4 LDR	X7, [X19, X4,LSL #3]

    (2339) 0x4ad0c8 CMP	X7, #0

    (2339) 0x4ad0cc B.GT	4acff0

  (2346) 0x4ad0d0 ADD	X8, X4, #1

  (2346) 0x4ad0d4 STR	X11, [X20, X4,LSL #3]

  (2346) 0x4ad0d8 LDR	X9, [X19, X8,LSL #3]

  (2346) 0x4ad0dc CMP	X9, #0

  (2346) 0x4ad0e0 B.GT	4ad00c

    (2339) 0x4ad0e4 ADD	X2, X4, #2

    (2339) 0x4ad0e8 STR	X11, [X20, X8,LSL #3]

    (2339) 0x4ad0ec LDR	X0, [X19, X2,LSL #3]

    (2339) 0x4ad0f0 CMP	X0, #0

    (2339) 0x4ad0f4 B.GT	4ad028

  (2344) 0x4ad0f8 ADD	X21, X4, #3

  (2344) 0x4ad0fc STR	X11, [X20, X2,LSL #3]

  (2344) 0x4ad100 LDR	X5, [X19, X21,LSL #3]

  (2344) 0x4ad104 CMP	X5, #0

  (2344) 0x4ad108 B.GT	4ad044

    (2339) 0x4ad10c ADD	X23, X4, #4

    (2339) 0x4ad110 STR	X11, [X20, X21,LSL #3]

    (2339) 0x4ad114 LDR	X10, [X19, X23,LSL #3]

    (2339) 0x4ad118 CMP	X10, #0

    (2339) 0x4ad11c B.GT	4ad060

  (2342) 0x4ad120 ADD	X12, X4, #5

  (2342) 0x4ad124 STR	X11, [X20, X23,LSL #3]

  (2342) 0x4ad128 LDR	X13, [X19, X12,LSL #3]

  (2342) 0x4ad12c CMP	X13, #0

  (2342) 0x4ad130 B.GT	4ad07c

    (2339) 0x4ad134 ADD	X14, X4, #6

    (2339) 0x4ad138 STR	X11, [X20, X12,LSL #3]

    (2339) 0x4ad13c LDR	X15, [X19, X14,LSL #3]

    (2339) 0x4ad140 CMP	X15, #0

    (2339) 0x4ad144 B.GT	4ad098

  (2340) 0x4ad148 STR	X11, [X20, X14,LSL #3]

  (2340) 0x4ad14c B	4ad0a4

0x4ad150 STR	X11, [X20, X4,LSL #3]

0x4ad154 B	4acf98

0x4ad158 STR	X11, [X20, X4,LSL #3]

0x4ad15c ADD	X4, X4, #1

0x4ad160 B	4acf80

0x4ad164 STR	X11, [X20, X4,LSL #3]

0x4ad168 ADD	X4, X4, #1

0x4ad16c B	4acf64

0x4ad170 STR	X11, [X20, X4,LSL #3]

0x4ad174 ADD	X4, X4, #1

0x4ad178 B	4acf2c

0x4ad17c STR	X11, [X20, X4,LSL #3]

0x4ad180 ADD	X4, X4, #1

0x4ad184 B	4acf10

0x4ad188 STR	X11, [X20, X4,LSL #3]

0x4ad18c ADD	X4, X4, #1

0x4ad190 B	4acf48

0x4ad194 STR	X11, [X20, X4,LSL #3]

0x4ad198 ADD	X4, X4, #1

0x4ad19c B	4acef4

0x4ad1a0 BL	40f2e0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	par_strength.c:1253-1278
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1253-1278.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 23.50 to 4.44 cycles (5.30x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 23.50 to 1.50 cycles (15.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 224 bytes. The binary function is storing 248 bytes.

General properties

nb instructions	186
loop length	744
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

23.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	21.50	21.50	23.50	23.50	23.50	23.50	0.00	0.00	0.00	0.00	17.67	17.67	17.67	14.00	14.00
cycles	21.50	21.50	23.50	23.50	23.50	23.50	0.00	0.00	0.00	0.00	17.67	17.67	17.67	14.00	14.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.25
Overall L1	23.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.50 cycles. At this rate:

9% of peak load performance is reached (9.53 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
21% of peak store performance is reached (10.55 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4acc60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADRP X3, <54fc60>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #928]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, SP, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X5, [X3, #3848]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, SP, #72	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X19, X2, [X21]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X20, [X21, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X21, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X23, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X4, [SP, #88]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ X4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X23, [X21, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 5195a0 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDP X1, X4, [SP, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X1, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4ace78 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x218>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X5, X19, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X6, X19, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X2, X6, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X7, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X2, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X8, X7, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X9, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ANDS X10, X9, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4acdc0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4acda0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4acd88 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4acd70 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X10, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4acd58 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X10, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4acd40 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X10, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4acd28 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4acd24 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X5, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X12, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4acd3c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X5, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X13, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4acd54 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X5, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X14, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4acd6c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X5, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X15, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4acd84 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X5, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X16, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4acd9c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X5, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X17, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X17, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4acdb4 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X5, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X6, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4ace70 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W0, 4ace78 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x218>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X2, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X2, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X1, [X21, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 51a560 <hypre_prefix_sum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDP X4, X6, [SP, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X4, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4acfa4 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x344>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB X10, X6, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVN X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X1, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ANDS X12, X10, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4ad0b0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4acf80 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x320>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X12, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4acf64 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X12, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4acf48 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X12, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4acf2c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X12, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4acf10 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X12, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4acef4 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x294>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4ad194 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x534>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X1, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X14, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4ad17c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x51c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X1, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X15, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4ad170 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x510>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X1, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X16, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4ad188 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x528>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X1, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X17, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X17, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4ad164 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x504>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X1, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X18, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X18, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4ad158 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X1, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X30, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X30, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4ad150 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X1, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X4, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 4ad0b0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X11, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4acf98 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x338>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X11, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 4acf80 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x320>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X11, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 4acf64 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X11, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 4acf2c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X11, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 4acf10 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X11, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 4acf48 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X11, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 4acef4 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x294>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
BL 40f2e0 <@plt_start@+0xf0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Source file and lines	par_strength.c:1253-1278
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1253-1278.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 23.50 to 1.50 cycles (15.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 224 bytes. The binary function is storing 248 bytes.

General properties

nb instructions	186
loop length	744
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

23.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	21.50	21.50	23.50	23.50	23.50	23.50	0.00	0.00	0.00	0.00	17.67	17.67	17.67	14.00	14.00
cycles	21.50	21.50	23.50	23.50	23.50	23.50	0.00	0.00	0.00	0.00	17.67	17.67	17.67	14.00	14.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	23.25
Overall L1	23.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.50 cycles. At this rate:

9% of peak load performance is reached (9.53 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
21% of peak store performance is reached (10.55 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4acc60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADRP X3, <54fc60>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #928]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, SP, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X5, [X3, #3848]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, SP, #72	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X19, X2, [X21]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X20, [X21, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X21, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X23, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X4, [SP, #88]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ X4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR XZR, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X23, [X21, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 5195a0 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDP X1, X4, [SP, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X1, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4ace78 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x218>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X5, X19, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X6, X19, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X2, X6, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X7, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X2, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X8, X7, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X9, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ANDS X10, X9, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4acdc0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4acda0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4acd88 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4acd70 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X10, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4acd58 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X10, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4acd40 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X10, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4acd28 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4acd24 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X5, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X12, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4acd3c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X5, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X13, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4acd54 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X5, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X14, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4acd6c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X5, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X15, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4acd84 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X5, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X16, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4acd9c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X5, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X17, [X5]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X17, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4acdb4 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X5, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X6, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4ace70 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W0, 4ace78 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x218>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X2, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X2, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X1, [X21, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 51a560 <hypre_prefix_sum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDP X4, X6, [SP, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X4, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4acfa4 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x344>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SUB X10, X6, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVN X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X1, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ANDS X12, X10, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4ad0b0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4acf80 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x320>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X12, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4acf64 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X12, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4acf48 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X12, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4acf2c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X12, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4acf10 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP X12, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4acef4 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x294>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4ad194 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x534>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X1, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X14, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4ad17c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x51c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X1, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X15, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4ad170 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x510>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X1, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X16, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4ad188 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x528>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X1, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X17, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X17, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4ad164 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x504>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X1, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X18, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X18, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4ad158 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X1, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X30, [X19, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X30, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 4ad150 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x4f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X1, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X4, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.NE 4ad0b0 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X11, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4acf98 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x338>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X11, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 4acf80 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x320>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X11, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 4acf64 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X11, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 4acf2c <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X11, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 4acf10 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X11, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 4acf48 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x2e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X11, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 4acef4 <hypre_BoomerAMGCreate2ndS._omp_fn.0+0x294>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
BL 40f2e0 <@plt_start@+0xf0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCreate2ndS._omp_fn.0–	0.08	0.03
▼Loop 2337 - par_strength.c:1253-1278 - exec–	0	0
○Loop 2341 - par_strength.c:1268-1274 - exec	0.01	0.01
○Loop 2345 - par_strength.c:1268-1274 - exec	0	0
○Loop 2342 - par_strength.c:1268-1278 - exec	0	0
▼Loop 2338 - par_strength.c:1268-1278 - exec–	0	0
○Loop 2339 - par_strength.c:1268-1278 - exec	0.07	0.02
○Loop 2340 - par_strength.c:1278-1278 - exec	0	0
○Loop 2346 - par_strength.c:1268-1278 - exec	0	0
○Loop 2343 - par_strength.c:1268-1274 - exec	0	0.01
○Loop 2344 - par_strength.c:1268-1278 - exec	0	0.01
○Loop 2347 - par_strength.c:1261-1263 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code