OV - exec - Function hypre_BoomerAMGCreate2ndS._omp

	Function: hypre_BoomerAMGCreate2ndS._omp_fn.7	Module: exec	Source: par_strength.c:1668-2230 [...]	Coverage: 1.84%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 1668 - 2230

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1668: #pragma omp parallel private(i1,i2,i3,jj1,jj2,index)

1669: #endif

1670:    {

1671:       HYPRE_Int my_thread_num = hypre_GetThreadNum();

1672:

1673:       HYPRE_Int i1_begin, i1_end;

1674:       hypre_GetSimpleThreadPartition(&i1_begin, &i1_end, num_cols_diag_S);

1675:

1676:       HYPRE_Int *C_temp_diag_j = NULL, *C_temp_offd_j = NULL;

1677:       HYPRE_Int *C_temp_diag_data = NULL, *C_temp_offd_data = NULL;

1678:

1679:       if (num_paths > 1)

1680:       {

1681:          C_temp_diag_j = C_temp_diag_j_array + num_coarse*my_thread_num;

1682:          C_temp_offd_j = C_temp_offd_j_array + num_cols_offd_C*my_thread_num;

1683:

1684:          C_temp_diag_data = C_temp_diag_data_array + num_coarse*my_thread_num;

1685:          C_temp_offd_data = C_temp_offd_data_array + num_cols_offd_C*my_thread_num;

1686:       }

1687:

1688:       HYPRE_Int *S_marker = NULL, *S_marker_offd = NULL;

1689:       if (num_coarse) S_marker = S_marker_array + num_coarse*my_thread_num;

1690:       if (num_cols_offd_C) S_marker_offd = S_marker_offd_array + num_cols_offd_C*my_thread_num;

1691:       for (i1 = 0; i1 < num_coarse; i1++)

1692:       {

1693:          S_marker[i1] = -1;

1694:       }

1695:       for (i1 = 0; i1 < num_cols_offd_C; i1++)

1696:       {

1697:          S_marker_offd[i1] = -1;

1698:       }

1699:

1700:       // These two counters are for before filtering by num_paths

1701:       HYPRE_Int jj_count_diag = 0;

1702:       HYPRE_Int jj_count_offd = 0;

1703:

1704:       // These two counters are for after filtering by num_paths

1705:       HYPRE_Int num_nonzeros_diag = 0;

1706:       HYPRE_Int num_nonzeros_offd = 0;

1707:

1708:       HYPRE_Int ic_begin = num_coarse_prefix_sum[my_thread_num];

1709:       HYPRE_Int ic_end = num_coarse_prefix_sum[my_thread_num + 1];

1710:       HYPRE_Int ic;

1711:

1712:       if (num_paths == 1)

1713:       {

1714:          for (ic = ic_begin; ic < ic_end; ic++)

[...]

1720:              HYPRE_Int i1 = coarse_to_fine[ic];

1721:

1722:              HYPRE_Int jj_row_begin_diag = num_nonzeros_diag;

1723:              HYPRE_Int jj_row_begin_offd = num_nonzeros_offd;

1724:

1725:              C_diag_i[ic] = num_nonzeros_diag;

1726:              if (num_cols_offd_C)

1727:              {

1728:                 C_offd_i[ic] = num_nonzeros_offd;

1729:              }

1730:

1731:              for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++)

1732:              {

1733:                  i2 = S_diag_j[jj1];

1734:                  if (CF_marker[i2] > 0)

1735:                  {

1736:                     index = fine_to_coarse[i2];

1737:                     if (S_marker[index] < jj_row_begin_diag)

1738:                     {

1739:                        S_marker[index] = num_nonzeros_diag;

1740:                        num_nonzeros_diag++;

1741:                     }

1742:                  }

1743:                  for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++)

1744:                  {

1745:                     i3 = S_diag_j[jj2];

1746:                     if (CF_marker[i3] > 0)

1747:                     {

1748:                        index = fine_to_coarse[i3];

1749:                        if (index != ic && S_marker[index] < jj_row_begin_diag)

1750:                        {

1751:                           S_marker[index] = num_nonzeros_diag;

1752:                           num_nonzeros_diag++;

1753:                        }

1754:                     }

1755:                  }

1756:                  for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++)

1757:                  {

1758:                     i3 = S_offd_j[jj2];

1759:                     if (CF_marker_offd[i3] > 0)

1760:                     {

1761:                        index = map_S_to_C[i3];

1762:                        if (S_marker_offd[index] < jj_row_begin_offd)

1763:                        {

1764:                           S_marker_offd[index] = num_nonzeros_offd;

1765:                           num_nonzeros_offd++;

1766:                        }

1767:                     }

1768:                  }

1769:              }

1770:              for (jj1 = S_offd_i[i1]; jj1 < S_offd_i[i1+1]; jj1++)

1771:              {

1772:                  i2 = S_offd_j[jj1];

1773:                  if (CF_marker_offd[i2] > 0)

1774:                  {

1775:                     index = map_S_to_C[i2];

1776:                     if (S_marker_offd[index] < jj_row_begin_offd)

1777:                     {

1778:                        S_marker_offd[index] = num_nonzeros_offd;

1779:                        num_nonzeros_offd++;

1780:                     }

1781:                  }

1782:                  for (jj2 = S_ext_diag_i[i2]; jj2 < S_ext_diag_i[i2+1]; jj2++)

1783:                  {

1784:                     i3 = S_ext_diag_j[jj2];

1785:                     if (i3 != ic && S_marker[i3] < jj_row_begin_diag)

1786:                     {

1787:                        S_marker[i3] = num_nonzeros_diag;

1788:                        num_nonzeros_diag++;

1789:                     }

1790:                  }

1791:                  for (jj2 = S_ext_offd_i[i2]; jj2 < S_ext_offd_i[i2+1]; jj2++)

1792:                  {

1793:                     i3 = S_ext_offd_j[jj2];

1794:                     if (S_marker_offd[i3] < jj_row_begin_offd)

1795:                     {

1796:                        S_marker_offd[i3] = num_nonzeros_offd;

1797:                        num_nonzeros_offd++;

[...]

1806:          for (ic = ic_begin; ic < ic_end; ic++)

[...]

1812:              HYPRE_Int i1 = coarse_to_fine[ic];

1813:

1814:              HYPRE_Int jj_row_begin_diag = jj_count_diag;

1815:              HYPRE_Int jj_row_begin_offd = jj_count_offd;

1816:

1817:              C_diag_i[ic] = num_nonzeros_diag;

1818:              if (num_cols_offd_C)

1819:              {

1820:                 C_offd_i[ic] = num_nonzeros_offd;

1821:              }

1822:

1823:              for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++)

1824:              {

1825:                  i2 = S_diag_j[jj1];

1826:                  if (CF_marker[i2] > 0)

1827:                  {

1828:                     index = fine_to_coarse[i2];

1829:                     if (S_marker[index] < jj_row_begin_diag)

1830:                     {

1831:                        S_marker[index] = jj_count_diag;

1832:                        C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 2;

1833:                        jj_count_diag++;

1834:                     }

1835:                     else

1836:                     {

1837:                        C_temp_diag_data[S_marker[index] - jj_row_begin_diag] += 2;

1838:                     }

1839:                  }

1840:                  for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++)

1841:                  {

1842:                     i3 = S_diag_j[jj2];

1843:                     if (CF_marker[i3] > 0 && fine_to_coarse[i3] != ic)

1844:                     {

1845:                        index = fine_to_coarse[i3];

1846:                        if (S_marker[index] < jj_row_begin_diag)

1847:                        {

1848:                           S_marker[index] = jj_count_diag;

1849:                           C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 1;

1850:                           jj_count_diag++;

1851:                        }

1852:                        else

1853:                        {

1854:                           C_temp_diag_data[S_marker[index] - jj_row_begin_diag]++;

1855:                        }

1856:                     }

1857:                  }

1858:                  for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++)

1859:                  {

1860:                     i3 = S_offd_j[jj2];

1861:                     if (CF_marker_offd[i3] > 0)

1862:                     {

1863:                        index = map_S_to_C[i3];

1864:                        if (S_marker_offd[index] < jj_row_begin_offd)

1865:                        {

1866:                           S_marker_offd[index] = jj_count_offd;

1867:                           C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 1;

1868:                           jj_count_offd++;

1869:                        }

1870:                        else

1871:                        {

1872:                           C_temp_offd_data[S_marker_offd[index] - jj_row_begin_offd]++;

1873:                        }

1874:                     }

1875:                  }

1876:              }

1877:              for (jj1 = S_offd_i[i1]; jj1 < S_offd_i[i1+1]; jj1++)

1878:              {

1879:                  i2 = S_offd_j[jj1];

1880:                  if (CF_marker_offd[i2] > 0)

1881:                  {

1882:                     index = map_S_to_C[i2];

1883:                     if (S_marker_offd[index] < jj_row_begin_offd)

1884:                     {

1885:                        S_marker_offd[index] = jj_count_offd;

1886:                        C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 2;

1887:                        jj_count_offd++;

1888:                     }

1889:                     else

1890:                     {

1891:                        C_temp_offd_data[S_marker_offd[index] - jj_row_begin_offd] += 2;

1892:                     }

1893:                  }

1894:                  for (jj2 = S_ext_diag_i[i2]; jj2 < S_ext_diag_i[i2+1]; jj2++)

1895:                  {

1896:                     i3 = S_ext_diag_j[jj2];

1897:                     if (i3 != ic)

1898:                     {

1899:                        if (S_marker[i3] < jj_row_begin_diag)

1900:                        {

1901:                           S_marker[i3] = jj_count_diag;

1902:                           C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 1;

1903:                           jj_count_diag++;

1904:                        }

1905:                        else

1906:                        {

1907:                           C_temp_diag_data[S_marker[i3] - jj_row_begin_diag]++;

1908:                        }

1909:                     }

1910:                  }

1911:                  for (jj2 = S_ext_offd_i[i2]; jj2 < S_ext_offd_i[i2+1]; jj2++)

1912:                  {

1913:                     i3 = S_ext_offd_j[jj2];

1914:                     if (S_marker_offd[i3] < jj_row_begin_offd)

1915:                     {

1916:                        S_marker_offd[i3] = jj_count_offd;

1917:                        C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 1;

1918:                        jj_count_offd++;

1919:                     }

1920:                     else

1921:                     {

1922:                        C_temp_offd_data[S_marker_offd[i3] - jj_row_begin_offd]++;

1923:                     }

1924:                  }

1925:              }

1926:

1927:              for (jj1 = jj_row_begin_diag; jj1 < jj_count_diag; jj1++)

1928:              {

1929:                  if (C_temp_diag_data[jj1 - jj_row_begin_diag] >= num_paths)

1930:                  {

1931:                     ++num_nonzeros_diag;

1932:                  }

1933:                  C_temp_diag_data[jj1 - jj_row_begin_diag] = 0;

1934:              }

1935:              for (jj1 = jj_row_begin_offd; jj1 < jj_count_offd; jj1++)

1936:              {

1937:                  if (C_temp_offd_data[jj1 - jj_row_begin_offd] >= num_paths)

1938:                  {

1939:                     ++num_nonzeros_offd;

1940:                  }

1941:                  C_temp_offd_data[jj1 - jj_row_begin_offd] = 0;

1942:              }

1943:          } /* for each row */

1944:       } /* num_paths > 1 */

1945:

1946:       hypre_prefix_sum_pair(

1947:          &num_nonzeros_diag, &C_diag_i[num_coarse],

1948:          &num_nonzeros_offd, &C_offd_i[num_coarse],

1949:          prefix_sum_workspace);

1950:

1951:       for (i1 = 0; i1 < num_coarse; i1++)

1952:       {

1953:          S_marker[i1] = -1;

1954:       }

1955:       for (i1 = 0; i1 < num_cols_offd_C; i1++)

1956:       {

1957:          S_marker_offd[i1] = -1;

1958:       }

1959:

1960: #ifdef HYPRE_USING_OPENMP

1961: #pragma omp barrier

1962: #pragma omp master

1963: #endif

1964:       {

1965:          if (C_diag_i[num_coarse])

1966:          {

1967:             C_diag_j = hypre_TAlloc(HYPRE_Int, C_diag_i[num_coarse]);

1968:          }

1969:          if (C_offd_i[num_coarse])

1970:          {

1971:             C_offd_j = hypre_TAlloc(HYPRE_Int, C_offd_i[num_coarse]);

1972:          }

1973:       }

1974: #ifdef HYPRE_USING_OPENMP

1975: #pragma omp barrier

1976: #endif

1977:

1978:       for (ic = ic_begin; ic < ic_end - 1; ic++)

1979:       {

1980:          if (C_diag_i[ic+1] == C_diag_i[ic] && C_offd_i[ic+1] == C_offd_i[ic])

1981:             CF_marker[coarse_to_fine[ic]] = 2;

1982:

1983:          C_diag_i[ic] += num_nonzeros_diag;

1984:          C_offd_i[ic] += num_nonzeros_offd;

1985:       }

1986:       if (ic_begin < ic_end)

1987:       {

1988:          C_diag_i[ic] += num_nonzeros_diag;

1989:          C_offd_i[ic] += num_nonzeros_offd;

1990:

1991:          HYPRE_Int next_C_diag_i = prefix_sum_workspace[2*(my_thread_num + 1)];

1992:          HYPRE_Int next_C_offd_i = prefix_sum_workspace[2*(my_thread_num + 1) + 1];

1993:

1994:          if (next_C_diag_i == C_diag_i[ic] && next_C_offd_i == C_offd_i[ic])

1995:             CF_marker[coarse_to_fine[ic]] = 2;

1996:       }

1997:

1998:       if (num_paths == 1)

1999:       {

2000:          for (ic = ic_begin; ic < ic_end; ic++)

[...]

2009:              HYPRE_Int jj_row_begin_offd = num_nonzeros_offd;

2010:

2011:              for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++)

2012:              {

2013:                  i2 = S_diag_j[jj1];

2014:                  if (CF_marker[i2] > 0)

2015:                  {

2016:                     index = fine_to_coarse[i2];

2017:                     if (S_marker[index] < jj_row_begin_diag)

2018:                     {

2019:                        S_marker[index] = num_nonzeros_diag;

2020:                        C_diag_j[num_nonzeros_diag] = index;

2021:                        num_nonzeros_diag++;

2022:                     }

2023:                  }

2024:                  for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++)

2025:                  {

2026:                     i3 = S_diag_j[jj2];

2027:                     if (CF_marker[i3] > 0)

2028:                     {

2029:                        index = fine_to_coarse[i3];

2030:                        if (index != ic && S_marker[index] < jj_row_begin_diag)

2031:                        {

2032:                           S_marker[index] = num_nonzeros_diag;

2033:                           C_diag_j[num_nonzeros_diag] = index;

2034:                           num_nonzeros_diag++;

2035:                        }

2036:                     }

2037:                  }

2038:                  for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++)

2039:                  {

2040:                     i3 = S_offd_j[jj2];

2041:                     if (CF_marker_offd[i3] > 0)

2042:                     {

2043:                        index = map_S_to_C[i3];

2044:                        if (S_marker_offd[index] < jj_row_begin_offd)

2045:                        {

2046:                           S_marker_offd[index] = num_nonzeros_offd;

2047:                           C_offd_j[num_nonzeros_offd] = index;

2048:                           num_nonzeros_offd++;

2049:                        }

2050:                     }

2051:                  }

2052:              }

2053:              for (jj1 = S_offd_i[i1]; jj1 < S_offd_i[i1+1]; jj1++)

2054:              {

2055:                  i2 = S_offd_j[jj1];

2056:                  if (CF_marker_offd[i2] > 0)

2057:                  {

2058:                     index = map_S_to_C[i2];

2059:                     if (S_marker_offd[index] < jj_row_begin_offd)

2060:                     {

2061:                        S_marker_offd[index] = num_nonzeros_offd;

2062:                        C_offd_j[num_nonzeros_offd] = index;

2063:                        num_nonzeros_offd++;

2064:                     }

2065:                  }

2066:                  for (jj2 = S_ext_diag_i[i2]; jj2 < S_ext_diag_i[i2+1]; jj2++)

2067:                  {

2068:                     i3 = S_ext_diag_j[jj2];

2069:                     if (i3 != ic && S_marker[i3] < jj_row_begin_diag)

2070:                     {

2071:                        S_marker[i3] = num_nonzeros_diag;

2072:                        C_diag_j[num_nonzeros_diag] = i3;

2073:                        num_nonzeros_diag++;

2074:                     }

2075:                  }

2076:                  for (jj2 = S_ext_offd_i[i2]; jj2 < S_ext_offd_i[i2+1]; jj2++)

2077:                  {

2078:                     i3 = S_ext_offd_j[jj2];

2079:                     if (S_marker_offd[i3] < jj_row_begin_offd)

2080:                     {

2081:                        S_marker_offd[i3] = num_nonzeros_offd;

2082:                        C_offd_j[num_nonzeros_offd] = i3;

2083:                        num_nonzeros_offd++;

[...]

2095:          for (ic = ic_begin; ic < ic_end; ic++)

[...]

2106:              for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++)

2107:              {

2108:                  i2 = S_diag_j[jj1];

2109:                  if (CF_marker[i2] > 0)

2110:                  {

2111:                     index = fine_to_coarse[i2];

2112:                     if (S_marker[index] < jj_row_begin_diag)

2113:                     {

2114:                        S_marker[index] = jj_count_diag;

2115:                        C_temp_diag_j[jj_count_diag - jj_row_begin_diag] = index;

2116:                        C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 2;

2117:                        jj_count_diag++;

2118:                     }

2119:                     else

2120:                     {

2121:                        C_temp_diag_data[S_marker[index] - jj_row_begin_diag] += 2;

2122:                     }

2123:                  }

2124:                  for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++)

2125:                  {

2126:                     i3 = S_diag_j[jj2];

2127:                     if (CF_marker[i3] > 0 && fine_to_coarse[i3] != ic)

2128:                     {

2129:                        index = fine_to_coarse[i3];

2130:                        if (S_marker[index] < jj_row_begin_diag)

2131:                        {

2132:                           S_marker[index] = jj_count_diag;

2133:                           C_temp_diag_j[jj_count_diag - jj_row_begin_diag] = index;

2134:                           C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 1;

2135:                           jj_count_diag++;

2136:                        }

2137:                        else

2138:                        {

2139:                           C_temp_diag_data[S_marker[index] - jj_row_begin_diag]++;

2140:                        }

2141:                     }

2142:                  }

2143:                  for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++)

2144:                  {

2145:                     i3 = S_offd_j[jj2];

2146:                     if (CF_marker_offd[i3] > 0)

2147:                     {

2148:                        index = map_S_to_C[i3];

2149:                        if (S_marker_offd[index] < jj_row_begin_offd)

2150:                        {

2151:                           S_marker_offd[index] = jj_count_offd;

2152:                           C_temp_offd_j[jj_count_offd - jj_row_begin_offd] = index;

2153:                           C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 1;

2154:                           jj_count_offd++;

2155:                        }

2156:                        else

2157:                        {

2158:                           C_temp_offd_data[S_marker_offd[index] - jj_row_begin_offd]++;

2159:                        }

2160:                     }

2161:                  }

2162:              }

2163:              for (jj1 = S_offd_i[i1]; jj1 < S_offd_i[i1+1]; jj1++)

2164:              {

2165:                  i2 = S_offd_j[jj1];

2166:                  if (CF_marker_offd[i2] > 0)

2167:                  {

2168:                     index = map_S_to_C[i2];

2169:                     if (S_marker_offd[index] < jj_row_begin_offd)

2170:                     {

2171:                        S_marker_offd[index] = jj_count_offd;

2172:                        C_temp_offd_j[jj_count_offd - jj_row_begin_offd] = index;

2173:                        C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 2;

2174:                        jj_count_offd++;

2175:                     }

2176:                     else

2177:                     {

2178:                        C_temp_offd_data[S_marker_offd[index] - jj_row_begin_offd] += 2;

2179:                     }

2180:                  }

2181:                  for (jj2 = S_ext_diag_i[i2]; jj2 < S_ext_diag_i[i2+1]; jj2++)

2182:                  {

2183:                     i3 = S_ext_diag_j[jj2];

2184:                     if (i3 != ic)

2185:                     {

2186:                        if (S_marker[i3] < jj_row_begin_diag)

2187:                        {

2188:                           S_marker[i3] = jj_count_diag;

2189:                           C_temp_diag_j[jj_count_diag - jj_row_begin_diag] = i3;

2190:                           C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 1;

2191:                           jj_count_diag++;

2192:                        }

2193:                        else

2194:                        {

2195:                           C_temp_diag_data[S_marker[i3] - jj_row_begin_diag]++;

2196:                        }

2197:                     }

2198:                  }

2199:                  for (jj2 = S_ext_offd_i[i2]; jj2 < S_ext_offd_i[i2+1]; jj2++)

2200:                  {

2201:                     i3 = S_ext_offd_j[jj2];

2202:                     if (S_marker_offd[i3] < jj_row_begin_offd)

2203:                     {

2204:                        S_marker_offd[i3] = jj_count_offd;

2205:                        C_temp_offd_j[jj_count_offd - jj_row_begin_offd] = i3;

2206:                        C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 1;

2207:                        jj_count_offd++;

2208:                     }

2209:                     else

2210:                     {

2211:                        C_temp_offd_data[S_marker_offd[i3] - jj_row_begin_offd]++;

2212:                     }

2213:                  }

2214:              }

2215:

2216:              for (jj1 = jj_row_begin_diag; jj1 < jj_count_diag; jj1++)

2217:              {

2218:                  if (C_temp_diag_data[jj1 - jj_row_begin_diag] >= num_paths)

2219:                  {

2220:                     C_diag_j[num_nonzeros_diag++] = C_temp_diag_j[jj1 - jj_row_begin_diag];

2221:                  }

2222:                  C_temp_diag_data[jj1 - jj_row_begin_diag] = 0;

2223:              }

2224:              for (jj1 = jj_row_begin_offd; jj1 < jj_count_offd; jj1++)

2225:              {

2226:                  if (C_temp_offd_data[jj1 - jj_row_begin_offd] >= num_paths)

2227:                  {

2228:                     C_offd_j[num_nonzeros_offd++] = C_temp_offd_j[jj1 - jj_row_begin_offd];

2229:                  }

2230:                  C_temp_offd_data[jj1 - jj_row_begin_offd] = 0;

0x4ab340 STP	X29, X30, [SP, #688]!

0x4ab344 ORR	X2, XZR, X0

0x4ab348 ADD	X29, SP, #0

0x4ab34c ADRP	X1,

0x4ab350 LDR	X0, [X1, #3848]

0x4ab354 STP	X25, X26, [SP, #64]

0x4ab358 LDR	X3, [X2, #8]

0x4ab35c LDP	X18, X26, [X2, #16]

0x4ab360 STP	X19, X20, [SP, #16]

0x4ab364 LDR	X5, [X2, #32]

0x4ab368 STP	X21, X22, [SP, #32]

0x4ab36c LDR	X7, [X2, #56]

0x4ab370 STP	X23, X24, [SP, #48]

0x4ab374 LDR	X8, [X2, #72]

0x4ab378 STP	X27, X28, [SP, #80]

0x4ab37c LDR	X9, [X2, #96]

0x4ab380 STR	X3, [SP, #104]

0x4ab384 LDR	X3, [X0]

0x4ab388 STR	X3, [SP, #328]

0x4ab38c MOVZ	X3, #0

0x4ab390 STR	X7, [SP, #144]

0x4ab394 STR	X18, [SP, #168]

0x4ab398 STR	X8, [SP, #192]

0x4ab39c STR	X9, [SP, #216]

0x4ab3a0 STR	X5, [SP, #232]

0x4ab3a4 LDR	X23, [X2]

0x4ab3a8 LDR	X25, [X2, #40]

0x4ab3ac LDR	X20, [X2, #48]

0x4ab3b0 LDP	X28, X10, [X2, #104]

0x4ab3b4 LDP	X11, X12, [X2, #136]

0x4ab3b8 LDP	X14, X19, [X2, #192]

0x4ab3bc STP	X12, X11, [SP, #152]

0x4ab3c0 LDR	X15, [X2, #160]

0x4ab3c4 STR	X14, [SP, #120]

0x4ab3c8 LDR	X13, [X2, #168]

0x4ab3cc STR	X10, [SP, #208]

0x4ab3d0 LDR	X16, [X2, #176]

0x4ab3d4 STR	X2, [SP, #224]

0x4ab3d8 LDR	X17, [X2, #184]

0x4ab3dc STR	X13, [SP, #136]

0x4ab3e0 LDR	X30, [X2, #208]

0x4ab3e4 STR	X16, [SP, #128]

0x4ab3e8 STR	X15, [SP, #248]

0x4ab3ec STR	X17, [SP, #200]

0x4ab3f0 LDP	X27, X24, [X2, #120]

0x4ab3f4 STR	X30, [SP, #184]

0x4ab3f8 LDP	X21, X22, [X2, #216]

0x4ab3fc BL	519580

0x4ab400 ORR	X4, XZR, X0

0x4ab404 ORR	X2, XZR, X20

0x4ab408 ADD	X1, SP, #304

0x4ab40c ADD	X0, SP, #296

0x4ab410 STR	X4, [SP, #112]

0x4ab414 BL	5195a0

0x4ab418 LDR	X2, [SP, #224]

0x4ab41c LDP	X1, X3, [SP, #104]

0x4ab420 LDP	X7, X8, [SP, #152]

0x4ab424 CMP	X1, #1

0x4ab428 LDR	X6, [X2, #88]

0x4ab42c LDR	X5, [SP, #120]

0x4ab430 LDR	X4, [SP, #136]

0x4ab434 STR	X6, [SP, #176]

0x4ab438 LDR	X18, [SP, #168]

0x4ab43c B.LE	4ac5e4

0x4ab440 LDR	X15, [X6]

0x4ab444 LDR	X9, [X2, #152]

0x4ab448 MADD	X20, X3, X15, XZR

0x4ab44c LDR	X12, [X9]

0x4ab450 UBFM	X10, X20, #61, #60

0x4ab454 STR	X9, [SP, #240]

0x4ab458 ADD	X11, X19, X10

0x4ab45c LDR	X19, [SP, #184]

0x4ab460 ADD	X20, X21, X10

0x4ab464 STR	X11, [SP, #264]

0x4ab468 MADD	X13, X3, X12, XZR

0x4ab46c UBFM	X14, X13, #61, #60

0x4ab470 ADD	X21, X19, X14

0x4ab474 ADD	X22, X22, X14

0x4ab478 STR	X21, [SP, #256]

0x4ab47c CBZ	X12, 4ab4f8

0x4ab480 LDR	X30, [SP, #200]

0x4ab484 MADD	X17, X3, X12, XZR

0x4ab488 ADD	X21, X30, X17,LSL #3

0x4ab48c CBZ	X15, 4abd08

0x4ab490 MADD	X1, X3, X15, XZR

0x4ab494 ADD	X19, X5, X1,LSL #3

0x4ab498 CMP	X12, #0

0x4ab49c B.LE	4ab4c8

0x4ab4a0 LDR	X5, [SP, #240]

0x4ab4a4 MOVZ	X6, #0

0x4ab4a8 MOVN	X2, #0

(2336) 0x4ab4ac STR	X2, [X21, X6,LSL #3]

(2336) 0x4ab4b0 ADD	X6, X6, #1

(2336) 0x4ab4b4 LDR	X0, [X5]

(2336) 0x4ab4b8 CMP	X0, X6

(2336) 0x4ab4bc B.GT	4ab4ac

0x4ab4c0 LDR	X9, [SP, #176]

0x4ab4c4 LDR	X15, [X9]

0x4ab4c8 MOVZ	X12, #0

0x4ab4cc MOVN	X10, #0

0x4ab4d0 CMP	X15, #0

0x4ab4d4 B.LE	4ab504

0x4ab4d8 LDR	X11, [SP, #176]

0x4ab4dc HINT	#0

(2335) 0x4ab4e0 STR	X10, [X19, X12,LSL #3]

(2335) 0x4ab4e4 ADD	X12, X12, #1

(2335) 0x4ab4e8 LDR	X13, [X11]

(2335) 0x4ab4ec CMP	X13, X12

(2335) 0x4ab4f0 B.GT	4ab4e0

0x4ab4f4 B	4ab504

0x4ab4f8 CBNZ	X15, 4ac930

0x4ab4fc MOVZ	X21, #0

0x4ab500 MOVZ	X19, #0

0x4ab504 ADD	X14, X4, X3,LSL #3

0x4ab508 ADD	X15, X3, #1

0x4ab50c LDR	X5, [X4, X3,LSL #3]

0x4ab510 STP	XZR, XZR, [SP, #312]

0x4ab514 LDR	X3, [X14, #8]

0x4ab518 STR	X15, [SP, #272]

0x4ab51c LDR	X4, [SP, #104]

0x4ab520 STR	X3, [SP, #136]

0x4ab524 CMP	X4, #1

0x4ab528 B.EQ	4ac604

0x4ab52c LDR	X16, [SP, #136]

0x4ab530 CMP	X5, X16

0x4ab534 B.GE	4abda0

0x4ab538 MOVZ	X30, #0

0x4ab53c LDR	X17, [SP, #216]

0x4ab540 ORR	X10, XZR, X5

0x4ab544 MOVZ	X1, #0

0x4ab548 MOVZ	X4, #0

0x4ab54c STR	WZR, [SP, #160]

0x4ab550 STP	X30, XZR, [SP, #112]

0x4ab554 MOVZ	X12, #1

0x4ab558 LDR	X30, [SP, #208]

0x4ab55c STR	WZR, [SP, #168]

0x4ab560 LDR	X16, [SP, #232]

0x4ab564 STR	X5, [SP, #280]

(2327) 0x4ab568 LDR	X5, [SP, #128]

(2327) 0x4ab56c LDR	X2, [SP, #112]

(2327) 0x4ab570 LDR	X0, [SP, #144]

(2327) 0x4ab574 LDR	X6, [X5, X10,LSL #3]

(2327) 0x4ab578 LDR	X9, [SP, #176]

(2327) 0x4ab57c STR	X2, [X0, X10,LSL #3]

(2327) 0x4ab580 STR	X6, [SP, #152]

(2327) 0x4ab584 LDR	X11, [X9]

(2327) 0x4ab588 CBZ	X11, 4ab598

(2327) 0x4ab58c LDR	X13, [SP, #120]

(2327) 0x4ab590 LDR	X14, [SP, #192]

(2327) 0x4ab594 STR	X13, [X14, X10,LSL #3]

(2327) 0x4ab598 LDR	X15, [SP, #152]

(2327) 0x4ab59c ORR	X5, XZR, X4

(2327) 0x4ab5a0 ORR	X2, XZR, X1

(2327) 0x4ab5a4 UBFM	X3, X15, #61, #60

(2327) 0x4ab5a8 LDR	X14, [X18, X15,LSL #3]

(2327) 0x4ab5ac ADD	X6, X3, #8

(2327) 0x4ab5b0 LDR	X0, [X18, X6]

(2327) 0x4ab5b4 ADD	X9, X18, X6

(2327) 0x4ab5b8 STR	X6, [SP, #184]

(2327) 0x4ab5bc CMP	X14, X0

(2327) 0x4ab5c0 B.GE	4ac5c4

(2327) 0x4ab5c4 STR	X27, [SP, #200]

(2327) 0x4ab5c8 ORR	X27, XZR, X9

  (2332) 0x4ab5cc LDR	X13, [X26, X14,LSL #3]

  (2332) 0x4ab5d0 LDR	X6, [X23, X13,LSL #3]

  (2332) 0x4ab5d4 UBFM	X9, X13, #61, #60

  (2332) 0x4ab5d8 CMP	X6, #0

  (2332) 0x4ab5dc B.LE	4ab600

  (2332) 0x4ab5e0 LDR	X11, [X8, X13,LSL #3]

  (2332) 0x4ab5e4 LDR	X0, [X21, X11,LSL #3]

  (2332) 0x4ab5e8 CMP	X0, X4

  (2332) 0x4ab5ec B.LT	4abd64

  (2332) 0x4ab5f0 SUB	X15, X0, X4

  (2332) 0x4ab5f4 LDR	X3, [X22, X15,LSL #3]

  (2332) 0x4ab5f8 ADD	X6, X3, #2

  (2332) 0x4ab5fc STR	X6, [X22, X15,LSL #3]

  (2332) 0x4ab600 ADD	X11, X9, #8

  (2332) 0x4ab604 LDR	X0, [X18, X13,LSL #3]

  (2332) 0x4ab608 ADD	X15, X18, X11

  (2332) 0x4ab60c LDR	X9, [X18, X11]

  (2332) 0x4ab610 CMP	X0, X9

  (2332) 0x4ab614 B.LT	4ab63c

  (2332) 0x4ab618 B	4ab684

    (2334) 0x4ab61c SUB	X6, X9, X4

    (2334) 0x4ab620 LDR	X3, [X22, X6,LSL #3]

    (2334) 0x4ab624 ADD	X9, X3, #1

    (2334) 0x4ab628 STR	X9, [X22, X6,LSL #3]

    (2334) 0x4ab62c LDR	X9, [X15]

    (2334) 0x4ab630 ADD	X0, X0, #1

    (2334) 0x4ab634 CMP	X0, X9

    (2334) 0x4ab638 B.GE	4ab684

    (2334) 0x4ab63c LDR	X3, [X26, X0,LSL #3]

    (2334) 0x4ab640 LDR	X6, [X23, X3,LSL #3]

    (2334) 0x4ab644 CMP	X6, #0

    (2334) 0x4ab648 B.LE	4ab630

    (2334) 0x4ab64c LDR	X3, [X8, X3,LSL #3]

    (2334) 0x4ab650 CMP	X3, X10

    (2334) 0x4ab654 B.EQ	4ab630

    (2334) 0x4ab658 LDR	X9, [X21, X3,LSL #3]

    (2334) 0x4ab65c CMP	X9, X4

    (2334) 0x4ab660 B.GE	4ab61c

    (2334) 0x4ab664 SUB	X6, X5, X4

    (2334) 0x4ab668 STR	X5, [X21, X3,LSL #3]

    (2334) 0x4ab66c ADD	X0, X0, #1

    (2334) 0x4ab670 ADD	X5, X5, #1

    (2334) 0x4ab674 STR	X12, [X22, X6,LSL #3]

    (2334) 0x4ab678 LDR	X9, [X15]

    (2334) 0x4ab67c CMP	X0, X9

    (2334) 0x4ab680 B.LT	4ab63c

  (2332) 0x4ab684 LDR	X0, [X16, X13,LSL #3]

  (2332) 0x4ab688 ADD	X13, X16, X11

  (2332) 0x4ab68c LDR	X11, [X16, X11]

  (2332) 0x4ab690 CMP	X0, X11

  (2332) 0x4ab694 B.LT	4ab6bc

  (2332) 0x4ab698 B	4ab6fc

    (2333) 0x4ab69c SUB	X15, X6, X1

    (2333) 0x4ab6a0 LDR	X9, [X20, X15,LSL #3]

    (2333) 0x4ab6a4 ADD	X3, X9, #1

    (2333) 0x4ab6a8 STR	X3, [X20, X15,LSL #3]

    (2333) 0x4ab6ac LDR	X11, [X13]

    (2333) 0x4ab6b0 ADD	X0, X0, #1

    (2333) 0x4ab6b4 CMP	X0, X11

    (2333) 0x4ab6b8 B.GE	4ab6fc

    (2333) 0x4ab6bc LDR	X15, [X25, X0,LSL #3]

    (2333) 0x4ab6c0 LDR	X3, [X24, X15,LSL #3]

    (2333) 0x4ab6c4 CMP	X3, #0

    (2333) 0x4ab6c8 B.LE	4ab6b0

    (2333) 0x4ab6cc LDR	X11, [X7, X15,LSL #3]

    (2333) 0x4ab6d0 LDR	X6, [X19, X11,LSL #3]

    (2333) 0x4ab6d4 CMP	X6, X1

    (2333) 0x4ab6d8 B.GE	4ab69c

    (2333) 0x4ab6dc SUB	X6, X2, X1

    (2333) 0x4ab6e0 STR	X2, [X19, X11,LSL #3]

    (2333) 0x4ab6e4 ADD	X0, X0, #1

    (2333) 0x4ab6e8 ADD	X2, X2, #1

    (2333) 0x4ab6ec STR	X12, [X20, X6,LSL #3]

    (2333) 0x4ab6f0 LDR	X11, [X13]

    (2333) 0x4ab6f4 CMP	X0, X11

    (2333) 0x4ab6f8 B.LT	4ab6bc

  (2332) 0x4ab6fc LDR	X13, [X27]

  (2332) 0x4ab700 ADD	X14, X14, #1

  (2332) 0x4ab704 CMP	X13, X14

  (2332) 0x4ab708 B.GT	4ab5cc

(2327) 0x4ab70c LDR	X15, [SP, #152]

(2327) 0x4ab710 LDR	X9, [SP, #184]

(2327) 0x4ab714 LDR	X27, [SP, #200]

(2327) 0x4ab718 LDR	X14, [X16, X15,LSL #3]

(2327) 0x4ab71c ADD	X15, X16, X9

(2327) 0x4ab720 LDR	X3, [X16, X9]

(2327) 0x4ab724 CMP	X14, X3

(2327) 0x4ab728 B.GE	4ab828

  (2326) 0x4ab72c LDR	X13, [X25, X14,LSL #3]

  (2326) 0x4ab730 LDR	X6, [X24, X13,LSL #3]

  (2326) 0x4ab734 UBFM	X11, X13, #61, #60

  (2326) 0x4ab738 CMP	X6, #0

  (2326) 0x4ab73c B.LE	4ab760

  (2326) 0x4ab740 LDR	X9, [X7, X13,LSL #3]

  (2326) 0x4ab744 LDR	X0, [X19, X9,LSL #3]

  (2326) 0x4ab748 CMP	X0, X1

  (2326) 0x4ab74c B.LT	4abd4c

  (2326) 0x4ab750 SUB	X6, X0, X1

  (2326) 0x4ab754 LDR	X3, [X20, X6,LSL #3]

  (2326) 0x4ab758 ADD	X9, X3, #2

  (2326) 0x4ab75c STR	X9, [X20, X6,LSL #3]

  (2326) 0x4ab760 ADD	X11, X11, #8

  (2326) 0x4ab764 LDR	X0, [X17, X13,LSL #3]

  (2326) 0x4ab768 ADD	X9, X17, X11

  (2326) 0x4ab76c LDR	X6, [X17, X11]

  (2326) 0x4ab770 CMP	X0, X6

  (2326) 0x4ab774 B.LT	4ab79c

  (2326) 0x4ab778 B	4ab7d4

    (2331) 0x4ab77c SUB	X6, X6, X4

    (2331) 0x4ab780 LDR	X3, [X22, X6,LSL #3]

    (2331) 0x4ab784 ADD	X3, X3, #1

    (2331) 0x4ab788 STR	X3, [X22, X6,LSL #3]

    (2331) 0x4ab78c LDR	X6, [X9]

    (2331) 0x4ab790 ADD	X0, X0, #1

    (2331) 0x4ab794 CMP	X0, X6

    (2331) 0x4ab798 B.GE	4ab7d4

    (2331) 0x4ab79c LDR	X3, [X28, X0,LSL #3]

    (2331) 0x4ab7a0 CMP	X3, X10

    (2331) 0x4ab7a4 B.EQ	4ab790

    (2331) 0x4ab7a8 LDR	X6, [X21, X3,LSL #3]

    (2331) 0x4ab7ac CMP	X6, X4

    (2331) 0x4ab7b0 B.GE	4ab77c

    (2331) 0x4ab7b4 SUB	X6, X5, X4

    (2331) 0x4ab7b8 STR	X5, [X21, X3,LSL #3]

    (2331) 0x4ab7bc ADD	X0, X0, #1

    (2331) 0x4ab7c0 ADD	X5, X5, #1

    (2331) 0x4ab7c4 STR	X12, [X22, X6,LSL #3]

    (2331) 0x4ab7c8 LDR	X6, [X9]

    (2331) 0x4ab7cc CMP	X0, X6

    (2331) 0x4ab7d0 B.LT	4ab79c

  (2326) 0x4ab7d4 LDR	X0, [X30, X13,LSL #3]

  (2326) 0x4ab7d8 ADD	X13, X30, X11

  (2326) 0x4ab7dc LDR	X11, [X30, X11]

  (2326) 0x4ab7e0 CMP	X0, X11

  (2326) 0x4ab7e4 B.GE	4ab818

    (2330) 0x4ab7e8 LDR	X9, [X27, X0,LSL #3]

    (2330) 0x4ab7ec LDR	X3, [X19, X9,LSL #3]

    (2330) 0x4ab7f0 CMP	X3, X1

    (2330) 0x4ab7f4 B.LT	4abd18

    (2330) 0x4ab7f8 SUB	X11, X3, X1

    (2330) 0x4ab7fc ADD	X0, X0, #1

    (2330) 0x4ab800 LDR	X6, [X20, X11,LSL #3]

    (2330) 0x4ab804 ADD	X9, X6, #1

    (2330) 0x4ab808 STR	X9, [X20, X11,LSL #3]

    (2330) 0x4ab80c LDR	X3, [X13]

    (2330) 0x4ab810 CMP	X3, X0

    (2330) 0x4ab814 B.GT	4ab7e8

  (2326) 0x4ab818 LDR	X13, [X15]

  (2326) 0x4ab81c ADD	X14, X14, #1

  (2326) 0x4ab820 CMP	X13, X14

  (2326) 0x4ab824 B.GT	4ab72c

(2327) 0x4ab828 CMP	X5, X4

(2327) 0x4ab82c B.LE	4aba88

(2327) 0x4ab830 SUB	X4, X22, X4,LSL #3

(2327) 0x4ab834 ORR	X3, XZR, X22

(2327) 0x4ab838 ADD	X14, X4, X5,LSL #3

(2327) 0x4ab83c SUB	X15, X14, X22

(2327) 0x4ab840 SUB	X9, X15, #8

(2327) 0x4ab844 UBFM	X11, X9, #3, #63

(2327) 0x4ab848 ADD	X0, X11, #1

(2327) 0x4ab84c ANDS	X6, X0, #4224

(2327) 0x4ab850 B.EQ	4ab9a8

(2327) 0x4ab854 CMP	X6, #1

(2327) 0x4ab858 B.EQ	4ab978

(2327) 0x4ab85c CMP	X6, #2

(2327) 0x4ab860 B.EQ	4ab950

(2327) 0x4ab864 CMP	X6, #3

(2327) 0x4ab868 B.EQ	4ab928

(2327) 0x4ab86c CMP	X6, #4

(2327) 0x4ab870 B.EQ	4ab900

(2327) 0x4ab874 CMP	X6, #5

(2327) 0x4ab878 B.EQ	4ab8d8

(2327) 0x4ab87c CMP	X6, #6

(2327) 0x4ab880 B.EQ	4ab8b0

(2327) 0x4ab884 LDR	X13, [X22]

(2327) 0x4ab888 LDR	X3, [SP, #104]

(2327) 0x4ab88c CMP	X3, X13

(2327) 0x4ab890 B.GT	4ab8a8

(2327) 0x4ab894 LDR	X4, [SP, #112]

(2327) 0x4ab898 MOVZ	W9, #1

(2327) 0x4ab89c STR	W9, [SP, #168]

(2327) 0x4ab8a0 ADD	X15, X4, #1

(2327) 0x4ab8a4 STR	X15, [SP, #112]

(2327) 0x4ab8a8 ORR	X3, XZR, X22

(2327) 0x4ab8ac STR	XZR, [X3], #8

(2327) 0x4ab8b0 LDR	X11, [X3]

(2327) 0x4ab8b4 LDR	X0, [SP, #104]

(2327) 0x4ab8b8 CMP	X0, X11

(2327) 0x4ab8bc B.GT	4ab8d4

(2327) 0x4ab8c0 LDR	X6, [SP, #112]

(2327) 0x4ab8c4 MOVZ	W4, #1

(2327) 0x4ab8c8 STR	W4, [SP, #168]

(2327) 0x4ab8cc ADD	X13, X6, #1

(2327) 0x4ab8d0 STR	X13, [SP, #112]

(2327) 0x4ab8d4 STR	XZR, [X3], #8

(2327) 0x4ab8d8 LDR	X15, [X3]

(2327) 0x4ab8dc LDR	X9, [SP, #104]

(2327) 0x4ab8e0 CMP	X9, X15

(2327) 0x4ab8e4 B.GT	4ab8fc

(2327) 0x4ab8e8 LDR	X11, [SP, #112]

(2327) 0x4ab8ec MOVZ	W6, #1

(2327) 0x4ab8f0 STR	W6, [SP, #168]

(2327) 0x4ab8f4 ADD	X0, X11, #1

(2327) 0x4ab8f8 STR	X0, [SP, #112]

(2327) 0x4ab8fc STR	XZR, [X3], #8

(2327) 0x4ab900 LDR	X13, [X3]

(2327) 0x4ab904 LDR	X4, [SP, #104]

(2327) 0x4ab908 CMP	X4, X13

(2327) 0x4ab90c B.GT	4ab924

(2327) 0x4ab910 LDR	X15, [SP, #112]

(2327) 0x4ab914 MOVZ	W11, #1

(2327) 0x4ab918 STR	W11, [SP, #168]

(2327) 0x4ab91c ADD	X9, X15, #1

(2327) 0x4ab920 STR	X9, [SP, #112]

(2327) 0x4ab924 STR	XZR, [X3], #8

(2327) 0x4ab928 LDR	X0, [X3]

(2327) 0x4ab92c LDR	X6, [SP, #104]

(2327) 0x4ab930 CMP	X6, X0

(2327) 0x4ab934 B.GT	4ab94c

(2327) 0x4ab938 LDR	X13, [SP, #112]

(2327) 0x4ab93c MOVZ	W15, #1

(2327) 0x4ab940 STR	W15, [SP, #168]

(2327) 0x4ab944 ADD	X4, X13, #1

(2327) 0x4ab948 STR	X4, [SP, #112]

(2327) 0x4ab94c STR	XZR, [X3], #8

(2327) 0x4ab950 LDR	X9, [X3]

(2327) 0x4ab954 LDR	X11, [SP, #104]

(2327) 0x4ab958 CMP	X11, X9

(2327) 0x4ab95c B.GT	4ab974

(2327) 0x4ab960 LDR	X0, [SP, #112]

(2327) 0x4ab964 MOVZ	W13, #1

(2327) 0x4ab968 STR	W13, [SP, #168]

(2327) 0x4ab96c ADD	X6, X0, #1

(2327) 0x4ab970 STR	X6, [SP, #112]

(2327) 0x4ab974 STR	XZR, [X3], #8

(2327) 0x4ab978 LDR	X4, [X3]

(2327) 0x4ab97c LDR	X15, [SP, #104]

(2327) 0x4ab980 CMP	X15, X4

(2327) 0x4ab984 B.GT	4ab99c

(2327) 0x4ab988 LDR	X9, [SP, #112]

(2327) 0x4ab98c MOVZ	W0, #1

(2327) 0x4ab990 STR	W0, [SP, #168]

(2327) 0x4ab994 ADD	X11, X9, #1

(2327) 0x4ab998 STR	X11, [SP, #112]

(2327) 0x4ab99c STR	XZR, [X3], #8

(2327) 0x4ab9a0 CMP	X14, X3

(2327) 0x4ab9a4 B.EQ	4aba88

(2327) 0x4ab9a8 LDR	W11, [SP, #168]

(2327) 0x4ab9ac LDP	X6, X9, [SP, #104]

  (2329) 0x4ab9b0 LDR	X13, [X3]

  (2329) 0x4ab9b4 CMP	X6, X13

  (2329) 0x4ab9b8 B.GT	4ab9c4

  (2329) 0x4ab9bc ADD	X9, X9, #1

  (2329) 0x4ab9c0 MOVZ	W11, #1

  (2329) 0x4ab9c4 ORR	X4, XZR, X3

  (2329) 0x4ab9c8 STR	XZR, [X4], #8

  (2329) 0x4ab9cc LDR	X3, [X3, #8]

  (2329) 0x4ab9d0 CMP	X6, X3

  (2329) 0x4ab9d4 B.GT	4ab9e0

  (2329) 0x4ab9d8 ADD	X9, X9, #1

  (2329) 0x4ab9dc MOVZ	W11, #1

  (2329) 0x4ab9e0 LDR	X15, [X4, #8]

  (2329) 0x4ab9e4 STR	XZR, [X4]

  (2329) 0x4ab9e8 CMP	X6, X15

  (2329) 0x4ab9ec B.GT	4ab9f8

  (2329) 0x4ab9f0 ADD	X9, X9, #1

  (2329) 0x4ab9f4 MOVZ	W11, #1

  (2329) 0x4ab9f8 LDR	X0, [X4, #16]

  (2329) 0x4ab9fc STR	XZR, [X4, #8]

  (2329) 0x4aba00 CMP	X6, X0

  (2329) 0x4aba04 B.GT	4aba10

  (2329) 0x4aba08 ADD	X9, X9, #1

  (2329) 0x4aba0c MOVZ	W11, #1

  (2329) 0x4aba10 LDR	X13, [X4, #24]

  (2329) 0x4aba14 STR	XZR, [X4, #16]

  (2329) 0x4aba18 CMP	X6, X13

  (2329) 0x4aba1c B.GT	4aba28

  (2329) 0x4aba20 ADD	X9, X9, #1

  (2329) 0x4aba24 MOVZ	W11, #1

  (2329) 0x4aba28 LDR	X3, [X4, #32]

  (2329) 0x4aba2c STR	XZR, [X4, #24]

  (2329) 0x4aba30 CMP	X6, X3

  (2329) 0x4aba34 B.GT	4aba40

  (2329) 0x4aba38 ADD	X9, X9, #1

  (2329) 0x4aba3c MOVZ	W11, #1

  (2329) 0x4aba40 LDR	X15, [X4, #40]

  (2329) 0x4aba44 STR	XZR, [X4, #32]

  (2329) 0x4aba48 CMP	X6, X15

  (2329) 0x4aba4c B.GT	4aba58

  (2329) 0x4aba50 ADD	X9, X9, #1

  (2329) 0x4aba54 MOVZ	W11, #1

  (2329) 0x4aba58 LDR	X0, [X4, #48]

  (2329) 0x4aba5c STR	XZR, [X4, #40]

  (2329) 0x4aba60 CMP	X6, X0

  (2329) 0x4aba64 B.GT	4aba70

  (2329) 0x4aba68 ADD	X9, X9, #1

  (2329) 0x4aba6c MOVZ	W11, #1

  (2329) 0x4aba70 ADD	X3, X4, #56

  (2329) 0x4aba74 STR	XZR, [X4, #48]

  (2329) 0x4aba78 CMP	X14, X3

  (2329) 0x4aba7c B.NE	4ab9b0

(2327) 0x4aba80 STR	X9, [SP, #112]

(2327) 0x4aba84 STR	W11, [SP, #168]

(2327) 0x4aba88 CMP	X1, X2

(2327) 0x4aba8c B.GE	4abcec

(2327) 0x4aba90 SUB	X1, X20, X1,LSL #3

(2327) 0x4aba94 ORR	X3, XZR, X20

(2327) 0x4aba98 ADD	X14, X1, X2,LSL #3

(2327) 0x4aba9c SUB	X6, X14, X20

(2327) 0x4abaa0 SUB	X4, X6, #8

(2327) 0x4abaa4 UBFM	X13, X4, #3, #63

(2327) 0x4abaa8 ADD	X15, X13, #1

(2327) 0x4abaac ANDS	X0, X15, #4224

(2327) 0x4abab0 B.EQ	4abc08

(2327) 0x4abab4 CMP	X0, #1

(2327) 0x4abab8 B.EQ	4abbd8

(2327) 0x4ababc CMP	X0, #2

(2327) 0x4abac0 B.EQ	4abbb0

(2327) 0x4abac4 CMP	X0, #3

(2327) 0x4abac8 B.EQ	4abb88

(2327) 0x4abacc CMP	X0, #4

(2327) 0x4abad0 B.EQ	4abb60

(2327) 0x4abad4 CMP	X0, #5

(2327) 0x4abad8 B.EQ	4abb38

(2327) 0x4abadc CMP	X0, #6

(2327) 0x4abae0 B.EQ	4abb10

(2327) 0x4abae4 LDR	X9, [X20]

(2327) 0x4abae8 LDR	X11, [SP, #104]

(2327) 0x4abaec CMP	X11, X9

(2327) 0x4abaf0 B.GT	4abb08

(2327) 0x4abaf4 LDR	X3, [SP, #120]

(2327) 0x4abaf8 MOVZ	W6, #1

(2327) 0x4abafc STR	W6, [SP, #160]

(2327) 0x4abb00 ADD	X1, X3, #1

(2327) 0x4abb04 STR	X1, [SP, #120]

(2327) 0x4abb08 ORR	X3, XZR, X20

(2327) 0x4abb0c STR	XZR, [X3], #8

(2327) 0x4abb10 LDR	X13, [X3]

(2327) 0x4abb14 LDR	X4, [SP, #104]

(2327) 0x4abb18 CMP	X4, X13

(2327) 0x4abb1c B.GT	4abb34

(2327) 0x4abb20 LDR	X15, [SP, #120]

(2327) 0x4abb24 MOVZ	W9, #1

(2327) 0x4abb28 STR	W9, [SP, #160]

(2327) 0x4abb2c ADD	X0, X15, #1

(2327) 0x4abb30 STR	X0, [SP, #120]

(2327) 0x4abb34 STR	XZR, [X3], #8

(2327) 0x4abb38 LDR	X11, [X3]

(2327) 0x4abb3c LDR	X1, [SP, #104]

(2327) 0x4abb40 CMP	X1, X11

(2327) 0x4abb44 B.GT	4abb5c

(2327) 0x4abb48 LDR	X6, [SP, #120]

(2327) 0x4abb4c MOVZ	W4, #1

(2327) 0x4abb50 STR	W4, [SP, #160]

(2327) 0x4abb54 ADD	X13, X6, #1

(2327) 0x4abb58 STR	X13, [SP, #120]

(2327) 0x4abb5c STR	XZR, [X3], #8

(2327) 0x4abb60 LDR	X15, [X3]

(2327) 0x4abb64 LDR	X0, [SP, #104]

(2327) 0x4abb68 CMP	X0, X15

(2327) 0x4abb6c B.GT	4abb84

(2327) 0x4abb70 LDR	X9, [SP, #120]

(2327) 0x4abb74 MOVZ	W1, #1

(2327) 0x4abb78 STR	W1, [SP, #160]

(2327) 0x4abb7c ADD	X11, X9, #1

(2327) 0x4abb80 STR	X11, [SP, #120]

(2327) 0x4abb84 STR	XZR, [X3], #8

(2327) 0x4abb88 LDR	X6, [X3]

(2327) 0x4abb8c LDR	X13, [SP, #104]

(2327) 0x4abb90 CMP	X13, X6

(2327) 0x4abb94 B.GT	4abbac

(2327) 0x4abb98 LDR	X4, [SP, #120]

(2327) 0x4abb9c MOVZ	W0, #1

(2327) 0x4abba0 STR	W0, [SP, #160]

(2327) 0x4abba4 ADD	X15, X4, #1

(2327) 0x4abba8 STR	X15, [SP, #120]

(2327) 0x4abbac STR	XZR, [X3], #8

(2327) 0x4abbb0 LDR	X9, [X3]

(2327) 0x4abbb4 LDR	X11, [SP, #104]

(2327) 0x4abbb8 CMP	X11, X9

(2327) 0x4abbbc B.GT	4abbd4

(2327) 0x4abbc0 LDR	X1, [SP, #120]

(2327) 0x4abbc4 MOVZ	W13, #1

(2327) 0x4abbc8 STR	W13, [SP, #160]

(2327) 0x4abbcc ADD	X6, X1, #1

(2327) 0x4abbd0 STR	X6, [SP, #120]

(2327) 0x4abbd4 STR	XZR, [X3], #8

(2327) 0x4abbd8 LDR	X15, [X3]

(2327) 0x4abbdc LDR	X4, [SP, #104]

(2327) 0x4abbe0 CMP	X4, X15

(2327) 0x4abbe4 B.GT	4abbfc

(2327) 0x4abbe8 LDR	X0, [SP, #120]

(2327) 0x4abbec MOVZ	W11, #1

(2327) 0x4abbf0 STR	W11, [SP, #160]

(2327) 0x4abbf4 ADD	X9, X0, #1

(2327) 0x4abbf8 STR	X9, [SP, #120]

(2327) 0x4abbfc STR	XZR, [X3], #8

(2327) 0x4abc00 CMP	X14, X3

(2327) 0x4abc04 B.EQ	4abcec

(2327) 0x4abc08 LDR	W9, [SP, #160]

(2327) 0x4abc0c LDR	X1, [SP, #104]

(2327) 0x4abc10 LDR	X6, [SP, #120]

  (2328) 0x4abc14 LDR	X13, [X3]

  (2328) 0x4abc18 CMP	X1, X13

  (2328) 0x4abc1c B.GT	4abc28

  (2328) 0x4abc20 ADD	X6, X6, #1

  (2328) 0x4abc24 MOVZ	W9, #1

  (2328) 0x4abc28 ORR	X15, XZR, X3

  (2328) 0x4abc2c STR	XZR, [X15], #8

  (2328) 0x4abc30 LDR	X3, [X3, #8]

  (2328) 0x4abc34 CMP	X1, X3

  (2328) 0x4abc38 B.GT	4abc44

  (2328) 0x4abc3c ADD	X6, X6, #1

  (2328) 0x4abc40 MOVZ	W9, #1

  (2328) 0x4abc44 LDR	X4, [X15, #8]

  (2328) 0x4abc48 STR	XZR, [X15]

  (2328) 0x4abc4c CMP	X1, X4

  (2328) 0x4abc50 B.GT	4abc5c

  (2328) 0x4abc54 ADD	X6, X6, #1

  (2328) 0x4abc58 MOVZ	W9, #1

  (2328) 0x4abc5c LDR	X0, [X15, #16]

  (2328) 0x4abc60 STR	XZR, [X15, #8]

  (2328) 0x4abc64 CMP	X1, X0

  (2328) 0x4abc68 B.GT	4abc74

  (2328) 0x4abc6c ADD	X6, X6, #1

  (2328) 0x4abc70 MOVZ	W9, #1

  (2328) 0x4abc74 LDR	X11, [X15, #24]

  (2328) 0x4abc78 STR	XZR, [X15, #16]

  (2328) 0x4abc7c CMP	X1, X11

  (2328) 0x4abc80 B.GT	4abc8c

  (2328) 0x4abc84 ADD	X6, X6, #1

  (2328) 0x4abc88 MOVZ	W9, #1

  (2328) 0x4abc8c LDR	X13, [X15, #32]

  (2328) 0x4abc90 STR	XZR, [X15, #24]

  (2328) 0x4abc94 CMP	X1, X13

  (2328) 0x4abc98 B.GT	4abca4

  (2328) 0x4abc9c ADD	X6, X6, #1

  (2328) 0x4abca0 MOVZ	W9, #1

  (2328) 0x4abca4 LDR	X3, [X15, #40]

  (2328) 0x4abca8 STR	XZR, [X15, #32]

  (2328) 0x4abcac CMP	X1, X3

  (2328) 0x4abcb0 B.GT	4abcbc

  (2328) 0x4abcb4 ADD	X6, X6, #1

  (2328) 0x4abcb8 MOVZ	W9, #1

  (2328) 0x4abcbc LDR	X4, [X15, #48]

  (2328) 0x4abcc0 STR	XZR, [X15, #40]

  (2328) 0x4abcc4 CMP	X1, X4

  (2328) 0x4abcc8 B.GT	4abcd4

  (2328) 0x4abccc ADD	X6, X6, #1

  (2328) 0x4abcd0 MOVZ	W9, #1

  (2328) 0x4abcd4 ADD	X3, X15, #56

  (2328) 0x4abcd8 STR	XZR, [X15, #48]

  (2328) 0x4abcdc CMP	X14, X3

  (2328) 0x4abce0 B.NE	4abc14

(2327) 0x4abce4 STR	X6, [SP, #120]

(2327) 0x4abce8 STR	W9, [SP, #160]

(2327) 0x4abcec LDR	X14, [SP, #136]

(2327) 0x4abcf0 ADD	X10, X10, #1

(2327) 0x4abcf4 CMP	X14, X10

(2327) 0x4abcf8 B.EQ	4abd7c

(2327) 0x4abcfc ORR	X1, XZR, X2

(2327) 0x4abd00 ORR	X4, XZR, X5

(2327) 0x4abd04 B	4ab568

0x4abd08 MOVZ	X19, #0

0x4abd0c CMP	X12, #0

0x4abd10 B.GT	4ab4a0

0x4abd14 B	4ab504

    (2330) 0x4abd18 SUB	X11, X2, X1

    (2330) 0x4abd1c STR	X2, [X19, X9,LSL #3]

    (2330) 0x4abd20 ADD	X0, X0, #1

    (2330) 0x4abd24 ADD	X2, X2, #1

    (2330) 0x4abd28 STR	X12, [X20, X11,LSL #3]

    (2330) 0x4abd2c LDR	X6, [X13]

    (2330) 0x4abd30 CMP	X0, X6

    (2330) 0x4abd34 B.LT	4ab7e8

  (2326) 0x4abd38 LDR	X13, [X15]

  (2326) 0x4abd3c ADD	X14, X14, #1

  (2326) 0x4abd40 CMP	X13, X14

  (2326) 0x4abd44 B.GT	4ab72c

(2327) 0x4abd48 B	4ab828

  (2326) 0x4abd4c SUB	X0, X2, X1

  (2326) 0x4abd50 MOVZ	X6, #2

  (2326) 0x4abd54 STR	X2, [X19, X9,LSL #3]

  (2326) 0x4abd58 ADD	X2, X2, #1

  (2326) 0x4abd5c STR	X6, [X20, X0,LSL #3]

  (2326) 0x4abd60 B	4ab760

  (2332) 0x4abd64 SUB	X0, X5, X4

  (2332) 0x4abd68 STR	X5, [X21, X11,LSL #3]

  (2332) 0x4abd6c MOVZ	X11, #2

  (2332) 0x4abd70 ADD	X5, X5, #1

  (2332) 0x4abd74 STR	X11, [X22, X0,LSL #3]

  (2332) 0x4abd78 B	4ab600

0x4abd7c LDR	W2, [SP, #168]

0x4abd80 LDR	X12, [SP, #112]

0x4abd84 LDR	X5, [SP, #280]

0x4abd88 CBZ	W2, 4abd90

0x4abd8c STR	X12, [SP, #312]

0x4abd90 LDR	W16, [SP, #160]

0x4abd94 CBZ	W16, 4abda0

0x4abd98 LDR	X17, [SP, #120]

0x4abd9c STR	X17, [SP, #320]

0x4abda0 LDP	X6, X4, [SP, #240]

0x4abda4 ADD	X2, SP, #320

0x4abda8 ADD	X0, SP, #312

0x4abdac STP	X7, X8, [SP, #112]

0x4abdb0 LDR	X16, [X6]

0x4abdb4 STP	X18, X5, [SP, #152]

0x4abdb8 LDR	X7, [SP, #144]

0x4abdbc UBFM	X17, X16, #61, #60

0x4abdc0 LDR	X15, [SP, #192]

0x4abdc4 ADD	X1, X7, X17

0x4abdc8 ADD	X3, X15, X17

0x4abdcc BL	51a784

0x4abdd0 LDR	X2, [SP, #224]

0x4abdd4 MOVN	X4, #0

0x4abdd8 MOVZ	X0, #0

0x4abddc LDP	X13, X8, [SP, #112]

0x4abde0 LDP	X18, X12, [SP, #152]

0x4abde4 LDR	X10, [X2, #152]

0x4abde8 LDR	X1, [X10]

0x4abdec CMP	X1, #0

0x4abdf0 B.LE	4abe14

0x4abdf4 HINT	#0

0x4abdf8 HINT	#0

0x4abdfc HINT	#0

(2318) 0x4abe00 STR	X4, [X21, X0,LSL #3]

(2318) 0x4abe04 ADD	X0, X0, #1

(2318) 0x4abe08 LDR	X30, [X10]

(2318) 0x4abe0c CMP	X30, X0

(2318) 0x4abe10 B.GT	4abe00

0x4abe14 LDR	X14, [SP, #224]

0x4abe18 MOVN	X5, #0

0x4abe1c MOVZ	X11, #0

0x4abe20 LDR	X3, [X14, #88]

0x4abe24 LDR	X9, [X3]

0x4abe28 CMP	X9, #0

0x4abe2c B.LE	4abe44

(2317) 0x4abe30 STR	X5, [X19, X11,LSL #3]

(2317) 0x4abe34 ADD	X11, X11, #1

(2317) 0x4abe38 LDR	X15, [X3]

(2317) 0x4abe3c CMP	X15, X11

(2317) 0x4abe40 B.GT	4abe30

0x4abe44 STP	X13, X8, [SP, #112]

0x4abe48 STP	X18, X12, [SP, #152]

0x4abe4c BL	40f590

0x4abe50 BL	40f540

0x4abe54 LDP	X7, X8, [SP, #112]

0x4abe58 LDP	X18, X12, [SP, #152]

0x4abe5c CBNZ	W0, 4abe88

0x4abe60 LDR	X6, [SP, #224]

0x4abe64 LDR	X4, [SP, #144]

0x4abe68 LDR	X16, [X6, #152]

0x4abe6c LDR	X17, [X16]

0x4abe70 LDR	X13, [X4, X17,LSL #3]

0x4abe74 UBFM	X5, X17, #61, #60

0x4abe78 CBNZ	X13, 4ac964

0x4abe7c LDR	X0, [SP, #192]

0x4abe80 LDR	X30, [X0, X5]

0x4abe84 CBNZ	X30, 4ac940

0x4abe88 STP	X7, X8, [SP, #112]

0x4abe8c STP	X18, X12, [SP, #152]

0x4abe90 BL	40f590

0x4abe94 LDR	X3, [SP, #136]

0x4abe98 LDP	X18, X5, [SP, #152]

0x4abe9c LDP	X7, X8, [SP, #112]

0x4abea0 SUB	X11, X3, #1

0x4abea4 CMP	X5, X11

0x4abea8 B.GE	4ac05c

0x4abeac SUB	X15, X11, X5

0x4abeb0 ORR	X9, XZR, X5

0x4abeb4 LDP	X4, X13, [SP, #312]

0x4abeb8 ANDS	X16, X15, #4160

0x4abebc MOVZ	X17, #2

0x4abec0 LDR	X6, [SP, #144]

0x4abec4 LDR	X3, [SP, #192]

0x4abec8 ADD	X30, X6, #8

0x4abecc ADD	X12, X3, #8

0x4abed0 B.EQ	4abf88

0x4abed4 CMP	X16, #1

0x4abed8 B.EQ	4abf4c

0x4abedc CMP	X16, X17

0x4abee0 B.EQ	4abf18

0x4abee4 LDR	X9, [SP, #144]

0x4abee8 LDR	X10, [X30, X5,LSL #3]

0x4abeec LDR	X16, [X9, X5,LSL #3]

0x4abef0 CMP	X10, X16

0x4abef4 B.EQ	4ac908

0x4abef8 LDR	X10, [SP, #144]

0x4abefc ADD	X6, X4, X16

0x4abf00 ADD	X9, X5, #1

0x4abf04 LDR	X1, [SP, #192]

0x4abf08 STR	X6, [X10, X5,LSL #3]

0x4abf0c LDR	X0, [X1, X5,LSL #3]

0x4abf10 ADD	X14, X0, X13

0x4abf14 STR	X14, [X1, X5,LSL #3]

0x4abf18 LDR	X3, [SP, #144]

0x4abf1c LDR	X2, [X30, X9,LSL #3]

0x4abf20 LDR	X14, [X3, X9,LSL #3]

0x4abf24 CMP	X2, X14

0x4abf28 B.EQ	4acc10

0x4abf2c LDR	X3, [SP, #144]

0x4abf30 ADD	X2, X4, X14

0x4abf34 LDR	X15, [SP, #192]

0x4abf38 STR	X2, [X3, X9,LSL #3]

0x4abf3c LDR	X16, [X15, X9,LSL #3]

0x4abf40 ADD	X6, X16, X13

0x4abf44 STR	X6, [X15, X9,LSL #3]

0x4abf48 ADD	X9, X9, #1

0x4abf4c LDR	X1, [SP, #144]

0x4abf50 LDR	X10, [X30, X9,LSL #3]

0x4abf54 LDR	X6, [X1, X9,LSL #3]

0x4abf58 CMP	X10, X6

0x4abf5c B.EQ	4ac8dc

0x4abf60 LDR	X1, [SP, #144]

0x4abf64 ADD	X10, X4, X6

0x4abf68 LDR	X3, [SP, #192]

0x4abf6c STR	X10, [X1, X9,LSL #3]

0x4abf70 LDR	X14, [X3, X9,LSL #3]

0x4abf74 ADD	X2, X14, X13

0x4abf78 STR	X2, [X3, X9,LSL #3]

0x4abf7c ADD	X9, X9, #1

0x4abf80 CMP	X9, X11

0x4abf84 B.EQ	4ac060

0x4abf88 LDR	X15, [SP, #128]

0x4abf8c LDR	X6, [SP, #144]

0x4abf90 B	4ac02c

(2316) 0x4abf94 ADD	X2, X4, X14

(2316) 0x4abf98 ADD	X1, X9, #1

(2316) 0x4abf9c STR	X2, [X6, X9,LSL #3]

(2316) 0x4abfa0 LDR	X16, [X3, X9,LSL #3]

(2316) 0x4abfa4 ADD	X10, X16, X13

(2316) 0x4abfa8 STR	X10, [X3, X9,LSL #3]

(2316) 0x4abfac LDR	X16, [X6, X1,LSL #3]

(2316) 0x4abfb0 LDR	X0, [X30, X1,LSL #3]

(2316) 0x4abfb4 CMP	X0, X16

(2316) 0x4abfb8 B.EQ	4ac584

(2316) 0x4abfbc ADD	X10, X4, X16

(2316) 0x4abfc0 ADD	X0, X1, #1

(2316) 0x4abfc4 STR	X10, [X6, X1,LSL #3]

(2316) 0x4abfc8 LDR	X14, [X3, X1,LSL #3]

(2316) 0x4abfcc ADD	X2, X14, X13

(2316) 0x4abfd0 STR	X2, [X3, X1,LSL #3]

(2316) 0x4abfd4 LDR	X2, [X6, X0,LSL #3]

(2316) 0x4abfd8 LDR	X9, [X30, X0,LSL #3]

(2316) 0x4abfdc CMP	X9, X2

(2316) 0x4abfe0 B.EQ	4ac564

(2316) 0x4abfe4 ADD	X9, X4, X2

(2316) 0x4abfe8 ADD	X10, X1, #2

(2316) 0x4abfec STR	X9, [X6, X0,LSL #3]

(2316) 0x4abff0 LDR	X16, [X3, X0,LSL #3]

(2316) 0x4abff4 ADD	X14, X16, X13

(2316) 0x4abff8 STR	X14, [X3, X0,LSL #3]

(2316) 0x4abffc LDR	X14, [X6, X10,LSL #3]

(2316) 0x4ac000 LDR	X0, [X30, X10,LSL #3]

(2316) 0x4ac004 CMP	X0, X14

(2316) 0x4ac008 B.EQ	4ac544

(2316) 0x4ac00c ADD	X0, X4, X14

(2316) 0x4ac010 ADD	X9, X1, #3

(2316) 0x4ac014 STR	X0, [X6, X10,LSL #3]

(2316) 0x4ac018 LDR	X1, [X3, X10,LSL #3]

(2316) 0x4ac01c ADD	X2, X1, X13

(2316) 0x4ac020 STR	X2, [X3, X10,LSL #3]

(2316) 0x4ac024 CMP	X9, X11

(2316) 0x4ac028 B.EQ	4ac060

(2316) 0x4ac02c LDR	X14, [X6, X9,LSL #3]

(2316) 0x4ac030 LDR	X16, [X30, X9,LSL #3]

(2316) 0x4ac034 CMP	X16, X14

(2316) 0x4ac038 B.NE	4abf94

(2316) 0x4ac03c LDR	X1, [X12, X9,LSL #3]

(2316) 0x4ac040 LDR	X10, [X3, X9,LSL #3]

(2316) 0x4ac044 CMP	X1, X10

(2316) 0x4ac048 B.NE	4abf94

(2316) 0x4ac04c LDR	X0, [X15, X9,LSL #3]

(2316) 0x4ac050 STR	X17, [X23, X0,LSL #3]

(2316) 0x4ac054 LDR	X14, [X6, X9,LSL #3]

(2316) 0x4ac058 B	4abf94

0x4ac05c ORR	X11, XZR, X5

0x4ac060 LDR	X17, [SP, #136]

0x4ac064 CMP	X5, X17

0x4ac068 B.GE	4ac4a8

0x4ac06c LDR	X13, [SP, #144]

0x4ac070 LDP	X3, X1, [SP, #312]

0x4ac074 LDR	X10, [X13, X11,LSL #3]

0x4ac078 LDR	X30, [SP, #192]

0x4ac07c LDR	X4, [SP, #272]

0x4ac080 ADD	X16, X10, X3

0x4ac084 LDR	X12, [SP, #248]

0x4ac088 STR	X16, [X13, X11,LSL #3]

0x4ac08c LDR	X14, [X30, X11,LSL #3]

0x4ac090 UBFM	X15, X4, #60, #59

0x4ac094 ADD	X6, X12, X15

0x4ac098 ADD	X0, X1, X14

0x4ac09c STR	X0, [X30, X11,LSL #3]

0x4ac0a0 LDR	X2, [X6, #8]

0x4ac0a4 LDR	X9, [X12, X15]

0x4ac0a8 LDR	X17, [X13, X11,LSL #3]

0x4ac0ac CMP	X2, X0

0x4ac0b0 CCMP	X9, X17, #0, #0

0x4ac0b4 B.EQ	4acc3c

0x4ac0b8 LDR	X4, [SP, #104]

0x4ac0bc LDR	X12, [SP, #224]

0x4ac0c0 LDR	X30, [X12, #64]

0x4ac0c4 LDR	X16, [X12, #80]

0x4ac0c8 CMP	X4, #1

0x4ac0cc B.EQ	4ac994

0x4ac0d0 STP	X16, X30, [SP, #112]

0x4ac0d4 MOVZ	X11, #1

0x4ac0d8 LDR	X30, [SP, #232]

0x4ac0dc LDP	X15, X12, [SP, #256]

  (2302) 0x4ac0e0 ORR	X2, XZR, X1

  (2302) 0x4ac0e4 ORR	X6, XZR, X3

  (2302) 0x4ac0e8 LDR	X10, [SP, #128]

  (2302) 0x4ac0ec LDR	X14, [X10, X5,LSL #3]

  (2302) 0x4ac0f0 UBFM	X0, X14, #61, #60

  (2302) 0x4ac0f4 LDR	X16, [X18, X14,LSL #3]

  (2302) 0x4ac0f8 ADD	X9, X0, #8

  (2302) 0x4ac0fc STR	X14, [SP, #152]

  (2302) 0x4ac100 LDR	X17, [X18, X9]

  (2302) 0x4ac104 ADD	X13, X18, X9

  (2302) 0x4ac108 STR	X9, [SP, #144]

  (2302) 0x4ac10c CMP	X16, X17

  (2302) 0x4ac110 B.GE	4ac5a4

  (2302) 0x4ac114 STR	X27, [SP, #160]

  (2302) 0x4ac118 ORR	X27, XZR, X13

  (2302) 0x4ac11c HINT	#0

    (2305) 0x4ac120 LDR	X14, [X26, X16,LSL #3]

    (2305) 0x4ac124 LDR	X0, [X23, X14,LSL #3]

    (2305) 0x4ac128 UBFM	X9, X14, #61, #60

    (2305) 0x4ac12c CMP	X0, #0

    (2305) 0x4ac130 B.LE	4ac154

    (2305) 0x4ac134 LDR	X13, [X8, X14,LSL #3]

    (2305) 0x4ac138 LDR	X4, [X21, X13,LSL #3]

    (2305) 0x4ac13c CMP	X4, X3

    (2305) 0x4ac140 B.LT	4ac50c

    (2305) 0x4ac144 SUB	X17, X4, X3

    (2305) 0x4ac148 LDR	X10, [X22, X17,LSL #3]

    (2305) 0x4ac14c ADD	X0, X10, #2

    (2305) 0x4ac150 STR	X0, [X22, X17,LSL #3]

    (2305) 0x4ac154 ADD	X13, X9, #8

    (2305) 0x4ac158 LDR	X0, [X18, X14,LSL #3]

    (2305) 0x4ac15c ADD	X17, X18, X13

    (2305) 0x4ac160 LDR	X10, [X18, X13]

    (2305) 0x4ac164 CMP	X0, X10

    (2305) 0x4ac168 B.LT	4ac190

    (2305) 0x4ac16c B	4ac1e0

      (2307) 0x4ac170 SUB	X9, X10, X3

      (2307) 0x4ac174 LDR	X4, [X22, X9,LSL #3]

      (2307) 0x4ac178 ADD	X10, X4, #1

      (2307) 0x4ac17c STR	X10, [X22, X9,LSL #3]

      (2307) 0x4ac180 LDR	X10, [X17]

      (2307) 0x4ac184 ADD	X0, X0, #1

      (2307) 0x4ac188 CMP	X0, X10

      (2307) 0x4ac18c B.GE	4ac1e0

      (2307) 0x4ac190 LDR	X4, [X26, X0,LSL #3]

      (2307) 0x4ac194 LDR	X9, [X23, X4,LSL #3]

      (2307) 0x4ac198 CMP	X9, #0

      (2307) 0x4ac19c B.LE	4ac184

      (2307) 0x4ac1a0 LDR	X4, [X8, X4,LSL #3]

      (2307) 0x4ac1a4 CMP	X4, X5

      (2307) 0x4ac1a8 B.EQ	4ac184

      (2307) 0x4ac1ac LDR	X10, [X21, X4,LSL #3]

      (2307) 0x4ac1b0 CMP	X10, X3

      (2307) 0x4ac1b4 B.GE	4ac170

      (2307) 0x4ac1b8 SUB	X9, X6, X3

      (2307) 0x4ac1bc STR	X6, [X21, X4,LSL #3]

      (2307) 0x4ac1c0 ADD	X0, X0, #1

      (2307) 0x4ac1c4 ADD	X6, X6, #1

      (2307) 0x4ac1c8 STR	X4, [X15, X9,LSL #3]

      (2307) 0x4ac1cc STR	X11, [X22, X9,LSL #3]

      (2307) 0x4ac1d0 LDR	X10, [X17]

      (2307) 0x4ac1d4 CMP	X0, X10

      (2307) 0x4ac1d8 B.LT	4ac190

    (2305) 0x4ac1dc HINT	#0

    (2305) 0x4ac1e0 LDR	X0, [X30, X14,LSL #3]

    (2305) 0x4ac1e4 ADD	X14, X30, X13

    (2305) 0x4ac1e8 LDR	X13, [X30, X13]

    (2305) 0x4ac1ec CMP	X0, X13

    (2305) 0x4ac1f0 B.LT	4ac218

    (2305) 0x4ac1f4 B	4ac25c

      (2306) 0x4ac1f8 SUB	X17, X9, X1

      (2306) 0x4ac1fc LDR	X10, [X20, X17,LSL #3]

      (2306) 0x4ac200 ADD	X4, X10, #1

      (2306) 0x4ac204 STR	X4, [X20, X17,LSL #3]

      (2306) 0x4ac208 LDR	X13, [X14]

      (2306) 0x4ac20c ADD	X0, X0, #1

      (2306) 0x4ac210 CMP	X0, X13

      (2306) 0x4ac214 B.GE	4ac25c

      (2306) 0x4ac218 LDR	X17, [X25, X0,LSL #3]

      (2306) 0x4ac21c LDR	X4, [X24, X17,LSL #3]

      (2306) 0x4ac220 CMP	X4, #0

      (2306) 0x4ac224 B.LE	4ac20c

      (2306) 0x4ac228 LDR	X13, [X7, X17,LSL #3]

      (2306) 0x4ac22c LDR	X9, [X19, X13,LSL #3]

      (2306) 0x4ac230 CMP	X9, X1

      (2306) 0x4ac234 B.GE	4ac1f8

      (2306) 0x4ac238 SUB	X9, X2, X1

      (2306) 0x4ac23c STR	X2, [X19, X13,LSL #3]

      (2306) 0x4ac240 ADD	X0, X0, #1

      (2306) 0x4ac244 ADD	X2, X2, #1

      (2306) 0x4ac248 STR	X13, [X12, X9,LSL #3]

      (2306) 0x4ac24c STR	X11, [X20, X9,LSL #3]

      (2306) 0x4ac250 LDR	X13, [X14]

      (2306) 0x4ac254 CMP	X0, X13

      (2306) 0x4ac258 B.LT	4ac218

    (2305) 0x4ac25c LDR	X14, [X27]

    (2305) 0x4ac260 ADD	X16, X16, #1

    (2305) 0x4ac264 CMP	X14, X16

    (2305) 0x4ac268 B.GT	4ac120

  (2302) 0x4ac26c LDR	X10, [SP, #144]

  (2302) 0x4ac270 LDP	X17, X27, [SP, #152]

  (2302) 0x4ac274 LDR	X4, [X30, X10]

  (2302) 0x4ac278 LDR	X16, [X30, X17,LSL #3]

  (2302) 0x4ac27c ADD	X17, X30, X10

  (2302) 0x4ac280 CMP	X16, X4

  (2302) 0x4ac284 B.GE	4ac3a4

  (2302) 0x4ac288 STP	X8, X30, [SP, #144]

  (2302) 0x4ac28c LDR	X14, [SP, #208]

  (2302) 0x4ac290 LDR	X30, [SP, #216]

  (2302) 0x4ac294 HINT	#0

  (2302) 0x4ac298 HINT	#0

  (2302) 0x4ac29c HINT	#0

    (2301) 0x4ac2a0 LDR	X13, [X25, X16,LSL #3]

    (2301) 0x4ac2a4 LDR	X8, [X24, X13,LSL #3]

    (2301) 0x4ac2a8 UBFM	X9, X13, #61, #60

    (2301) 0x4ac2ac CMP	X8, #0

    (2301) 0x4ac2b0 B.LE	4ac2d4

    (2301) 0x4ac2b4 LDR	X0, [X7, X13,LSL #3]

    (2301) 0x4ac2b8 LDR	X10, [X19, X0,LSL #3]

    (2301) 0x4ac2bc CMP	X10, X1

    (2301) 0x4ac2c0 B.LT	4ac528

    (2301) 0x4ac2c4 SUB	X4, X10, X1

    (2301) 0x4ac2c8 LDR	X8, [X20, X4,LSL #3]

    (2301) 0x4ac2cc ADD	X0, X8, #2

    (2301) 0x4ac2d0 STR	X0, [X20, X4,LSL #3]

    (2301) 0x4ac2d4 ADD	X9, X9, #8

    (2301) 0x4ac2d8 LDR	X0, [X30, X13,LSL #3]

    (2301) 0x4ac2dc ADD	X10, X30, X9

    (2301) 0x4ac2e0 LDR	X8, [X30, X9]

    (2301) 0x4ac2e4 CMP	X0, X8

    (2301) 0x4ac2e8 B.LT	4ac310

    (2301) 0x4ac2ec B	4ac34c

      (2304) 0x4ac2f0 SUB	X8, X8, X3

      (2304) 0x4ac2f4 LDR	X4, [X22, X8,LSL #3]

      (2304) 0x4ac2f8 ADD	X4, X4, #1

      (2304) 0x4ac2fc STR	X4, [X22, X8,LSL #3]

      (2304) 0x4ac300 LDR	X8, [X10]

      (2304) 0x4ac304 ADD	X0, X0, #1

      (2304) 0x4ac308 CMP	X0, X8

      (2304) 0x4ac30c B.GE	4ac34c

      (2304) 0x4ac310 LDR	X4, [X28, X0,LSL #3]

      (2304) 0x4ac314 CMP	X4, X5

      (2304) 0x4ac318 B.EQ	4ac304

      (2304) 0x4ac31c LDR	X8, [X21, X4,LSL #3]

      (2304) 0x4ac320 CMP	X8, X3

      (2304) 0x4ac324 B.GE	4ac2f0

      (2304) 0x4ac328 SUB	X8, X6, X3

      (2304) 0x4ac32c STR	X6, [X21, X4,LSL #3]

      (2304) 0x4ac330 ADD	X0, X0, #1

      (2304) 0x4ac334 ADD	X6, X6, #1

      (2304) 0x4ac338 STR	X4, [X15, X8,LSL #3]

      (2304) 0x4ac33c STR	X11, [X22, X8,LSL #3]

      (2304) 0x4ac340 LDR	X8, [X10]

      (2304) 0x4ac344 CMP	X0, X8

      (2304) 0x4ac348 B.LT	4ac310

    (2301) 0x4ac34c LDR	X0, [X14, X13,LSL #3]

    (2301) 0x4ac350 ADD	X13, X14, X9

    (2301) 0x4ac354 LDR	X9, [X14, X9]

    (2301) 0x4ac358 CMP	X0, X9

    (2301) 0x4ac35c B.GE	4ac390

      (2303) 0x4ac360 LDR	X10, [X27, X0,LSL #3]

      (2303) 0x4ac364 LDR	X4, [X19, X10,LSL #3]

      (2303) 0x4ac368 CMP	X4, X1

      (2303) 0x4ac36c B.LT	4ac438

      (2303) 0x4ac370 SUB	X8, X4, X1

      (2303) 0x4ac374 ADD	X0, X0, #1

      (2303) 0x4ac378 LDR	X9, [X20, X8,LSL #3]

      (2303) 0x4ac37c ADD	X10, X9, #1

      (2303) 0x4ac380 STR	X10, [X20, X8,LSL #3]

      (2303) 0x4ac384 LDR	X4, [X13]

      (2303) 0x4ac388 CMP	X4, X0

      (2303) 0x4ac38c B.GT	4ac360

    (2301) 0x4ac390 LDR	X13, [X17]

    (2301) 0x4ac394 ADD	X16, X16, #1

    (2301) 0x4ac398 CMP	X13, X16

    (2301) 0x4ac39c B.GT	4ac2a0

  (2302) 0x4ac3a0 LDP	X8, X30, [SP, #144]

  (2302) 0x4ac3a4 SUB	X16, X6, X3

  (2302) 0x4ac3a8 MOVZ	X0, #0

  (2302) 0x4ac3ac UBFM	X17, X16, #61, #60

  (2302) 0x4ac3b0 CMP	X6, X3

  (2302) 0x4ac3b4 B.LE	4ac3e0

    (2299) 0x4ac3b8 HINT	#0

    (2299) 0x4ac3bc HINT	#0

    (2299) 0x4ac3c0 LDR	X3, [X22, X0]

    (2299) 0x4ac3c4 LDR	X14, [SP, #104]

    (2299) 0x4ac3c8 CMP	X14, X3

    (2299) 0x4ac3cc B.LE	4ac4e0

    (2299) 0x4ac3d0 STR	XZR, [X22, X0]

    (2299) 0x4ac3d4 ADD	X0, X0, #8

    (2299) 0x4ac3d8 CMP	X17, X0

    (2299) 0x4ac3dc B.NE	4ac3c0

  (2302) 0x4ac3e0 ORR	X3, XZR, X6

  (2302) 0x4ac3e4 SUB	X6, X2, X1

  (2302) 0x4ac3e8 MOVZ	X13, #0

  (2302) 0x4ac3ec UBFM	X16, X6, #61, #60

  (2302) 0x4ac3f0 CMP	X1, X2

  (2302) 0x4ac3f4 B.GE	4ac420

  (2302) 0x4ac3f8 HINT	#0

  (2302) 0x4ac3fc HINT	#0

    (2308) 0x4ac400 LDR	X1, [X20, X13]

    (2308) 0x4ac404 LDR	X17, [SP, #104]

    (2308) 0x4ac408 CMP	X17, X1

    (2308) 0x4ac40c B.LE	4ac470

    (2308) 0x4ac410 STR	XZR, [X20, X13]

    (2308) 0x4ac414 ADD	X13, X13, #8

    (2308) 0x4ac418 CMP	X16, X13

    (2308) 0x4ac41c B.NE	4ac400

  (2302) 0x4ac420 LDR	X0, [SP, #136]

  (2302) 0x4ac424 ADD	X5, X5, #1

  (2302) 0x4ac428 CMP	X0, X5

  (2302) 0x4ac42c B.EQ	4ac4a8

  (2302) 0x4ac430 ORR	X1, XZR, X2

  (2302) 0x4ac434 B	4ac0e0

      (2303) 0x4ac438 SUB	X8, X2, X1

      (2303) 0x4ac43c STR	X2, [X19, X10,LSL #3]

      (2303) 0x4ac440 ADD	X0, X0, #1

      (2303) 0x4ac444 ADD	X2, X2, #1

      (2303) 0x4ac448 STR	X10, [X12, X8,LSL #3]

      (2303) 0x4ac44c STR	X11, [X20, X8,LSL #3]

      (2303) 0x4ac450 LDR	X9, [X13]

      (2303) 0x4ac454 CMP	X0, X9

      (2303) 0x4ac458 B.LT	4ac360

    (2301) 0x4ac45c LDR	X13, [X17]

    (2301) 0x4ac460 ADD	X16, X16, #1

    (2301) 0x4ac464 CMP	X13, X16

    (2301) 0x4ac468 B.GT	4ac2a0

  (2302) 0x4ac46c B	4ac3a0

    (2308) 0x4ac470 LDR	X4, [SP, #320]

    (2308) 0x4ac474 LDR	X14, [X12, X13]

    (2308) 0x4ac478 LDR	X10, [SP, #112]

    (2308) 0x4ac47c ADD	X9, X4, #1

    (2308) 0x4ac480 STR	X9, [SP, #320]

    (2308) 0x4ac484 STR	X14, [X10, X4,LSL #3]

    (2308) 0x4ac488 STR	XZR, [X20, X13]

    (2308) 0x4ac48c ADD	X13, X13, #8

    (2308) 0x4ac490 CMP	X13, X16

    (2308) 0x4ac494 B.NE	4ac400

  (2302) 0x4ac498 LDR	X0, [SP, #136]

  (2302) 0x4ac49c ADD	X5, X5, #1

  (2302) 0x4ac4a0 CMP	X0, X5

  (2302) 0x4ac4a4 B.NE	4ac430

(2300) 0x4ac4a8 ADRP	X21,

(2300) 0x4ac4ac LDR	X19, [X21, #3848]

(2300) 0x4ac4b0 LDR	X2, [SP, #328]

(2300) 0x4ac4b4 LDR	X1, [X19]

(2300) 0x4ac4b8 SUBS	X2, X2, X1

(2300) 0x4ac4bc MOVZ	X1, #0

(2300) 0x4ac4c0 B.NE	4acc50

(2300) 0x4ac4c4 LDP	X19, X20, [SP, #16]

(2300) 0x4ac4c8 LDP	X21, X22, [SP, #32]

(2300) 0x4ac4cc LDP	X23, X24, [SP, #48]

(2300) 0x4ac4d0 LDP	X25, X26, [SP, #64]

(2300) 0x4ac4d4 LDP	X27, X28, [SP, #80]

(2300) 0x4ac4d8 LDP	X29, X30, [SP], #336

(2300) 0x4ac4dc RET

  (2298) 0x4ac4e0 LDR	X9, [SP, #312]

  (2298) 0x4ac4e4 LDR	X4, [X15, X0]

  (2298) 0x4ac4e8 LDR	X13, [SP, #120]

  (2298) 0x4ac4ec ADD	X10, X9, #1

  (2298) 0x4ac4f0 STR	X10, [SP, #312]

  (2298) 0x4ac4f4 STR	X4, [X13, X9,LSL #3]

  (2298) 0x4ac4f8 STR	XZR, [X22, X0]

  (2298) 0x4ac4fc ADD	X0, X0, #8

  (2298) 0x4ac500 CMP	X0, X17

  (2298) 0x4ac504 B.NE	4ac3c0

(2300) 0x4ac508 B	4ac3e0

    (2305) 0x4ac50c SUB	X17, X6, X3

    (2305) 0x4ac510 STR	X6, [X21, X13,LSL #3]

    (2305) 0x4ac514 ADD	X6, X6, #1

    (2305) 0x4ac518 STR	X13, [X15, X17,LSL #3]

    (2305) 0x4ac51c MOVZ	X13, #2

    (2305) 0x4ac520 STR	X13, [X22, X17,LSL #3]

    (2305) 0x4ac524 B	4ac154

    (2301) 0x4ac528 SUB	X10, X2, X1

    (2301) 0x4ac52c MOVZ	X4, #2

    (2301) 0x4ac530 STR	X2, [X19, X0,LSL #3]

    (2301) 0x4ac534 ADD	X2, X2, #1

    (2301) 0x4ac538 STR	X0, [X12, X10,LSL #3]

    (2301) 0x4ac53c STR	X4, [X20, X10,LSL #3]

    (2301) 0x4ac540 B	4ac2d4

(2316) 0x4ac544 LDR	X2, [X12, X10,LSL #3]

(2316) 0x4ac548 LDR	X16, [X3, X10,LSL #3]

(2316) 0x4ac54c CMP	X2, X16

(2316) 0x4ac550 B.NE	4ac00c

(2316) 0x4ac554 LDR	X9, [X15, X10,LSL #3]

(2316) 0x4ac558 STR	X17, [X23, X9,LSL #3]

(2316) 0x4ac55c LDR	X14, [X6, X10,LSL #3]

(2316) 0x4ac560 B	4ac00c

(2316) 0x4ac564 LDR	X16, [X12, X0,LSL #3]

(2316) 0x4ac568 LDR	X14, [X3, X0,LSL #3]

(2316) 0x4ac56c CMP	X16, X14

(2316) 0x4ac570 B.NE	4abfe4

(2316) 0x4ac574 LDR	X10, [X15, X0,LSL #3]

(2316) 0x4ac578 STR	X17, [X23, X10,LSL #3]

(2316) 0x4ac57c LDR	X2, [X6, X0,LSL #3]

(2316) 0x4ac580 B	4abfe4

(2316) 0x4ac584 LDR	X14, [X12, X1,LSL #3]

(2316) 0x4ac588 LDR	X2, [X3, X1,LSL #3]

(2316) 0x4ac58c CMP	X14, X2

(2316) 0x4ac590 B.NE	4abfbc

(2316) 0x4ac594 LDR	X9, [X15, X1,LSL #3]

(2316) 0x4ac598 STR	X17, [X23, X9,LSL #3]

(2316) 0x4ac59c LDR	X16, [X6, X1,LSL #3]

(2316) 0x4ac5a0 B	4abfbc

  (2302) 0x4ac5a4 LDR	X4, [SP, #144]

  (2302) 0x4ac5a8 LDR	X16, [SP, #152]

  (2302) 0x4ac5ac LDR	X10, [X30, X4]

  (2302) 0x4ac5b0 ADD	X17, X30, X4

  (2302) 0x4ac5b4 LDR	X16, [X30, X16,LSL #3]

  (2302) 0x4ac5b8 CMP	X10, X16

  (2302) 0x4ac5bc B.GT	4ac288

  (2302) 0x4ac5c0 B	4ac3e0

(2327) 0x4ac5c4 LDR	X11, [SP, #152]

(2327) 0x4ac5c8 LDR	X13, [SP, #184]

(2327) 0x4ac5cc LDR	X14, [X16, X11,LSL #3]

(2327) 0x4ac5d0 LDR	X3, [X16, X13]

(2327) 0x4ac5d4 ADD	X15, X16, X13

(2327) 0x4ac5d8 CMP	X3, X14

(2327) 0x4ac5dc B.GT	4ab72c

(2327) 0x4ac5e0 B	4aba88

0x4ac5e4 LDR	X0, [X2, #152]

0x4ac5e8 MOVZ	X20, #0

0x4ac5ec MOVZ	X22, #0

0x4ac5f0 STP	XZR, XZR, [SP, #256]

0x4ac5f4 LDR	X15, [X6]

0x4ac5f8 STR	X0, [SP, #240]

0x4ac5fc LDR	X12, [X0]

0x4ac600 B	4ab47c

0x4ac604 LDR	X30, [SP, #136]

0x4ac608 CMP	X5, X30

0x4ac60c B.GE	4abda0

0x4ac610 LDP	X16, X17, [SP, #208]

0x4ac614 ORR	X9, XZR, X5

0x4ac618 MOVZ	W30, #0

0x4ac61c MOVZ	X11, #0

0x4ac620 MOVZ	W13, #0

0x4ac624 MOVZ	X6, #0

0x4ac628 STP	X22, X20, [SP, #152]

0x4ac62c LDR	X15, [SP, #232]

0x4ac630 STR	X5, [SP, #168]

(2319) 0x4ac634 LDR	X20, [SP, #128]

(2319) 0x4ac638 LDR	X0, [SP, #144]

(2319) 0x4ac63c LDR	X3, [SP, #176]

(2319) 0x4ac640 LDR	X22, [X20, X9,LSL #3]

(2319) 0x4ac644 STR	X11, [X0, X9,LSL #3]

(2319) 0x4ac648 LDR	X10, [X3]

(2319) 0x4ac64c STR	X22, [SP, #120]

(2319) 0x4ac650 CBZ	X10, 4ac65c

(2319) 0x4ac654 LDR	X14, [SP, #192]

(2319) 0x4ac658 STR	X6, [X14, X9,LSL #3]

(2319) 0x4ac65c LDR	X12, [SP, #120]

(2319) 0x4ac660 ORR	X4, XZR, X11

(2319) 0x4ac664 ORR	X2, XZR, X6

(2319) 0x4ac668 UBFM	X5, X12, #61, #60

(2319) 0x4ac66c LDR	X14, [X18, X12,LSL #3]

(2319) 0x4ac670 ADD	X3, X5, #8

(2319) 0x4ac674 ORR	X5, XZR, X27

(2319) 0x4ac678 LDR	X1, [X18, X3]

(2319) 0x4ac67c ADD	X22, X18, X3

(2319) 0x4ac680 CMP	X14, X1

(2319) 0x4ac684 B.GE	4ac794

  (2323) 0x4ac688 LDR	X20, [X26, X14,LSL #3]

  (2323) 0x4ac68c LDR	X27, [X23, X20,LSL #3]

  (2323) 0x4ac690 UBFM	X10, X20, #61, #60

  (2323) 0x4ac694 CMP	X27, #0

  (2323) 0x4ac698 B.LE	4ac6b8

  (2323) 0x4ac69c LDR	X0, [X8, X20,LSL #3]

  (2323) 0x4ac6a0 LDR	X12, [X21, X0,LSL #3]

  (2323) 0x4ac6a4 CMP	X12, X11

  (2323) 0x4ac6a8 B.GE	4ac6b8

  (2323) 0x4ac6ac MOVZ	W30, #1

  (2323) 0x4ac6b0 STR	X4, [X21, X0,LSL #3]

  (2323) 0x4ac6b4 ADD	X4, X4, #1

  (2323) 0x4ac6b8 ADD	X12, X10, #8

  (2323) 0x4ac6bc LDR	X0, [X18, X20,LSL #3]

  (2323) 0x4ac6c0 ADD	X27, X18, X12

  (2323) 0x4ac6c4 LDR	X10, [X18, X12]

  (2323) 0x4ac6c8 CMP	X0, X10

  (2323) 0x4ac6cc B.GE	4ac730

  (2323) 0x4ac6d0 STR	X2, [SP, #112]

  (2323) 0x4ac6d4 HINT	#0

  (2323) 0x4ac6d8 HINT	#0

  (2323) 0x4ac6dc HINT	#0

    (2325) 0x4ac6e0 LDR	X1, [X26, X0,LSL #3]

    (2325) 0x4ac6e4 LDR	X2, [X23, X1,LSL #3]

    (2325) 0x4ac6e8 CMP	X2, #0

    (2325) 0x4ac6ec B.LE	4ac720

    (2325) 0x4ac6f0 LDR	X1, [X8, X1,LSL #3]

    (2325) 0x4ac6f4 CMP	X1, X9

    (2325) 0x4ac6f8 B.EQ	4ac720

    (2325) 0x4ac6fc LDR	X2, [X21, X1,LSL #3]

    (2325) 0x4ac700 CMP	X11, X2

    (2325) 0x4ac704 B.LE	4ac720

    (2325) 0x4ac708 STR	X4, [X21, X1,LSL #3]

    (2325) 0x4ac70c MOVZ	W30, #1

    (2325) 0x4ac710 ADD	X4, X4, #1

    (2325) 0x4ac714 LDR	X10, [X27]

    (2325) 0x4ac718 HINT	#0

    (2325) 0x4ac71c HINT	#0

    (2325) 0x4ac720 ADD	X0, X0, #1

    (2325) 0x4ac724 CMP	X0, X10

    (2325) 0x4ac728 B.LT	4ac6e0

  (2323) 0x4ac72c LDR	X2, [SP, #112]

  (2323) 0x4ac730 LDR	X0, [X15, X20,LSL #3]

  (2323) 0x4ac734 ADD	X20, X15, X12

  (2323) 0x4ac738 LDR	X10, [X15, X12]

  (2323) 0x4ac73c CMP	X0, X10

  (2323) 0x4ac740 B.GE	4ac780

    (2324) 0x4ac744 LDR	X27, [X25, X0,LSL #3]

    (2324) 0x4ac748 LDR	X12, [X24, X27,LSL #3]

    (2324) 0x4ac74c CMP	X12, #0

    (2324) 0x4ac750 B.LE	4ac774

    (2324) 0x4ac754 LDR	X1, [X7, X27,LSL #3]

    (2324) 0x4ac758 LDR	X27, [X19, X1,LSL #3]

    (2324) 0x4ac75c CMP	X27, X6

    (2324) 0x4ac760 B.GE	4ac774

    (2324) 0x4ac764 STR	X2, [X19, X1,LSL #3]

    (2324) 0x4ac768 MOVZ	W13, #1

    (2324) 0x4ac76c ADD	X2, X2, #1

    (2324) 0x4ac770 LDR	X10, [X20]

    (2324) 0x4ac774 ADD	X0, X0, #1

    (2324) 0x4ac778 CMP	X0, X10

    (2324) 0x4ac77c B.LT	4ac744

  (2323) 0x4ac780 LDR	X20, [X22]

  (2323) 0x4ac784 ADD	X14, X14, #1

  (2323) 0x4ac788 CMP	X20, X14

  (2323) 0x4ac78c B.GT	4ac688

(2319) 0x4ac790 ORR	X27, XZR, X5

(2319) 0x4ac794 LDR	X22, [SP, #120]

(2319) 0x4ac798 ADD	X20, X15, X3

(2319) 0x4ac79c LDR	X3, [X15, X3]

(2319) 0x4ac7a0 LDR	X14, [X15, X22,LSL #3]

(2319) 0x4ac7a4 CMP	X14, X3

(2319) 0x4ac7a8 B.GE	4ac874

  (2320) 0x4ac7ac LDR	X12, [X25, X14,LSL #3]

  (2320) 0x4ac7b0 LDR	X5, [X24, X12,LSL #3]

  (2320) 0x4ac7b4 UBFM	X10, X12, #61, #60

  (2320) 0x4ac7b8 CMP	X5, #0

  (2320) 0x4ac7bc B.LE	4ac7dc

  (2320) 0x4ac7c0 LDR	X0, [X7, X12,LSL #3]

  (2320) 0x4ac7c4 LDR	X1, [X19, X0,LSL #3]

  (2320) 0x4ac7c8 CMP	X1, X6

  (2320) 0x4ac7cc B.GE	4ac7dc

  (2320) 0x4ac7d0 MOVZ	W13, #1

  (2320) 0x4ac7d4 STR	X2, [X19, X0,LSL #3]

  (2320) 0x4ac7d8 ADD	X2, X2, #1

  (2320) 0x4ac7dc ADD	X10, X10, #8

  (2320) 0x4ac7e0 LDR	X0, [X17, X12,LSL #3]

  (2320) 0x4ac7e4 ADD	X22, X17, X10

  (2320) 0x4ac7e8 LDR	X3, [X17, X10]

  (2320) 0x4ac7ec CMP	X0, X3

  (2320) 0x4ac7f0 B.GE	4ac834

  (2320) 0x4ac7f4 HINT	#0

  (2320) 0x4ac7f8 HINT	#0

  (2320) 0x4ac7fc HINT	#0

    (2322) 0x4ac800 LDR	X1, [X28, X0,LSL #3]

    (2322) 0x4ac804 CMP	X1, X9

    (2322) 0x4ac808 B.EQ	4ac828

    (2322) 0x4ac80c LDR	X5, [X21, X1,LSL #3]

    (2322) 0x4ac810 CMP	X5, X11

    (2322) 0x4ac814 B.GE	4ac828

    (2322) 0x4ac818 STR	X4, [X21, X1,LSL #3]

    (2322) 0x4ac81c MOVZ	W30, #1

    (2322) 0x4ac820 ADD	X4, X4, #1

    (2322) 0x4ac824 LDR	X3, [X22]

    (2322) 0x4ac828 ADD	X0, X0, #1

    (2322) 0x4ac82c CMP	X0, X3

    (2322) 0x4ac830 B.LT	4ac800

  (2320) 0x4ac834 LDR	X1, [X16, X12,LSL #3]

  (2320) 0x4ac838 ADD	X12, X16, X10

  (2320) 0x4ac83c LDR	X5, [X16, X10]

  (2320) 0x4ac840 CMP	X1, X5

  (2320) 0x4ac844 B.GE	4ac864

    (2321) 0x4ac848 LDR	X10, [X27, X1,LSL #3]

    (2321) 0x4ac84c LDR	X22, [X19, X10,LSL #3]

    (2321) 0x4ac850 CMP	X22, X6

    (2321) 0x4ac854 B.LT	4ac890

    (2321) 0x4ac858 ADD	X1, X1, #1

    (2321) 0x4ac85c CMP	X1, X5

    (2321) 0x4ac860 B.LT	4ac848

  (2320) 0x4ac864 LDR	X3, [X20]

  (2320) 0x4ac868 ADD	X14, X14, #1

  (2320) 0x4ac86c CMP	X3, X14

  (2320) 0x4ac870 B.GT	4ac7ac

(2319) 0x4ac874 LDR	X11, [SP, #136]

(2319) 0x4ac878 ADD	X9, X9, #1

(2319) 0x4ac87c CMP	X11, X9

(2319) 0x4ac880 B.EQ	4ac8c0

(2319) 0x4ac884 ORR	X11, XZR, X4

(2319) 0x4ac888 ORR	X6, XZR, X2

(2319) 0x4ac88c B	4ac634

    (2321) 0x4ac890 STR	X2, [X19, X10,LSL #3]

    (2321) 0x4ac894 ADD	X1, X1, #1

    (2321) 0x4ac898 ADD	X2, X2, #1

    (2321) 0x4ac89c LDR	X5, [X12]

    (2321) 0x4ac8a0 MOVZ	W13, #1

    (2321) 0x4ac8a4 CMP	X1, X5

    (2321) 0x4ac8a8 B.LT	4ac848

  (2320) 0x4ac8ac LDR	X3, [X20]

  (2320) 0x4ac8b0 ADD	X14, X14, #1

  (2320) 0x4ac8b4 CMP	X3, X14

  (2320) 0x4ac8b8 B.GT	4ac7ac

(2319) 0x4ac8bc B	4ac874

0x4ac8c0 LDP	X22, X20, [SP, #152]

0x4ac8c4 LDR	X5, [SP, #168]

0x4ac8c8 CBZ	W30, 4ac8d0

0x4ac8cc STR	X4, [SP, #312]

0x4ac8d0 CBZ	W13, 4abda0

0x4ac8d4 STR	X2, [SP, #320]

0x4ac8d8 B	4abda0

0x4ac8dc LDR	X2, [SP, #192]

0x4ac8e0 LDR	X14, [X12, X9,LSL #3]

0x4ac8e4 LDR	X3, [X2, X9,LSL #3]

0x4ac8e8 CMP	X14, X3

0x4ac8ec B.NE	4abf60

0x4ac8f0 LDR	X0, [SP, #128]

0x4ac8f4 LDR	X16, [SP, #144]

0x4ac8f8 LDR	X15, [X0, X9,LSL #3]

0x4ac8fc STR	X17, [X23, X15,LSL #3]

0x4ac900 LDR	X6, [X16, X9,LSL #3]

0x4ac904 B	4abf60

0x4ac908 LDR	X1, [X12, X5,LSL #3]

0x4ac90c LDR	X14, [X3, X5,LSL #3]

0x4ac910 CMP	X1, X14

0x4ac914 B.NE	4abef8

0x4ac918 LDR	X2, [SP, #128]

0x4ac91c LDR	X15, [SP, #144]

0x4ac920 LDR	X3, [X2, X5,LSL #3]

0x4ac924 STR	X17, [X23, X3,LSL #3]

0x4ac928 LDR	X16, [X15, X5,LSL #3]

0x4ac92c B	4abef8

0x4ac930 MADD	X16, X3, X15, XZR

0x4ac934 MOVZ	X21, #0

0x4ac938 ADD	X19, X5, X16,LSL #3

0x4ac93c B	4ab4c8

0x4ac940 UBFM	X0, X30, #61, #60

0x4ac944 STP	X7, X8, [SP, #112]

0x4ac948 STP	X18, X12, [SP, #152]

0x4ac94c BL	51670c

0x4ac950 LDR	X14, [SP, #224]

0x4ac954 LDP	X7, X8, [SP, #112]

0x4ac958 LDP	X18, X12, [SP, #152]

0x4ac95c STR	X0, [X14, #80]

0x4ac960 B	4abe88

0x4ac964 UBFM	X0, X13, #61, #60

0x4ac968 STP	X7, X8, [SP, #112]

0x4ac96c STP	X18, X12, [SP, #152]

0x4ac970 BL	51670c

0x4ac974 LDR	X2, [SP, #224]

0x4ac978 LDP	X7, X8, [SP, #112]

0x4ac97c LDP	X18, X12, [SP, #152]

0x4ac980 STR	X0, [X2, #64]

0x4ac984 LDR	X10, [X2, #152]

0x4ac988 LDR	X1, [X10]

0x4ac98c UBFM	X5, X1, #61, #60

0x4ac990 B	4abe7c

0x4ac994 LDP	X13, X14, [SP, #208]

0x4ac998 LDR	X12, [SP, #232]

(2309) 0x4ac99c LDR	X20, [SP, #128]

(2309) 0x4ac9a0 LDR	X22, [X20, X5,LSL #3]

(2309) 0x4ac9a4 UBFM	X2, X22, #61, #60

(2309) 0x4ac9a8 LDR	X11, [X18, X22,LSL #3]

(2309) 0x4ac9ac ADD	X20, X2, #8

(2309) 0x4ac9b0 LDR	X15, [X18, X20]

(2309) 0x4ac9b4 ADD	X17, X18, X20

(2309) 0x4ac9b8 CMP	X15, X11

(2309) 0x4ac9bc B.LE	4acadc

  (2313) 0x4ac9c0 LDR	X10, [X26, X11,LSL #3]

  (2313) 0x4ac9c4 LDR	X6, [X23, X10,LSL #3]

  (2313) 0x4ac9c8 UBFM	X4, X10, #61, #60

  (2313) 0x4ac9cc CMP	X6, #0

  (2313) 0x4ac9d0 B.LE	4ac9fc

  (2313) 0x4ac9d4 LDR	X9, [X8, X10,LSL #3]

  (2313) 0x4ac9d8 LDR	X0, [X21, X9,LSL #3]

  (2313) 0x4ac9dc CMP	X0, X3

  (2313) 0x4ac9e0 B.GE	4ac9fc

  (2313) 0x4ac9e4 LDR	X2, [SP, #312]

  (2313) 0x4ac9e8 STR	X2, [X21, X9,LSL #3]

  (2313) 0x4ac9ec STR	X9, [X30, X2,LSL #3]

  (2313) 0x4ac9f0 LDR	X15, [SP, #312]

  (2313) 0x4ac9f4 ADD	X6, X15, #1

  (2313) 0x4ac9f8 STR	X6, [SP, #312]

  (2313) 0x4ac9fc ADD	X9, X4, #8

  (2313) 0x4aca00 LDR	X0, [X18, X10,LSL #3]

  (2313) 0x4aca04 ADD	X15, X18, X9

  (2313) 0x4aca08 LDR	X6, [X18, X9]

  (2313) 0x4aca0c CMP	X0, X6

  (2313) 0x4aca10 B.GE	4aca70

  (2313) 0x4aca14 HINT	#0

  (2313) 0x4aca18 HINT	#0

  (2313) 0x4aca1c HINT	#0

    (2315) 0x4aca20 LDR	X2, [X26, X0,LSL #3]

    (2315) 0x4aca24 LDR	X4, [X23, X2,LSL #3]

    (2315) 0x4aca28 CMP	X4, #0

    (2315) 0x4aca2c B.LE	4aca64

    (2315) 0x4aca30 LDR	X2, [X8, X2,LSL #3]

    (2315) 0x4aca34 CMP	X2, X5

    (2315) 0x4aca38 B.EQ	4aca64

    (2315) 0x4aca3c LDR	X4, [X21, X2,LSL #3]

    (2315) 0x4aca40 CMP	X4, X3

    (2315) 0x4aca44 B.GE	4aca64

    (2315) 0x4aca48 LDR	X6, [SP, #312]

    (2315) 0x4aca4c STR	X6, [X21, X2,LSL #3]

    (2315) 0x4aca50 STR	X2, [X30, X6,LSL #3]

    (2315) 0x4aca54 LDR	X2, [SP, #312]

    (2315) 0x4aca58 LDR	X6, [X15]

    (2315) 0x4aca5c ADD	X4, X2, #1

    (2315) 0x4aca60 STR	X4, [SP, #312]

    (2315) 0x4aca64 ADD	X0, X0, #1

    (2315) 0x4aca68 CMP	X0, X6

    (2315) 0x4aca6c B.LT	4aca20

  (2313) 0x4aca70 LDR	X0, [X12, X10,LSL #3]

  (2313) 0x4aca74 ADD	X10, X12, X9

  (2313) 0x4aca78 LDR	X6, [X12, X9]

  (2313) 0x4aca7c CMP	X6, X0

  (2313) 0x4aca80 B.LE	4acacc

    (2314) 0x4aca84 LDR	X9, [X25, X0,LSL #3]

    (2314) 0x4aca88 LDR	X15, [X24, X9,LSL #3]

    (2314) 0x4aca8c CMP	X15, #0

    (2314) 0x4aca90 B.LE	4acac0

    (2314) 0x4aca94 LDR	X2, [X7, X9,LSL #3]

    (2314) 0x4aca98 LDR	X4, [X19, X2,LSL #3]

    (2314) 0x4aca9c CMP	X4, X1

    (2314) 0x4acaa0 B.GE	4acac0

    (2314) 0x4acaa4 LDR	X6, [SP, #320]

    (2314) 0x4acaa8 STR	X6, [X19, X2,LSL #3]

    (2314) 0x4acaac STR	X2, [X16, X6,LSL #3]

    (2314) 0x4acab0 LDR	X9, [SP, #320]

    (2314) 0x4acab4 LDR	X6, [X10]

    (2314) 0x4acab8 ADD	X15, X9, #1

    (2314) 0x4acabc STR	X15, [SP, #320]

    (2314) 0x4acac0 ADD	X0, X0, #1

    (2314) 0x4acac4 CMP	X0, X6

    (2314) 0x4acac8 B.LT	4aca84

  (2313) 0x4acacc LDR	X10, [X17]

  (2313) 0x4acad0 ADD	X11, X11, #1

  (2313) 0x4acad4 CMP	X10, X11

  (2313) 0x4acad8 B.GT	4ac9c0

(2309) 0x4acadc LDR	X4, [X12, X22,LSL #3]

(2309) 0x4acae0 ADD	X22, X12, X20

(2309) 0x4acae4 LDR	X20, [X12, X20]

(2309) 0x4acae8 CMP	X20, X4

(2309) 0x4acaec B.LE	4acbcc

  (2310) 0x4acaf0 LDR	X6, [X25, X4,LSL #3]

  (2310) 0x4acaf4 LDR	X17, [X24, X6,LSL #3]

  (2310) 0x4acaf8 UBFM	X9, X6, #61, #60

  (2310) 0x4acafc CMP	X17, #0

  (2310) 0x4acb00 B.LE	4acb2c

  (2310) 0x4acb04 LDR	X15, [X7, X6,LSL #3]

  (2310) 0x4acb08 LDR	X2, [X19, X15,LSL #3]

  (2310) 0x4acb0c CMP	X2, X1

  (2310) 0x4acb10 B.GE	4acb2c

  (2310) 0x4acb14 LDR	X0, [SP, #320]

  (2310) 0x4acb18 STR	X0, [X19, X15,LSL #3]

  (2310) 0x4acb1c STR	X15, [X16, X0,LSL #3]

  (2310) 0x4acb20 LDR	X11, [SP, #320]

  (2310) 0x4acb24 ADD	X10, X11, #1

  (2310) 0x4acb28 STR	X10, [SP, #320]

  (2310) 0x4acb2c ADD	X20, X9, #8

  (2310) 0x4acb30 LDR	X0, [X14, X6,LSL #3]

  (2310) 0x4acb34 ADD	X17, X14, X20

  (2310) 0x4acb38 LDR	X11, [X14, X20]

  (2310) 0x4acb3c CMP	X11, X0

  (2310) 0x4acb40 B.LE	4acb84

    (2312) 0x4acb44 LDR	X15, [X28, X0,LSL #3]

    (2312) 0x4acb48 CMP	X15, X5

    (2312) 0x4acb4c B.EQ	4acb78

    (2312) 0x4acb50 LDR	X2, [X21, X15,LSL #3]

    (2312) 0x4acb54 CMP	X2, X3

    (2312) 0x4acb58 B.GE	4acb78

    (2312) 0x4acb5c LDR	X9, [SP, #312]

    (2312) 0x4acb60 STR	X9, [X21, X15,LSL #3]

    (2312) 0x4acb64 STR	X15, [X30, X9,LSL #3]

    (2312) 0x4acb68 LDR	X10, [SP, #312]

    (2312) 0x4acb6c LDR	X11, [X17]

    (2312) 0x4acb70 ADD	X15, X10, #1

    (2312) 0x4acb74 STR	X15, [SP, #312]

    (2312) 0x4acb78 ADD	X0, X0, #1

    (2312) 0x4acb7c CMP	X0, X11

    (2312) 0x4acb80 B.LT	4acb44

  (2310) 0x4acb84 LDR	X11, [X13, X6,LSL #3]

  (2310) 0x4acb88 ADD	X6, X13, X20

  (2310) 0x4acb8c LDR	X9, [X13, X20]

  (2310) 0x4acb90 CMP	X9, X11

  (2310) 0x4acb94 B.LE	4acbbc

  (2310) 0x4acb98 HINT	#0

  (2310) 0x4acb9c HINT	#0

    (2311) 0x4acba0 LDR	X20, [X27, X11,LSL #3]

    (2311) 0x4acba4 LDR	X17, [X19, X20,LSL #3]

    (2311) 0x4acba8 CMP	X17, X1

    (2311) 0x4acbac B.LT	4acbe4

    (2311) 0x4acbb0 ADD	X11, X11, #1

    (2311) 0x4acbb4 CMP	X11, X9

    (2311) 0x4acbb8 B.LT	4acba0

  (2310) 0x4acbbc LDR	X0, [X22]

  (2310) 0x4acbc0 ADD	X4, X4, #1

  (2310) 0x4acbc4 CMP	X0, X4

  (2310) 0x4acbc8 B.GT	4acaf0

(2309) 0x4acbcc LDR	X3, [SP, #136]

(2309) 0x4acbd0 ADD	X5, X5, #1

(2309) 0x4acbd4 CMP	X3, X5

(2309) 0x4acbd8 B.EQ	4ac4a8

(2309) 0x4acbdc LDP	X3, X1, [SP, #312]

(2309) 0x4acbe0 B	4ac99c

    (2311) 0x4acbe4 LDR	X2, [SP, #320]

    (2311) 0x4acbe8 ADD	X11, X11, #1

    (2311) 0x4acbec STR	X2, [X19, X20,LSL #3]

    (2311) 0x4acbf0 STR	X20, [X16, X2,LSL #3]

    (2311) 0x4acbf4 LDR	X10, [SP, #320]

    (2311) 0x4acbf8 LDR	X9, [X6]

    (2311) 0x4acbfc ADD	X15, X10, #1

    (2311) 0x4acc00 STR	X15, [SP, #320]

    (2311) 0x4acc04 CMP	X9, X11

    (2311) 0x4acc08 B.GT	4acba0

  (2310) 0x4acc0c B	4acbbc

0x4acc10 LDR	X16, [SP, #192]

0x4acc14 LDR	X15, [X12, X9,LSL #3]

0x4acc18 LDR	X6, [X16, X9,LSL #3]

0x4acc1c CMP	X15, X6

0x4acc20 B.NE	4abf2c

0x4acc24 LDR	X10, [SP, #128]

0x4acc28 LDR	X0, [SP, #144]

0x4acc2c LDR	X1, [X10, X9,LSL #3]

0x4acc30 STR	X17, [X23, X1,LSL #3]

0x4acc34 LDR	X14, [X0, X9,LSL #3]

0x4acc38 B	4abf2c

0x4acc3c LDR	X30, [SP, #128]

0x4acc40 MOVZ	X13, #2

0x4acc44 LDR	X11, [X30, X11,LSL #3]

0x4acc48 STR	X13, [X23, X11,LSL #3]

0x4acc4c B	4ac0b8

0x4acc50 BL	40f2e0

0x4acc54 HINT	#0

0x4acc58 HINT	#0

0x4acc5c HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	par_strength.c:1668-2230
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1668-1714,1720-1797,1806,1812-2000,2009-2083,2095,2106-2230.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 73.50 to 18.38 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 73.50 to 4.50 cycles (16.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 1416 bytes. The binary function is storing 704 bytes.

General properties

nb instructions	384
loop length	1536
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

47.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	27.00	27.00	28.25	28.25	28.25	28.25	0.00	0.00	0.00	0.00	73.50	73.17	73.33	33.50	33.50
cycles	27.00	27.00	28.25	28.25	28.25	28.25	0.00	0.00	0.00	0.00	73.50	73.17	73.33	33.50	33.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	47.13
Overall L1	73.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 73.50 cycles. At this rate:

20% of peak load performance is reached (19.27 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
19% of peak store performance is reached (9.58 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4ab340

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #688]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X2, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X1, <54f34c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X1, #3848]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X2, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X18, X26, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X5, [X2, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X7, [X2, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X2, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X2, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X3, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X3, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X7, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X18, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X9, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X5, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X23, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [X2, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X20, [X2, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X28, X10, [X2, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X11, X12, [X2, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X14, X19, [X2, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X12, X11, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [X2, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X14, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [X2, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X2, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X2, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X17, [X2, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X13, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X30, [X2, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X16, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X15, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X17, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X27, X24, [X2, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X30, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X21, X22, [X2, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
BL 519580 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X4, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, SP, #296	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X4, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 5195a0 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X1, X3, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X7, X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X6, [X2, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X6, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.LE 4ac5e4 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x12a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X2, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X20, X3, X15, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X12, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X10, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X11, X19, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X19, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X20, X21, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X11, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X13, X3, X12, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X14, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X21, X19, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X22, X22, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X21, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBZ X12, 4ab4f8 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X30, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X17, X3, X12, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X21, X30, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X15, 4abd08 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x9c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X1, X3, X15, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X19, X5, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4ab4c8 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X5, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ X6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ X12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4ab504 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x1c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
HINT #0
B 4ab504 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x1c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBNZ X15, 4ac930 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x15f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X21, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X4, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X5, [X4, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP XZR, XZR, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X14, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X15, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X3, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4ac604 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x12c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X16, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X5, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4abda0 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xa60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X30, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X17, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X10, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X30, XZR, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR WZR, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X5, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ X19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 4ab4a0 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 4ab504 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x1c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W2, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ W2, 4abd90 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xa50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X12, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W16, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ W16, 4abda0 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xa60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X17, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X17, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X6, X4, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X2, SP, #320	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, SP, #312	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X7, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X18, X5, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X7, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X17, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X15, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X7, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X15, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 51a784 <hypre_prefix_sum_pair>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVN X4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X13, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X18, X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X10, [X2, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4abe14 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xad4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
LDR X14, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVN X5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X3, [X14, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4abe44 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xb04>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X13, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X18, X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f590 <@plt_start@+0x3a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 40f540 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X7, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X18, X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CBNZ W0, 4abe88 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xb48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X6, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X6, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X4, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X5, X17, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBNZ X13, 4ac964 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x1624>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X0, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X30, 4ac940 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x1600>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X7, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X18, X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f590 <@plt_start@+0x3a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X3, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X18, X5, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X7, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SUB X11, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X5, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4ac05c <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xd1c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X15, X11, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X9, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X4, X13, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ANDS X16, X15, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MOVZ X17, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X6, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X30, X6, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.EQ 4abf88 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xc48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4abf4c <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xc0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X16, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4abf18 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xbd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X30, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X10, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4ac908 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x15c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, X4, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X6, [X10, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X1, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X0, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X14, [X1, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X30, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X3, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X2, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4acc10 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x18d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X3, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X4, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X15, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X2, [X3, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X15, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, X16, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X6, [X15, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X30, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X1, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X10, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4ac8dc <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x159c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X4, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X3, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [X1, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X3, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X14, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X2, [X3, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4ac060 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xd20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4ac02c <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xcec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X11, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X17, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X5, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4ac4a8 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x1168>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X3, X1, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X10, [X13, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X10, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X16, [X13, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X30, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X15, X4, #60, #59	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X12, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X1, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X0, [X30, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X2, [X6, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X12, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X13, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X9, X17, #0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.EQ 4acc3c <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x18fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X4, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X12, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X12, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4ac994 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x1654>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X16, X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X30, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X15, X12, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X0, [X2, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ X20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP XZR, XZR, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4ab47c <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X30, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X5, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4abda0 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xa60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X16, X17, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X9, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W30, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X22, X20, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X5, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X22, X20, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X5, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ W30, 4ac8d0 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x1590>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X4, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBZ W13, 4abda0 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xa60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X2, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4abda0 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xa60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X12, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X2, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X14, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 4abf60 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xc20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X0, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X17, [X23, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X6, [X16, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4abf60 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xc20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X12, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X3, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X1, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 4abef8 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xbb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X2, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X17, [X23, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X15, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4abef8 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xbb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X16, X3, X15, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVZ X21, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X19, X5, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4ab4c8 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X0, X30, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X7, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X18, X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 51670c <hypre_MAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X7, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X18, X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X0, [X14, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4abe88 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xb48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X0, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X7, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X18, X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 51670c <hypre_MAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X7, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X18, X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X0, [X2, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X2, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X5, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4abe7c <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xb3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X13, X14, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X12, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X12, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X16, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X15, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 4abf2c <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xbec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X17, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X0, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4abf2c <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xbec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X30, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ X13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X30, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X13, [X23, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4ac0b8 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xd78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 40f2e0 <@plt_start@+0xf0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Source file and lines	par_strength.c:1668-2230
Module	exec

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 73.50 to 4.50 cycles (16.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 1416 bytes. The binary function is storing 704 bytes.

General properties

nb instructions	384
loop length	1536
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

47.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	27.00	27.00	28.25	28.25	28.25	28.25	0.00	0.00	0.00	0.00	73.50	73.17	73.33	33.50	33.50
cycles	27.00	27.00	28.25	28.25	28.25	28.25	0.00	0.00	0.00	0.00	73.50	73.17	73.33	33.50	33.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	47.13
Overall L1	73.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 73.50 cycles. At this rate:

20% of peak load performance is reached (19.27 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
19% of peak store performance is reached (9.58 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4ab340

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #688]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X2, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X1, <54f34c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X1, #3848]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X2, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X18, X26, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X5, [X2, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X7, [X2, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X2, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X2, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X3, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X3, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X7, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X18, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X9, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X5, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X23, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [X2, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X20, [X2, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X28, X10, [X2, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X11, X12, [X2, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X14, X19, [X2, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X12, X11, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [X2, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X14, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [X2, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X2, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X2, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X17, [X2, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X13, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X30, [X2, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X16, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X15, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X17, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X27, X24, [X2, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X30, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X21, X22, [X2, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
BL 519580 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X4, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, SP, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, SP, #296	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X4, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 5195a0 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X1, X3, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X7, X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X6, [X2, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X6, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.LE 4ac5e4 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x12a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X2, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X20, X3, X15, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X12, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X10, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X11, X19, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X19, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X20, X21, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X11, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X13, X3, X12, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X14, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X21, X19, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X22, X22, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X21, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBZ X12, 4ab4f8 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X30, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X17, X3, X12, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X21, X30, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ X15, 4abd08 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x9c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X1, X3, X15, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X19, X5, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4ab4c8 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X5, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ X6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ X12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4ab504 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x1c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
HINT #0
B 4ab504 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x1c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBNZ X15, 4ac930 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x15f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X21, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X4, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X5, [X4, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP XZR, XZR, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X14, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X15, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X3, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4ac604 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x12c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X16, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X5, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4abda0 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xa60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X30, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X17, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X10, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR WZR, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X30, XZR, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X30, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR WZR, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X5, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ X19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 4ab4a0 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 4ab504 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x1c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W2, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ W2, 4abd90 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xa50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X12, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W16, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ W16, 4abda0 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xa60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X17, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X17, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X6, X4, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X2, SP, #320	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, SP, #312	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X7, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X18, X5, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X7, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X17, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X15, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X7, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X15, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 51a784 <hypre_prefix_sum_pair>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVN X4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X13, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X18, X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X10, [X2, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4abe14 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xad4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
LDR X14, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVN X5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X3, [X14, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4abe44 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xb04>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X13, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X18, X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f590 <@plt_start@+0x3a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 40f540 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X7, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X18, X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CBNZ W0, 4abe88 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xb48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X6, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X6, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X4, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X5, X17, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBNZ X13, 4ac964 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x1624>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X0, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X30, 4ac940 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x1600>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X7, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X18, X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f590 <@plt_start@+0x3a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X3, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X18, X5, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X7, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SUB X11, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X5, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4ac05c <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xd1c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X15, X11, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X9, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X4, X13, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ANDS X16, X15, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MOVZ X17, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X6, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X30, X6, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.EQ 4abf88 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xc48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4abf4c <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xc0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X16, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4abf18 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xbd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X30, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X10, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4ac908 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x15c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, X4, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X6, [X10, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X1, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X0, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X14, [X1, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X30, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X3, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X2, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4acc10 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x18d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X3, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X4, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X15, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X2, [X3, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X15, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, X16, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X6, [X15, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X30, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X1, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X10, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4ac8dc <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x159c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X4, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X3, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [X1, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X3, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X14, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X2, [X3, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4ac060 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xd20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4ac02c <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xcec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X11, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X17, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X5, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4ac4a8 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x1168>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X3, X1, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X10, [X13, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X10, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X16, [X13, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X30, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X15, X4, #60, #59	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X12, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X1, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X0, [X30, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X2, [X6, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X12, X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X13, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CCMP X9, X17, #0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.EQ 4acc3c <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x18fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X4, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X12, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X12, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4ac994 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x1654>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP X16, X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X30, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X15, X12, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X0, [X2, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ X20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP XZR, XZR, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4ab47c <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X30, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X5, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4abda0 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xa60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X16, X17, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X9, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W30, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X22, X20, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X5, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X22, X20, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X5, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ W30, 4ac8d0 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x1590>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X4, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBZ W13, 4abda0 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xa60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X2, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4abda0 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xa60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X12, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X2, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X14, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 4abf60 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xc20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X0, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X17, [X23, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X6, [X16, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4abf60 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xc20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X12, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X3, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X1, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 4abef8 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xbb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X2, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X17, [X23, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X15, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4abef8 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xbb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X16, X3, X15, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVZ X21, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X19, X5, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4ab4c8 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X0, X30, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X7, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X18, X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 51670c <hypre_MAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X7, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X18, X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X0, [X14, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4abe88 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xb48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X0, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X7, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X18, X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 51670c <hypre_MAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X7, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X18, X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X0, [X2, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X2, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X5, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4abe7c <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xb3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X13, X14, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X12, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X12, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X16, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X15, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 4abf2c <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xbec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X17, [X23, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X0, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4abf2c <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xbec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X30, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ X13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X30, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X13, [X23, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4ac0b8 <hypre_BoomerAMGCreate2ndS._omp_fn.7+0xd78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 40f2e0 <@plt_start@+0xf0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCreate2ndS._omp_fn.7–	1.84	0.7
○Loop 2336 - par_strength.c:1691-1693 - exec	0.34	0.11
○Loop 2318 - par_strength.c:1951-1953 - exec	0.03	0.01
▼Loop 2319 - par_strength.c:1714-1797 - exec–	0.01	0.01
▼Loop 2323 - par_strength.c:1731-1765 - exec–	0.11	0.04
○Loop 2325 - par_strength.c:1743-1752 - exec	0.62	0.2
○Loop 2324 - par_strength.c:1756-1765 - exec	0	0
▼Loop 2320 - par_strength.c:1770-1797 - exec–	0	0
○Loop 2322 - par_strength.c:1782-1788 - exec	0	0
○Loop 2321 - par_strength.c:1791-1797 - exec	0	0
○Loop 2335 - par_strength.c:1695-1697 - exec	0	0
▼Loop 2309 - par_strength.c:2000-2083 - exec–	0	0
▼Loop 2313 - par_strength.c:2011-2048 - exec–	0.1	0.03
○Loop 2315 - par_strength.c:2024-2034 - exec	0.63	0.21
○Loop 2314 - par_strength.c:2038-2048 - exec	0	0
▼Loop 2310 - par_strength.c:2053-2083 - exec–	0	0
○Loop 2312 - par_strength.c:2066-2073 - exec	0	0
○Loop 2311 - par_strength.c:2076-2083 - exec	0	0
○Loop 2317 - par_strength.c:1955-1957 - exec	0	0
▼Loop 2300 - par_strength.c:1668-2230 - exec–	0	0
▼Loop 2298 - par_strength.c:2216-2222 - exec–	0	0
○Loop 2299 - par_strength.c:2216-2222 - exec	0	0
▼Loop 2302 - par_strength.c:2095-2230 - exec–	0	0
○Loop 2308 - par_strength.c:2224-2230 - exec	0	0
▼Loop 2301 - par_strength.c:2163-2211 - exec–	0	0
○Loop 2304 - par_strength.c:2181-2195 - exec	0	0
○Loop 2303 - par_strength.c:2199-2211 - exec	0	0
▼Loop 2305 - par_strength.c:2106-2158 - exec–	0	0
○Loop 2306 - par_strength.c:2143-2158 - exec	0	0
○Loop 2307 - par_strength.c:2124-2139 - exec	0	0
▼Loop 2327 - par_strength.c:1806-1941 - exec–	0	0
○Loop 2328 - par_strength.c:1935-1941 - exec	0	0
▼Loop 2326 - par_strength.c:1877-1922 - exec–	0	0
○Loop 2330 - par_strength.c:1911-1922 - exec	0	0
○Loop 2331 - par_strength.c:1894-1907 - exec	0	0
○Loop 2329 - par_strength.c:1927-1933 - exec	0	0
▼Loop 2332 - par_strength.c:1823-1872 - exec–	0	0
○Loop 2334 - par_strength.c:1840-1854 - exec	0	0
○Loop 2333 - par_strength.c:1858-1872 - exec	0	0
○Loop 2316 - par_strength.c:1978-1984 - exec	0	0.01

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code