OV - exec - Function hypre_BoomerAMGBuildMultipass._omp

	Function: hypre_BoomerAMGBuildMultipass._omp_fn.10	Module: exec	Source: par_multi_interp.c:1737-1881 [...]	Coverage: 1.13%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1737 - 1881

--------------------------------------------------------------------------------

1737: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa,tmp_array,tmp_array_offd)

[...]

1746:              tmp_marker = NULL;

1747:              if (n_fine)

1748:              {    tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); }

1749:              tmp_marker_offd = NULL;

1750:              if (num_cols_offd)

1751:              {    tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); }

1752:              tmp_array = NULL;

1753:              if (n_coarse)

1754:              {    tmp_array = hypre_CTAlloc(HYPRE_Int,n_coarse); }

1755:              tmp_array_offd = NULL;

1756:              if (new_num_cols_offd > n_coarse_offd)

1757:              {    tmp_array_offd = hypre_CTAlloc(HYPRE_Int,new_num_cols_offd); }

1758:              else

1759:              {    tmp_array_offd = hypre_CTAlloc(HYPRE_Int,n_coarse_offd);}

1760:              for (i=0; i < n_fine; i++)

1761:              {    tmp_marker[i] = -1; }

1762:              for (i=0; i < num_cols_offd; i++)

1763:              {    tmp_marker_offd[i] = -1; }

1764:

1765:              /* Compute this thread's range of pass_length */

1766:              my_thread_num = hypre_GetThreadNum();

1767:              num_threads = hypre_NumActiveThreads();

1768:              thread_start = pass_pointer[pass] + (pass_length/num_threads)*my_thread_num;

1769:              if (my_thread_num == num_threads-1)

1770:              {  thread_stop = pass_pointer[pass] + pass_length; }

1771:              else

1772:              {  thread_stop = pass_pointer[pass] + (pass_length/num_threads)*(my_thread_num+1); }

1773:

1774:              for (i=thread_start; i < thread_stop; i++)

1775:              {

1776:                 i1 = pass_array[i];

1777:                 sum_C = 0;

1778:                 sum_N = 0;

1779:                 j_start = P_diag_start[i1];

1780:                 j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1781:                 cnt = P_diag_i[i1];

1782:                 for (j=j_start; j < j_end; j++)

1783:                 {

1784:                    k1 = P_diag_pass[pass][j];

1785:                tmp_array[k1] = cnt;

1786:                P_diag_data[cnt] = 0;

1787:                P_diag_j[cnt++] = k1;

1788:                 }

1789:                 j_start = P_offd_start[i1];

1790:                 j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1791:                 cnt_offd = P_offd_i[i1];

1792:                 for (j=j_start; j < j_end; j++)

1793:                 {

1794:                    k1 = P_offd_pass[pass][j];

1795:                tmp_array_offd[k1] = cnt_offd;

1796:                P_offd_data[cnt_offd] = 0;

1797:                P_offd_j[cnt_offd++] = k1;

1798:                 }

1799:                 for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1800:                 {

1801:                j1 = S_diag_j[j];

1802:                if (assigned[j1] == pass-1)

1803:                   tmp_marker[j1] = i1;

1804:                 }

1805:                 for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

1806:                 {

1807:                j1 = S_offd_j[j];

1808:                if (assigned_offd[j1] == pass-1)

1809:                   tmp_marker_offd[j1] = i1;

1810:                 }

1811:                 for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1812:                 {

1813:                j1 = A_diag_j[j];

1814:                if (tmp_marker[j1] == i1)

1815:                {

1816:                   for (k=P_diag_i[j1]; k < P_diag_i[j1+1]; k++)

1817:                   {

1818:                  k1 = P_diag_j[k];

1819:                      alfa = A_diag_data[j]*P_diag_data[k];

1820:                      P_diag_data[tmp_array[k1]] += alfa;

1821:                      sum_C += alfa;

1822:                      sum_N += alfa;

1823:                       }

1824:                   for (k=P_offd_i[j1]; k < P_offd_i[j1+1]; k++)

1825:                   {

1826:                  k1 = P_offd_j[k];

1827:                      alfa = A_diag_data[j]*P_offd_data[k];

1828:                      P_offd_data[tmp_array_offd[k1]] += alfa;

1829:                      sum_C += alfa;

1830:                      sum_N += alfa;

1831:                       }

1832:                    }

1833:                    else

1834:                    {

1835:                       if (CF_marker[j1] != -3 &&

1836:                 (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1837:                  sum_N += A_diag_data[j];

1838:                    }

1839:                 }

1840:                 for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

1841:                 {

1842:                if (col_offd_S_to_A)

1843:                   j1 = map_A_to_S[A_offd_j[j]];

1844:                else

1845:                   j1 = A_offd_j[j];

1846:

1847:                if (j1 > -1 && tmp_marker_offd[j1] == i1)

1848:                {

1849:                   j_start = Pext_start[j1];

1850:                   j_end = j_start+Pext_i[j1+1];

1851:                   for (k=j_start; k < j_end; k++)

1852:                   {

1853:                  k1 = Pext_pass[pass][k];

1854:                      alfa = A_offd_data[j]*Pext_data[k];

1855:                  if (k1 < 0)

1856:                         P_diag_data[tmp_array[-k1-1]] += alfa;

1857:                  else

1858:                         P_offd_data[tmp_array_offd[k1]] += alfa;

1859:                      sum_C += alfa;

1860:                      sum_N += alfa;

1861:                       }

1862:                    }

1863:                    else

1864:                    {

1865:                       if (CF_marker_offd[j1] != -3 &&

1866:                 (num_functions == 1 || dof_func_offd[j1] == dof_func[i1]))

1867:                  sum_N += A_offd_data[j];

1868:                    }

1869:                 }

1870:                 diagonal = A_diag_data[A_diag_i[i1]];

1871:                 if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1872:

1873:                 for (j=P_diag_i[i1]; j < P_diag_i[i1+1]; j++)

1874:                P_diag_data[j] *= alfa;

1875:                 for (j=P_offd_i[i1]; j < P_offd_i[i1+1]; j++)

1876:                P_offd_data[j] *= alfa;

1877:              }

1878:              hypre_TFree(tmp_marker);

1879:              hypre_TFree(tmp_marker_offd);

1880:              hypre_TFree(tmp_array);

1881:              hypre_TFree(tmp_array_offd);

0x44f6c4 STP	X29, X30, [SP, #640]!

0x44f6c8 ADD	X29, SP, #0

0x44f6cc LDR	X1, [X0, #80]

0x44f6d0 STP	X19, X20, [SP, #16]

0x44f6d4 LDR	X3, [X0, #88]

0x44f6d8 STP	X21, X22, [SP, #32]

0x44f6dc LDR	X4, [X0, #96]

0x44f6e0 STP	X23, X24, [SP, #48]

0x44f6e4 LDR	X5, [X0, #104]

0x44f6e8 STP	X25, X26, [SP, #64]

0x44f6ec LDR	X6, [X0, #112]

0x44f6f0 STP	X27, X28, [SP, #80]

0x44f6f4 LDR	X7, [X0, #128]

0x44f6f8 STR	X5, [SP, #112]

0x44f6fc LDR	X8, [X0, #152]

0x44f700 STR	X3, [SP, #120]

0x44f704 STR	X6, [SP, #136]

0x44f708 STR	X7, [SP, #152]

0x44f70c STR	X4, [SP, #232]

0x44f710 STR	X8, [SP, #144]

0x44f714 STR	X1, [SP, #240]

0x44f718 LDR	X20, [X0, #120]

0x44f71c LDP	X25, X19, [X0, #136]

0x44f720 LDR	X24, [X0, #160]

0x44f724 LDR	X2, [X0, #272]

0x44f728 LDP	X11, X12, [X0, #168]

0x44f72c LDP	X23, X22, [X0, #280]

0x44f730 STR	X11, [SP, #336]

0x44f734 LDR	X13, [X0, #184]

0x44f738 LDP	X10, X9, [X0, #296]

0x44f73c LDR	X14, [X0, #192]

0x44f740 STR	X13, [SP, #160]

0x44f744 LDR	X15, [X0, #200]

0x44f748 LDR	X16, [X0, #208]

0x44f74c STR	X14, [SP, #360]

0x44f750 LDR	X17, [X0, #216]

0x44f754 STR	X15, [SP, #176]

0x44f758 LDR	X18, [X0, #224]

0x44f75c STR	X16, [SP, #224]

0x44f760 LDR	X21, [X0, #232]

0x44f764 STR	X17, [SP, #216]

0x44f768 LDR	X26, [X0, #240]

0x44f76c STR	X18, [SP, #296]

0x44f770 LDR	X27, [X0, #248]

0x44f774 STR	X21, [SP, #288]

0x44f778 LDR	X28, [X0, #256]

0x44f77c STR	X26, [SP, #344]

0x44f780 LDR	X30, [X0, #264]

0x44f784 STR	X27, [SP, #328]

0x44f788 LDR	X1, [X0, #312]

0x44f78c STR	X28, [SP, #280]

0x44f790 LDR	X3, [X0, #320]

0x44f794 STR	X30, [SP, #184]

0x44f798 STR	X1, [SP, #272]

0x44f79c LDR	X4, [X0, #328]

0x44f7a0 LDR	X13, [X0]

0x44f7a4 LDR	X6, [X0, #8]

0x44f7a8 STR	X4, [SP, #168]

0x44f7ac LDR	X28, [X0, #16]

0x44f7b0 LDR	X7, [X0, #24]

0x44f7b4 STR	X6, [SP, #192]

0x44f7b8 LDR	X21, [X0, #32]

0x44f7bc LDR	X8, [X0, #40]

0x44f7c0 STR	X7, [SP, #320]

0x44f7c4 LDR	X11, [X0, #48]

0x44f7c8 LDR	X27, [X0, #56]

0x44f7cc STR	X8, [SP, #256]

0x44f7d0 LDR	X5, [X0, #72]

0x44f7d4 STR	X11, [SP, #312]

0x44f7d8 LDR	X0, [X0, #64]

0x44f7dc STR	X5, [SP, #304]

0x44f7e0 STR	X0, [SP, #248]

0x44f7e4 CBNZ	X2, 450754

0x44f7e8 MOVZ	X26, #0

0x44f7ec LDR	X0, [SP, #136]

0x44f7f0 CBNZ	X0, 450724

0x44f7f4 STR	XZR, [SP, #128]

0x44f7f8 CBNZ	X23, 4506f0

0x44f7fc CMP	X3, X22

0x44f800 B.LE	4506d8

0x44f804 ORR	X0, XZR, X3

0x44f808 STP	X9, X10, [SP, #200]

0x44f80c STR	X2, [SP, #264]

0x44f810 STR	X12, [SP, #352]

0x44f814 STR	X13, [SP, #368]

0x44f818 MOVZ	X1, #8

0x44f81c BL	51674c

0x44f820 LDR	X18, [SP, #264]

0x44f824 ORR	X22, XZR, X0

0x44f828 LDP	X14, X15, [SP, #200]

0x44f82c LDR	X4, [SP, #352]

0x44f830 LDR	X5, [SP, #368]

0x44f834 CMP	X18, #0

0x44f838 B.LE	44f864

0x44f83c UBFM	X2, X18, #61, #60

0x44f840 MOVZ	W1, #255

0x44f844 STP	X14, X15, [SP, #200]

0x44f848 ORR	X0, XZR, X26

0x44f84c STR	X4, [SP, #264]

0x44f850 STR	X5, [SP, #352]

0x44f854 BL	40f370

0x44f858 LDP	X14, X15, [SP, #200]

0x44f85c LDR	X4, [SP, #264]

0x44f860 LDR	X5, [SP, #352]

0x44f864 LDR	X16, [SP, #136]

0x44f868 CMP	X16, #0

0x44f86c B.LE	44f898

0x44f870 UBFM	X2, X16, #61, #60

0x44f874 MOVZ	W1, #255

0x44f878 LDR	X0, [SP, #128]

0x44f87c STP	X14, X15, [SP, #200]

0x44f880 STR	X4, [SP, #264]

0x44f884 STR	X5, [SP, #352]

0x44f888 BL	40f370

0x44f88c LDP	X14, X15, [SP, #200]

0x44f890 LDR	X4, [SP, #264]

0x44f894 LDR	X5, [SP, #352]

0x44f898 STP	X14, X15, [SP, #200]

0x44f89c STR	X4, [SP, #264]

0x44f8a0 STR	X5, [SP, #352]

0x44f8a4 BL	519580

0x44f8a8 STR	X0, [SP, #136]

0x44f8ac BL	519560

0x44f8b0 LDP	X6, X7, [SP, #168]

0x44f8b4 SUB	X2, X0, #1

0x44f8b8 LDP	X9, X10, [SP, #200]

0x44f8bc SDIV	X0, X6, X0

0x44f8c0 LDR	X8, [SP, #184]

0x44f8c4 LDR	X14, [SP, #136]

0x44f8c8 LDR	X12, [SP, #264]

0x44f8cc UBFM	X3, X8, #61, #60

0x44f8d0 LDR	X11, [X7, X8,LSL #3]

0x44f8d4 CMP	X14, X2

0x44f8d8 STR	X3, [SP, #176]

0x44f8dc MADD	X18, X14, X0, XZR

0x44f8e0 LDR	X13, [SP, #352]

0x44f8e4 ADD	X4, X0, X18

0x44f8e8 ADD	X5, X11, X18

0x44f8ec ADD	X15, X6, X11

0x44f8f0 ADD	X1, X4, X11

0x44f8f4 CSEL	X6, X15, X1, #0

0x44f8f8 CMP	X6, X5

0x44f8fc B.LE	4500ec

0x44f900 LDR	X17, [SP, #360]

0x44f904 SUB	X16, X25, #8

0x44f908 SUB	X18, X24, #8

0x44f90c STR	D8, [SP, #96]

0x44f910 LDR	X8, [SP, #184]

0x44f914 STR	X16, [SP, #136]

0x44f918 ADD	X30, X17, X5,LSL #3

0x44f91c ADD	X7, X17, X6,LSL #3

0x44f920 SUB	X0, X8, #1

0x44f924 STR	X30, [SP, #168]

0x44f928 STR	X7, [SP, #264]

(840) 0x44f92c LDR	X11, [SP, #168]

(840) 0x44f930 LDR	X15, [SP, #152]

(840) 0x44f934 LDR	X2, [SP, #224]

(840) 0x44f938 LDR	X3, [X11]

(840) 0x44f93c UBFM	X11, X3, #61, #60

(840) 0x44f940 LDR	X14, [X2, X3,LSL #3]

(840) 0x44f944 ADD	X6, X11, #8

(840) 0x44f948 LDR	X4, [X15, X6]

(840) 0x44f94c LDR	X1, [X15, X3,LSL #3]

(840) 0x44f950 ADD	X5, X14, X4

(840) 0x44f954 SUB	X17, X5, X1

(840) 0x44f958 CMP	X14, X17

(840) 0x44f95c B.GE	44fb14

(840) 0x44f960 LDR	X30, [SP, #176]

(840) 0x44f964 SUB	X2, XZR, X1,LSL #3

(840) 0x44f968 SUB	X8, X1, X14

(840) 0x44f96c ADD	X5, X8, X17

(840) 0x44f970 LDR	X16, [SP, #296]

(840) 0x44f974 ADD	X14, X2, X14,LSL #3

(840) 0x44f978 SUB	X15, X5, X1

(840) 0x44f97c ANDS	X4, X15, #4224

(840) 0x44f980 LDR	X7, [X16, X30]

(840) 0x44f984 ADD	X2, X7, X14

(840) 0x44f988 B.EQ	4506b8

(840) 0x44f98c CMP	X4, #1

(840) 0x44f990 B.EQ	44fa4c

(840) 0x44f994 CMP	X4, #2

(840) 0x44f998 B.EQ	44fa34

(840) 0x44f99c CMP	X4, #3

(840) 0x44f9a0 B.EQ	44fa1c

(840) 0x44f9a4 CMP	X4, #4

(840) 0x44f9a8 B.EQ	44fa04

(840) 0x44f9ac CMP	X4, #5

(840) 0x44f9b0 B.EQ	44f9ec

(840) 0x44f9b4 CMP	X4, #6

(840) 0x44f9b8 B.EQ	44f9d4

(840) 0x44f9bc LDR	X17, [X2, X1,LSL #3]

(840) 0x44f9c0 LDR	X30, [SP, #136]

(840) 0x44f9c4 STR	X1, [X23, X17,LSL #3]

(840) 0x44f9c8 STR	XZR, [X20, X1,LSL #3]

(840) 0x44f9cc ADD	X1, X1, #1

(840) 0x44f9d0 STR	X17, [X30, X1,LSL #3]

(840) 0x44f9d4 LDR	X16, [X2, X1,LSL #3]

(840) 0x44f9d8 LDR	X7, [SP, #136]

(840) 0x44f9dc STR	X1, [X23, X16,LSL #3]

(840) 0x44f9e0 STR	XZR, [X20, X1,LSL #3]

(840) 0x44f9e4 ADD	X1, X1, #1

(840) 0x44f9e8 STR	X16, [X7, X1,LSL #3]

(840) 0x44f9ec LDR	X8, [X2, X1,LSL #3]

(840) 0x44f9f0 LDR	X15, [SP, #136]

(840) 0x44f9f4 STR	X1, [X23, X8,LSL #3]

(840) 0x44f9f8 STR	XZR, [X20, X1,LSL #3]

(840) 0x44f9fc ADD	X1, X1, #1

(840) 0x44fa00 STR	X8, [X15, X1,LSL #3]

(840) 0x44fa04 LDR	X14, [X2, X1,LSL #3]

(840) 0x44fa08 LDR	X4, [SP, #136]

(840) 0x44fa0c STR	X1, [X23, X14,LSL #3]

(840) 0x44fa10 STR	XZR, [X20, X1,LSL #3]

(840) 0x44fa14 ADD	X1, X1, #1

(840) 0x44fa18 STR	X14, [X4, X1,LSL #3]

(840) 0x44fa1c LDR	X17, [X2, X1,LSL #3]

(840) 0x44fa20 LDR	X30, [SP, #136]

(840) 0x44fa24 STR	X1, [X23, X17,LSL #3]

(840) 0x44fa28 STR	XZR, [X20, X1,LSL #3]

(840) 0x44fa2c ADD	X1, X1, #1

(840) 0x44fa30 STR	X17, [X30, X1,LSL #3]

(840) 0x44fa34 LDR	X16, [X2, X1,LSL #3]

(840) 0x44fa38 LDR	X7, [SP, #136]

(840) 0x44fa3c STR	X1, [X23, X16,LSL #3]

(840) 0x44fa40 STR	XZR, [X20, X1,LSL #3]

(840) 0x44fa44 ADD	X1, X1, #1

(840) 0x44fa48 STR	X16, [X7, X1,LSL #3]

(840) 0x44fa4c LDR	X8, [X2, X1,LSL #3]

(840) 0x44fa50 LDR	X4, [SP, #136]

(840) 0x44fa54 STR	X1, [X23, X8,LSL #3]

(840) 0x44fa58 STR	XZR, [X20, X1,LSL #3]

(840) 0x44fa5c ADD	X1, X1, #1

(840) 0x44fa60 STR	X8, [X4, X1,LSL #3]

(840) 0x44fa64 CMP	X1, X5

(840) 0x44fa68 B.EQ	44fb14

  (851) 0x44fa6c LDR	X14, [X2, X1,LSL #3]

  (851) 0x44fa70 ADD	X7, X1, #1

  (851) 0x44fa74 ADD	X17, X1, #2

  (851) 0x44fa78 ADD	X16, X1, #3

  (851) 0x44fa7c ADD	X15, X1, #4

  (851) 0x44fa80 ADD	X8, X1, #6

  (851) 0x44fa84 STR	X1, [X23, X14,LSL #3]

  (851) 0x44fa88 STR	XZR, [X20, X1,LSL #3]

  (851) 0x44fa8c STR	X14, [X4, X7,LSL #3]

  (851) 0x44fa90 ADD	X14, X1, #5

  (851) 0x44fa94 LDR	X30, [X2, X7,LSL #3]

  (851) 0x44fa98 STR	X7, [X23, X30,LSL #3]

  (851) 0x44fa9c STR	XZR, [X20, X7,LSL #3]

  (851) 0x44faa0 ADD	X7, X1, #7

  (851) 0x44faa4 ADD	X1, X1, #8

  (851) 0x44faa8 STR	X30, [X4, X17,LSL #3]

  (851) 0x44faac LDR	X30, [X2, X17,LSL #3]

  (851) 0x44fab0 STR	X17, [X23, X30,LSL #3]

  (851) 0x44fab4 STR	XZR, [X20, X17,LSL #3]

  (851) 0x44fab8 STR	X30, [X4, X16,LSL #3]

  (851) 0x44fabc LDR	X17, [X2, X16,LSL #3]

  (851) 0x44fac0 STR	X16, [X23, X17,LSL #3]

  (851) 0x44fac4 STR	XZR, [X20, X16,LSL #3]

  (851) 0x44fac8 STR	X17, [X4, X15,LSL #3]

  (851) 0x44facc LDR	X16, [X2, X15,LSL #3]

  (851) 0x44fad0 STR	X15, [X23, X16,LSL #3]

  (851) 0x44fad4 STR	XZR, [X20, X15,LSL #3]

  (851) 0x44fad8 STR	X16, [X4, X14,LSL #3]

  (851) 0x44fadc LDR	X15, [X2, X14,LSL #3]

  (851) 0x44fae0 STR	X14, [X23, X15,LSL #3]

  (851) 0x44fae4 STR	XZR, [X20, X14,LSL #3]

  (851) 0x44fae8 STR	X15, [X4, X8,LSL #3]

  (851) 0x44faec LDR	X14, [X2, X8,LSL #3]

  (851) 0x44faf0 STR	X8, [X23, X14,LSL #3]

  (851) 0x44faf4 STR	XZR, [X20, X8,LSL #3]

  (851) 0x44faf8 STR	X14, [X4, X7,LSL #3]

  (851) 0x44fafc LDR	X8, [X2, X7,LSL #3]

  (851) 0x44fb00 STR	X7, [X23, X8,LSL #3]

  (851) 0x44fb04 STR	XZR, [X20, X7,LSL #3]

  (851) 0x44fb08 STR	X8, [X4, X1,LSL #3]

  (851) 0x44fb0c CMP	X1, X5

  (851) 0x44fb10 B.NE	44fa6c

(840) 0x44fb14 LDR	X2, [SP, #144]

(840) 0x44fb18 LDR	X5, [SP, #216]

(840) 0x44fb1c LDR	X4, [X2, X6]

(840) 0x44fb20 LDR	X30, [X5, X3,LSL #3]

(840) 0x44fb24 LDR	X1, [X2, X3,LSL #3]

(840) 0x44fb28 ADD	X7, X30, X4

(840) 0x44fb2c SUB	X17, X7, X1

(840) 0x44fb30 CMP	X30, X17

(840) 0x44fb34 B.GE	44fcd0

(840) 0x44fb38 LDR	X16, [SP, #176]

(840) 0x44fb3c SUB	X2, XZR, X1,LSL #3

(840) 0x44fb40 SUB	X8, X1, X30

(840) 0x44fb44 ADD	X5, X8, X17

(840) 0x44fb48 LDR	X15, [SP, #288]

(840) 0x44fb4c ADD	X30, X2, X30,LSL #3

(840) 0x44fb50 SUB	X4, X5, X1

(840) 0x44fb54 ANDS	X7, X4, #4224

(840) 0x44fb58 LDR	X14, [X15, X16]

(840) 0x44fb5c ADD	X2, X14, X30

(840) 0x44fb60 B.EQ	44fc28

(840) 0x44fb64 CMP	X7, #1

(840) 0x44fb68 B.EQ	44fc0c

(840) 0x44fb6c CMP	X7, #2

(840) 0x44fb70 B.EQ	44fbf8

(840) 0x44fb74 CMP	X7, #3

(840) 0x44fb78 B.EQ	44fbe4

(840) 0x44fb7c CMP	X7, #4

(840) 0x44fb80 B.EQ	44fbd0

(840) 0x44fb84 CMP	X7, #5

(840) 0x44fb88 B.EQ	44fbbc

(840) 0x44fb8c CMP	X7, #6

(840) 0x44fb90 B.EQ	44fba8

(840) 0x44fb94 LDR	X17, [X2, X1,LSL #3]

(840) 0x44fb98 STR	X1, [X22, X17,LSL #3]

(840) 0x44fb9c STR	XZR, [X19, X1,LSL #3]

(840) 0x44fba0 ADD	X1, X1, #1

(840) 0x44fba4 STR	X17, [X18, X1,LSL #3]

(840) 0x44fba8 LDR	X16, [X2, X1,LSL #3]

(840) 0x44fbac STR	X1, [X22, X16,LSL #3]

(840) 0x44fbb0 STR	XZR, [X19, X1,LSL #3]

(840) 0x44fbb4 ADD	X1, X1, #1

(840) 0x44fbb8 STR	X16, [X18, X1,LSL #3]

(840) 0x44fbbc LDR	X15, [X2, X1,LSL #3]

(840) 0x44fbc0 STR	X1, [X22, X15,LSL #3]

(840) 0x44fbc4 STR	XZR, [X19, X1,LSL #3]

(840) 0x44fbc8 ADD	X1, X1, #1

(840) 0x44fbcc STR	X15, [X18, X1,LSL #3]

(840) 0x44fbd0 LDR	X14, [X2, X1,LSL #3]

(840) 0x44fbd4 STR	X1, [X22, X14,LSL #3]

(840) 0x44fbd8 STR	XZR, [X19, X1,LSL #3]

(840) 0x44fbdc ADD	X1, X1, #1

(840) 0x44fbe0 STR	X14, [X18, X1,LSL #3]

(840) 0x44fbe4 LDR	X8, [X2, X1,LSL #3]

(840) 0x44fbe8 STR	X1, [X22, X8,LSL #3]

(840) 0x44fbec STR	XZR, [X19, X1,LSL #3]

(840) 0x44fbf0 ADD	X1, X1, #1

(840) 0x44fbf4 STR	X8, [X18, X1,LSL #3]

(840) 0x44fbf8 LDR	X4, [X2, X1,LSL #3]

(840) 0x44fbfc STR	X1, [X22, X4,LSL #3]

(840) 0x44fc00 STR	XZR, [X19, X1,LSL #3]

(840) 0x44fc04 ADD	X1, X1, #1

(840) 0x44fc08 STR	X4, [X18, X1,LSL #3]

(840) 0x44fc0c LDR	X30, [X2, X1,LSL #3]

(840) 0x44fc10 STR	X1, [X22, X30,LSL #3]

(840) 0x44fc14 STR	XZR, [X19, X1,LSL #3]

(840) 0x44fc18 ADD	X1, X1, #1

(840) 0x44fc1c STR	X30, [X18, X1,LSL #3]

(840) 0x44fc20 CMP	X1, X5

(840) 0x44fc24 B.EQ	44fcd0

  (850) 0x44fc28 LDR	X7, [X2, X1,LSL #3]

  (850) 0x44fc2c ADD	X4, X1, #1

  (850) 0x44fc30 ADD	X16, X1, #2

  (850) 0x44fc34 ADD	X15, X1, #3

  (850) 0x44fc38 ADD	X14, X1, #4

  (850) 0x44fc3c ADD	X8, X1, #5

  (850) 0x44fc40 ADD	X30, X1, #6

  (850) 0x44fc44 STR	X1, [X22, X7,LSL #3]

  (850) 0x44fc48 STR	XZR, [X19, X1,LSL #3]

  (850) 0x44fc4c STR	X7, [X18, X4,LSL #3]

  (850) 0x44fc50 LDR	X17, [X2, X4,LSL #3]

  (850) 0x44fc54 STR	X4, [X22, X17,LSL #3]

  (850) 0x44fc58 STR	XZR, [X19, X4,LSL #3]

  (850) 0x44fc5c ADD	X4, X1, #7

  (850) 0x44fc60 ADD	X1, X1, #8

  (850) 0x44fc64 STR	X17, [X18, X16,LSL #3]

  (850) 0x44fc68 LDR	X7, [X2, X16,LSL #3]

  (850) 0x44fc6c STR	X16, [X22, X7,LSL #3]

  (850) 0x44fc70 STR	XZR, [X19, X16,LSL #3]

  (850) 0x44fc74 STR	X7, [X18, X15,LSL #3]

  (850) 0x44fc78 LDR	X16, [X2, X15,LSL #3]

  (850) 0x44fc7c STR	X15, [X22, X16,LSL #3]

  (850) 0x44fc80 STR	XZR, [X19, X15,LSL #3]

  (850) 0x44fc84 STR	X16, [X18, X14,LSL #3]

  (850) 0x44fc88 LDR	X15, [X2, X14,LSL #3]

  (850) 0x44fc8c STR	X14, [X22, X15,LSL #3]

  (850) 0x44fc90 STR	XZR, [X19, X14,LSL #3]

  (850) 0x44fc94 STR	X15, [X18, X8,LSL #3]

  (850) 0x44fc98 LDR	X14, [X2, X8,LSL #3]

  (850) 0x44fc9c STR	X8, [X22, X14,LSL #3]

  (850) 0x44fca0 STR	XZR, [X19, X8,LSL #3]

  (850) 0x44fca4 STR	X14, [X18, X30,LSL #3]

  (850) 0x44fca8 LDR	X17, [X2, X30,LSL #3]

  (850) 0x44fcac STR	X30, [X22, X17,LSL #3]

  (850) 0x44fcb0 STR	XZR, [X19, X30,LSL #3]

  (850) 0x44fcb4 STR	X17, [X18, X4,LSL #3]

  (850) 0x44fcb8 LDR	X8, [X2, X4,LSL #3]

  (850) 0x44fcbc STR	X4, [X22, X8,LSL #3]

  (850) 0x44fcc0 STR	XZR, [X19, X4,LSL #3]

  (850) 0x44fcc4 STR	X8, [X18, X1,LSL #3]

  (850) 0x44fcc8 CMP	X1, X5

  (850) 0x44fccc B.NE	44fc28

(840) 0x44fcd0 LDR	X5, [SP, #240]

(840) 0x44fcd4 LDR	X1, [X5, X3,LSL #3]

(840) 0x44fcd8 ADD	X30, X5, X6

(840) 0x44fcdc LDR	X16, [X5, X6]

(840) 0x44fce0 CMP	X1, X16

(840) 0x44fce4 B.GE	44fd08

  (849) 0x44fce8 LDR	X2, [SP, #120]

  (849) 0x44fcec LDR	X7, [X2, X1,LSL #3]

  (849) 0x44fcf0 LDR	X4, [X10, X7,LSL #3]

  (849) 0x44fcf4 CMP	X4, X0

  (849) 0x44fcf8 B.EQ	450140

  (849) 0x44fcfc ADD	X1, X1, #1

  (849) 0x44fd00 CMP	X1, X16

  (849) 0x44fd04 B.LT	44fce8

(840) 0x44fd08 LDR	X15, [SP, #232]

(840) 0x44fd0c LDR	X2, [X15, X3,LSL #3]

(840) 0x44fd10 ADD	X14, X15, X6

(840) 0x44fd14 LDR	X7, [X15, X6]

(840) 0x44fd18 CMP	X2, X7

(840) 0x44fd1c B.GE	44fd40

  (848) 0x44fd20 LDR	X17, [SP, #112]

  (848) 0x44fd24 LDR	X8, [X17, X2,LSL #3]

  (848) 0x44fd28 LDR	X30, [X9, X8,LSL #3]

  (848) 0x44fd2c CMP	X30, X0

  (848) 0x44fd30 B.EQ	450124

  (848) 0x44fd34 ADD	X2, X2, #1

  (848) 0x44fd38 CMP	X2, X7

  (848) 0x44fd3c B.LT	44fd20

(840) 0x44fd40 LDR	X4, [SP, #256]

(840) 0x44fd44 MOVI	D0, #0

(840) 0x44fd48 FMOV	D1, D0

(840) 0x44fd4c LDR	X16, [X4, X3,LSL #3]

(840) 0x44fd50 LDR	X7, [X4, X6]

(840) 0x44fd54 ADD	X1, X16, #1

(840) 0x44fd58 STR	X16, [SP, #184]

(840) 0x44fd5c CMP	X1, X7

(840) 0x44fd60 B.GE	44fdd0

(840) 0x44fd64 STP	X9, X0, [SP, #200]

(840) 0x44fd68 LDR	X0, [SP, #192]

(840) 0x44fd6c LDR	X9, [SP, #312]

(840) 0x44fd70 B	44fd90

  (845) 0x44fd74 LDR	X8, [X28, X2,LSL #3]

  (845) 0x44fd78 LDR	X30, [X28, X11]

  (845) 0x44fd7c CMP	X30, X8

  (845) 0x44fd80 B.EQ	44fdb8

  (845) 0x44fd84 ADD	X1, X1, #1

  (845) 0x44fd88 CMP	X1, X7

  (845) 0x44fd8c B.EQ	44fdcc

  (845) 0x44fd90 LDR	X2, [X9, X1,LSL #3]

  (845) 0x44fd94 LDR	X15, [X26, X2,LSL #3]

  (845) 0x44fd98 UBFM	X14, X2, #61, #60

  (845) 0x44fd9c CMP	X3, X15

  (845) 0x44fda0 B.EQ	450158

  (845) 0x44fda4 LDR	X17, [X13, X2,LSL #3]

  (845) 0x44fda8 CMN	X17, #3

  (845) 0x44fdac B.EQ	44fd84

  (845) 0x44fdb0 CMP	X0, #1

  (845) 0x44fdb4 B.NE	44fd74

  (845) 0x44fdb8 LDR	D2, [X21, X1,LSL #3]

  (845) 0x44fdbc ADD	X1, X1, #1

  (845) 0x44fdc0 FADD	D0, D0, D2

  (845) 0x44fdc4 CMP	X1, X7

  (845) 0x44fdc8 B.NE	44fd90

(840) 0x44fdcc LDP	X9, X0, [SP, #200]

(840) 0x44fdd0 LDR	X15, [SP, #248]

(840) 0x44fdd4 LDR	X1, [X15, X3,LSL #3]

(840) 0x44fdd8 LDR	X4, [X15, X6]

(840) 0x44fddc CMP	X1, X4

(840) 0x44fde0 B.GE	44fe6c

(840) 0x44fde4 STR	X0, [SP, #200]

(840) 0x44fde8 LDR	X0, [SP, #128]

(840) 0x44fdec LDP	X14, X15, [SP, #272]

(840) 0x44fdf0 LDR	X17, [SP, #192]

(840) 0x44fdf4 LDR	X5, [SP, #304]

(840) 0x44fdf8 LDR	X7, [SP, #320]

(840) 0x44fdfc B	44fe20

  (843) 0x44fe00 LDR	X30, [SP, #160]

  (843) 0x44fe04 LDR	X8, [X30, X2]

  (843) 0x44fe08 LDR	X2, [X28, X11]

  (843) 0x44fe0c CMP	X8, X2

  (843) 0x44fe10 B.EQ	44fe54

  (843) 0x44fe14 ADD	X1, X1, #1

  (843) 0x44fe18 CMP	X1, X4

  (843) 0x44fe1c B.EQ	44fe68

  (843) 0x44fe20 LDR	X30, [X5, X1,LSL #3]

  (843) 0x44fe24 CBZ	X7, 44fe2c

  (843) 0x44fe28 LDR	X30, [X15, X30,LSL #3]

  (843) 0x44fe2c UBFM	X2, X30, #61, #60

  (843) 0x44fe30 TBNZ	X30, #63, 44fe40

  (843) 0x44fe34 LDR	X8, [X0, X30,LSL #3]

  (843) 0x44fe38 CMP	X3, X8

  (843) 0x44fe3c B.EQ	450448

  (843) 0x44fe40 LDR	X16, [X12, X2]

  (843) 0x44fe44 CMN	X16, #3

  (843) 0x44fe48 B.EQ	44fe14

  (843) 0x44fe4c CMP	X17, #1

  (843) 0x44fe50 B.NE	44fe00

  (843) 0x44fe54 LDR	D16, [X27, X1,LSL #3]

  (843) 0x44fe58 ADD	X1, X1, #1

  (843) 0x44fe5c FADD	D0, D0, D16

  (843) 0x44fe60 CMP	X1, X4

  (843) 0x44fe64 B.NE	44fe20

(840) 0x44fe68 LDR	X0, [SP, #200]

(840) 0x44fe6c LDR	X11, [SP, #184]

(840) 0x44fe70 LDR	D21, [X21, X11,LSL #3]

(840) 0x44fe74 FMUL	D22, D1, D21

(840) 0x44fe78 FCMP	D22, #0

(840) 0x44fe7c B.EQ	44fe88

(840) 0x44fe80 FNEG	D8, D0

(840) 0x44fe84 FDIV	D8, D8, D22

(840) 0x44fe88 LDR	X16, [SP, #152]

(840) 0x44fe8c LDR	X8, [X16, X3,LSL #3]

(840) 0x44fe90 LDR	X30, [X16, X6]

(840) 0x44fe94 CMP	X30, X8

(840) 0x44fe98 B.LE	44ffac

(840) 0x44fe9c ADD	X4, X20, X30,LSL #3

(840) 0x44fea0 ADD	X17, X20, X8,LSL #3

(840) 0x44fea4 SUB	X2, X4, X17

(840) 0x44fea8 SUB	X5, X2, #8

(840) 0x44feac UBFM	X7, X5, #3, #63

(840) 0x44feb0 ADD	X14, X7, #1

(840) 0x44feb4 ANDS	X15, X14, #4224

(840) 0x44feb8 B.EQ	44ff4c

(840) 0x44febc CMP	X15, #1

(840) 0x44fec0 B.EQ	44ff38

(840) 0x44fec4 CMP	X15, #2

(840) 0x44fec8 B.EQ	44ff2c

(840) 0x44fecc CMP	X15, #3

(840) 0x44fed0 B.EQ	44ff20

(840) 0x44fed4 CMP	X15, #4

(840) 0x44fed8 B.EQ	44ff14

(840) 0x44fedc CMP	X15, #5

(840) 0x44fee0 B.EQ	44ff08

(840) 0x44fee4 CMP	X15, #6

(840) 0x44fee8 B.EQ	44fefc

(840) 0x44feec LDR	D0, [X20, X8,LSL #3]

(840) 0x44fef0 ADD	X17, X17, #8

(840) 0x44fef4 FMUL	D23, D0, D8

(840) 0x44fef8 STR	D23, [X20, X8,LSL #3]

(840) 0x44fefc LDR	D24, [X17]

(840) 0x44ff00 FMUL	D25, D24, D8

(840) 0x44ff04 STR	D25, [X17], #8

(840) 0x44ff08 LDR	D26, [X17]

(840) 0x44ff0c FMUL	D27, D26, D8

(840) 0x44ff10 STR	D27, [X17], #8

(840) 0x44ff14 LDR	D28, [X17]

(840) 0x44ff18 FMUL	D29, D28, D8

(840) 0x44ff1c STR	D29, [X17], #8

(840) 0x44ff20 LDR	D30, [X17]

(840) 0x44ff24 FMUL	D31, D30, D8

(840) 0x44ff28 STR	D31, [X17], #8

(840) 0x44ff2c LDR	D4, [X17]

(840) 0x44ff30 FMUL	D5, D4, D8

(840) 0x44ff34 STR	D5, [X17], #8

(840) 0x44ff38 LDR	D6, [X17]

(840) 0x44ff3c FMUL	D3, D6, D8

(840) 0x44ff40 STR	D3, [X17], #8

(840) 0x44ff44 CMP	X17, X4

(840) 0x44ff48 B.EQ	44ffac

  (842) 0x44ff4c LDR	D7, [X17]

  (842) 0x44ff50 ORR	X1, XZR, X17

  (842) 0x44ff54 FMUL	D16, D7, D8

  (842) 0x44ff58 STR	D16, [X1], #8

  (842) 0x44ff5c LDR	D17, [X17, #8]

  (842) 0x44ff60 FMUL	D2, D17, D8

  (842) 0x44ff64 STR	D2, [X17, #8]

  (842) 0x44ff68 LDR	D18, [X1, #8]

  (842) 0x44ff6c FMUL	D19, D18, D8

  (842) 0x44ff70 STR	D19, [X1, #8]

  (842) 0x44ff74 LDP	D20, D21, [X17, #24]

  (842) 0x44ff78 LDP	D22, D1, [X17, #40]

  (842) 0x44ff7c LDR	D0, [X17, #56]

  (842) 0x44ff80 FMUL	D23, D20, D8

  (842) 0x44ff84 FMUL	D24, D21, D8

  (842) 0x44ff88 FMUL	D25, D22, D8

  (842) 0x44ff8c FMUL	D26, D1, D8

  (842) 0x44ff90 FMUL	D27, D0, D8

  (842) 0x44ff94 STP	D23, D24, [X17, #24]

  (842) 0x44ff98 STP	D25, D26, [X17, #40]

  (842) 0x44ff9c ADD	X17, X17, #64

  (842) 0x44ffa0 STUR	D27, [X17, #504]

  (842) 0x44ffa4 CMP	X17, X4

  (842) 0x44ffa8 B.NE	44ff4c

(840) 0x44ffac LDR	X11, [SP, #144]

(840) 0x44ffb0 LDR	X3, [X11, X3,LSL #3]

(840) 0x44ffb4 LDR	X6, [X11, X6]

(840) 0x44ffb8 CMP	X6, X3

(840) 0x44ffbc B.LE	4500d0

(840) 0x44ffc0 ADD	X16, X19, X6,LSL #3

(840) 0x44ffc4 ADD	X7, X19, X3,LSL #3

(840) 0x44ffc8 SUB	X8, X16, X7

(840) 0x44ffcc SUB	X30, X8, #8

(840) 0x44ffd0 UBFM	X4, X30, #3, #63

(840) 0x44ffd4 ADD	X2, X4, #1

(840) 0x44ffd8 ANDS	X5, X2, #4224

(840) 0x44ffdc B.EQ	450070

(840) 0x44ffe0 CMP	X5, #1

(840) 0x44ffe4 B.EQ	45005c

(840) 0x44ffe8 CMP	X5, #2

(840) 0x44ffec B.EQ	450050

(840) 0x44fff0 CMP	X5, #3

(840) 0x44fff4 B.EQ	450044

(840) 0x44fff8 CMP	X5, #4

(840) 0x44fffc B.EQ	450038

(840) 0x450000 CMP	X5, #5

(840) 0x450004 B.EQ	45002c

(840) 0x450008 CMP	X5, #6

(840) 0x45000c B.EQ	450020

(840) 0x450010 LDR	D28, [X19, X3,LSL #3]

(840) 0x450014 ADD	X7, X7, #8

(840) 0x450018 FMUL	D29, D28, D8

(840) 0x45001c STR	D29, [X19, X3,LSL #3]

(840) 0x450020 LDR	D30, [X7]

(840) 0x450024 FMUL	D31, D30, D8

(840) 0x450028 STR	D31, [X7], #8

(840) 0x45002c LDR	D4, [X7]

(840) 0x450030 FMUL	D5, D4, D8

(840) 0x450034 STR	D5, [X7], #8

(840) 0x450038 LDR	D6, [X7]

(840) 0x45003c FMUL	D3, D6, D8

(840) 0x450040 STR	D3, [X7], #8

(840) 0x450044 LDR	D7, [X7]

(840) 0x450048 FMUL	D16, D7, D8

(840) 0x45004c STR	D16, [X7], #8

(840) 0x450050 LDR	D17, [X7]

(840) 0x450054 FMUL	D2, D17, D8

(840) 0x450058 STR	D2, [X7], #8

(840) 0x45005c LDR	D18, [X7]

(840) 0x450060 FMUL	D19, D18, D8

(840) 0x450064 STR	D19, [X7], #8

(840) 0x450068 CMP	X16, X7

(840) 0x45006c B.EQ	4500d0

  (841) 0x450070 LDR	D20, [X7]

  (841) 0x450074 ORR	X14, XZR, X7

  (841) 0x450078 FMUL	D21, D20, D8

  (841) 0x45007c STR	D21, [X14], #8

  (841) 0x450080 LDR	D22, [X7, #8]

  (841) 0x450084 FMUL	D1, D22, D8

  (841) 0x450088 STR	D1, [X7, #8]

  (841) 0x45008c LDR	D0, [X14, #8]

  (841) 0x450090 FMUL	D23, D0, D8

  (841) 0x450094 STR	D23, [X14, #8]

  (841) 0x450098 LDP	D24, D25, [X7, #24]

  (841) 0x45009c LDP	D26, D27, [X7, #40]

  (841) 0x4500a0 LDR	D28, [X7, #56]

  (841) 0x4500a4 FMUL	D29, D24, D8

  (841) 0x4500a8 FMUL	D30, D25, D8

  (841) 0x4500ac FMUL	D31, D26, D8

  (841) 0x4500b0 FMUL	D4, D27, D8

  (841) 0x4500b4 FMUL	D5, D28, D8

  (841) 0x4500b8 STP	D29, D30, [X7, #24]

  (841) 0x4500bc STP	D31, D4, [X7, #40]

  (841) 0x4500c0 ADD	X7, X7, #64

  (841) 0x4500c4 STUR	D5, [X7, #504]

  (841) 0x4500c8 CMP	X16, X7

  (841) 0x4500cc B.NE	450070

(840) 0x4500d0 LDR	X15, [SP, #168]

(840) 0x4500d4 LDR	X17, [SP, #264]

(840) 0x4500d8 ADD	X1, X15, #8

(840) 0x4500dc STR	X1, [SP, #168]

(840) 0x4500e0 CMP	X17, X1

(840) 0x4500e4 B.NE	44f92c

0x4500e8 LDR	D8, [SP, #96]

0x4500ec ORR	X0, XZR, X26

0x4500f0 BL	516820

0x4500f4 LDR	X0, [SP, #128]

0x4500f8 BL	516820

0x4500fc ORR	X0, XZR, X23

0x450100 BL	516820

0x450104 ORR	X0, XZR, X22

0x450108 LDP	X19, X20, [SP, #16]

0x45010c LDP	X21, X22, [SP, #32]

0x450110 LDP	X23, X24, [SP, #48]

0x450114 LDP	X25, X26, [SP, #64]

0x450118 LDP	X27, X28, [SP, #80]

0x45011c LDP	X29, X30, [SP], #384

0x450120 B	516820

  (848) 0x450124 LDR	X5, [SP, #128]

  (848) 0x450128 ADD	X2, X2, #1

  (848) 0x45012c STR	X3, [X5, X8,LSL #3]

  (848) 0x450130 LDR	X7, [X14]

  (848) 0x450134 CMP	X7, X2

  (848) 0x450138 B.GT	44fd20

(840) 0x45013c B	44fd40

  (849) 0x450140 STR	X3, [X26, X7,LSL #3]

  (849) 0x450144 ADD	X1, X1, #1

  (849) 0x450148 LDR	X16, [X30]

  (849) 0x45014c CMP	X1, X16

  (849) 0x450150 B.LT	44fce8

(840) 0x450154 B	44fd08

  (845) 0x450158 LDR	X16, [SP, #152]

  (845) 0x45015c ADD	X5, X14, #8

  (845) 0x450160 LDR	X4, [X16, X2,LSL #3]

  (845) 0x450164 LDR	X17, [X16, X5]

  (845) 0x450168 CMP	X4, X17

  (845) 0x45016c B.GE	4502d0

  (845) 0x450170 SUB	X15, X17, X4

  (845) 0x450174 ANDS	X14, X15, #4160

  (845) 0x450178 B.EQ	450218

  (845) 0x45017c CMP	X14, #1

  (845) 0x450180 B.EQ	4501e4

  (845) 0x450184 CMP	X14, #2

  (845) 0x450188 B.EQ	4501b8

  (845) 0x45018c LDR	X8, [X25, X4,LSL #3]

  (845) 0x450190 LDR	D3, [X20, X4,LSL #3]

  (845) 0x450194 ADD	X4, X4, #1

  (845) 0x450198 LDR	D4, [X21, X1,LSL #3]

  (845) 0x45019c LDR	X30, [X23, X8,LSL #3]

  (845) 0x4501a0 FMUL	D5, D4, D3

  (845) 0x4501a4 LDR	D6, [X20, X30,LSL #3]

  (845) 0x4501a8 FADD	D1, D1, D5

  (845) 0x4501ac FADD	D0, D0, D5

  (845) 0x4501b0 FADD	D7, D6, D5

  (845) 0x4501b4 STR	D7, [X20, X30,LSL #3]

  (845) 0x4501b8 LDR	X16, [X25, X4,LSL #3]

  (845) 0x4501bc LDR	D16, [X20, X4,LSL #3]

  (845) 0x4501c0 ADD	X4, X4, #1

  (845) 0x4501c4 LDR	D8, [X21, X1,LSL #3]

  (845) 0x4501c8 LDR	X15, [X23, X16,LSL #3]

  (845) 0x4501cc FMUL	D17, D8, D16

  (845) 0x4501d0 LDR	D18, [X20, X15,LSL #3]

  (845) 0x4501d4 FADD	D1, D1, D17

  (845) 0x4501d8 FADD	D0, D0, D17

  (845) 0x4501dc FADD	D19, D18, D17

  (845) 0x4501e0 STR	D19, [X20, X15,LSL #3]

  (845) 0x4501e4 LDR	X14, [X25, X4,LSL #3]

  (845) 0x4501e8 LDR	D21, [X20, X4,LSL #3]

  (845) 0x4501ec ADD	X4, X4, #1

  (845) 0x4501f0 LDR	D20, [X21, X1,LSL #3]

  (845) 0x4501f4 LDR	X8, [X23, X14,LSL #3]

  (845) 0x4501f8 FMUL	D8, D20, D21

  (845) 0x4501fc LDR	D22, [X20, X8,LSL #3]

  (845) 0x450200 FADD	D1, D1, D8

  (845) 0x450204 FADD	D0, D0, D8

  (845) 0x450208 FADD	D23, D22, D8

  (845) 0x45020c STR	D23, [X20, X8,LSL #3]

  (845) 0x450210 CMP	X4, X17

  (845) 0x450214 B.EQ	4502d0

    (847) 0x450218 LDR	X30, [X25, X4,LSL #3]

    (847) 0x45021c ADD	X8, X4, #1

    (847) 0x450220 ADD	X14, X4, #3

    (847) 0x450224 ADD	X15, X8, #1

    (847) 0x450228 LDR	D25, [X20, X4,LSL #3]

    (847) 0x45022c ADD	X4, X4, #4

    (847) 0x450230 LDR	D24, [X21, X1,LSL #3]

    (847) 0x450234 LDR	X30, [X23, X30,LSL #3]

    (847) 0x450238 LDR	X16, [X25, X8,LSL #3]

    (847) 0x45023c FMUL	D26, D24, D25

    (847) 0x450240 LDR	D27, [X20, X30,LSL #3]

    (847) 0x450244 LDR	X16, [X23, X16,LSL #3]

    (847) 0x450248 FADD	D28, D1, D26

    (847) 0x45024c FADD	D29, D0, D26

    (847) 0x450250 FADD	D30, D27, D26

    (847) 0x450254 STR	D30, [X20, X30,LSL #3]

    (847) 0x450258 LDR	D2, [X20, X8,LSL #3]

    (847) 0x45025c LDR	D31, [X21, X1,LSL #3]

    (847) 0x450260 LDR	D4, [X20, X16,LSL #3]

    (847) 0x450264 LDR	X30, [X25, X15,LSL #3]

    (847) 0x450268 FMUL	D5, D31, D2

    (847) 0x45026c LDR	X8, [X25, X14,LSL #3]

    (847) 0x450270 LDR	X30, [X23, X30,LSL #3]

    (847) 0x450274 LDR	X8, [X23, X8,LSL #3]

    (847) 0x450278 FADD	D3, D4, D5

    (847) 0x45027c FADD	D6, D28, D5

    (847) 0x450280 FADD	D7, D29, D5

    (847) 0x450284 STR	D3, [X20, X16,LSL #3]

    (847) 0x450288 LDR	D8, [X21, X1,LSL #3]

    (847) 0x45028c LDR	D16, [X20, X15,LSL #3]

    (847) 0x450290 LDR	D17, [X20, X30,LSL #3]

    (847) 0x450294 FMUL	D18, D8, D16

    (847) 0x450298 FADD	D19, D17, D18

    (847) 0x45029c FADD	D20, D6, D18

    (847) 0x4502a0 FADD	D21, D7, D18

    (847) 0x4502a4 STR	D19, [X20, X30,LSL #3]

    (847) 0x4502a8 LDR	D1, [X20, X14,LSL #3]

    (847) 0x4502ac LDR	D22, [X21, X1,LSL #3]

    (847) 0x4502b0 LDR	D0, [X20, X8,LSL #3]

    (847) 0x4502b4 FMUL	D8, D22, D1

    (847) 0x4502b8 FADD	D23, D0, D8

    (847) 0x4502bc FADD	D1, D20, D8

    (847) 0x4502c0 FADD	D0, D21, D8

    (847) 0x4502c4 STR	D23, [X20, X8,LSL #3]

    (847) 0x4502c8 CMP	X4, X17

    (847) 0x4502cc B.NE	450218

  (845) 0x4502d0 LDR	X17, [SP, #144]

  (845) 0x4502d4 LDR	X2, [X17, X2,LSL #3]

  (845) 0x4502d8 LDR	X15, [X17, X5]

  (845) 0x4502dc CMP	X2, X15

  (845) 0x4502e0 B.GE	44fd84

  (845) 0x4502e4 SUB	X5, X15, X2

  (845) 0x4502e8 ANDS	X4, X5, #4160

  (845) 0x4502ec B.EQ	45038c

  (845) 0x4502f0 CMP	X4, #1

  (845) 0x4502f4 B.EQ	450358

  (845) 0x4502f8 CMP	X4, #2

  (845) 0x4502fc B.EQ	45032c

  (845) 0x450300 LDR	X14, [X24, X2,LSL #3]

  (845) 0x450304 LDR	D25, [X19, X2,LSL #3]

  (845) 0x450308 ADD	X2, X2, #1

  (845) 0x45030c LDR	D24, [X21, X1,LSL #3]

  (845) 0x450310 LDR	X16, [X22, X14,LSL #3]

  (845) 0x450314 FMUL	D26, D24, D25

  (845) 0x450318 LDR	D27, [X19, X16,LSL #3]

  (845) 0x45031c FADD	D1, D1, D26

  (845) 0x450320 FADD	D0, D0, D26

  (845) 0x450324 FADD	D28, D27, D26

  (845) 0x450328 STR	D28, [X19, X16,LSL #3]

  (845) 0x45032c LDR	X30, [X24, X2,LSL #3]

  (845) 0x450330 LDR	D30, [X19, X2,LSL #3]

  (845) 0x450334 ADD	X2, X2, #1

  (845) 0x450338 LDR	D29, [X21, X1,LSL #3]

  (845) 0x45033c LDR	X8, [X22, X30,LSL #3]

  (845) 0x450340 FMUL	D31, D29, D30

  (845) 0x450344 LDR	D2, [X19, X8,LSL #3]

  (845) 0x450348 FADD	D1, D1, D31

  (845) 0x45034c FADD	D0, D0, D31

  (845) 0x450350 FADD	D4, D2, D31

  (845) 0x450354 STR	D4, [X19, X8,LSL #3]

  (845) 0x450358 LDR	X17, [X24, X2,LSL #3]

  (845) 0x45035c LDR	D3, [X19, X2,LSL #3]

  (845) 0x450360 ADD	X2, X2, #1

  (845) 0x450364 LDR	D5, [X21, X1,LSL #3]

  (845) 0x450368 LDR	X5, [X22, X17,LSL #3]

  (845) 0x45036c FMUL	D8, D5, D3

  (845) 0x450370 LDR	D6, [X19, X5,LSL #3]

  (845) 0x450374 FADD	D1, D1, D8

  (845) 0x450378 FADD	D0, D0, D8

  (845) 0x45037c FADD	D7, D6, D8

  (845) 0x450380 STR	D7, [X19, X5,LSL #3]

  (845) 0x450384 CMP	X2, X15

  (845) 0x450388 B.EQ	44fd84

    (846) 0x45038c LDR	X14, [X24, X2,LSL #3]

    (846) 0x450390 ADD	X4, X2, #1

    (846) 0x450394 ADD	X30, X2, #3

    (846) 0x450398 ADD	X17, X4, #1

    (846) 0x45039c LDR	D8, [X21, X1,LSL #3]

    (846) 0x4503a0 LDR	D16, [X19, X2,LSL #3]

    (846) 0x4503a4 ADD	X2, X2, #4

    (846) 0x4503a8 LDR	X8, [X22, X14,LSL #3]

    (846) 0x4503ac LDR	X16, [X24, X4,LSL #3]

    (846) 0x4503b0 FMUL	D17, D8, D16

    (846) 0x4503b4 LDR	X14, [X24, X17,LSL #3]

    (846) 0x4503b8 LDR	D18, [X19, X8,LSL #3]

    (846) 0x4503bc LDR	X5, [X22, X16,LSL #3]

    (846) 0x4503c0 FADD	D19, D1, D17

    (846) 0x4503c4 FADD	D20, D0, D17

    (846) 0x4503c8 FADD	D21, D18, D17

    (846) 0x4503cc STR	D21, [X19, X8,LSL #3]

    (846) 0x4503d0 LDR	D1, [X19, X4,LSL #3]

    (846) 0x4503d4 LDR	D22, [X21, X1,LSL #3]

    (846) 0x4503d8 LDR	D0, [X19, X5,LSL #3]

    (846) 0x4503dc LDR	X4, [X24, X30,LSL #3]

    (846) 0x4503e0 FMUL	D23, D22, D1

    (846) 0x4503e4 LDR	X8, [X22, X14,LSL #3]

    (846) 0x4503e8 LDR	X16, [X22, X4,LSL #3]

    (846) 0x4503ec FADD	D24, D0, D23

    (846) 0x4503f0 FADD	D25, D19, D23

    (846) 0x4503f4 FADD	D26, D20, D23

    (846) 0x4503f8 STR	D24, [X19, X5,LSL #3]

    (846) 0x4503fc LDR	D27, [X21, X1,LSL #3]

    (846) 0x450400 LDR	D28, [X19, X17,LSL #3]

    (846) 0x450404 LDR	D29, [X19, X8,LSL #3]

    (846) 0x450408 FMUL	D30, D27, D28

    (846) 0x45040c FADD	D31, D29, D30

    (846) 0x450410 FADD	D4, D25, D30

    (846) 0x450414 FADD	D5, D26, D30

    (846) 0x450418 STR	D31, [X19, X8,LSL #3]

    (846) 0x45041c LDR	D6, [X21, X1,LSL #3]

    (846) 0x450420 LDR	D3, [X19, X30,LSL #3]

    (846) 0x450424 LDR	D2, [X19, X16,LSL #3]

    (846) 0x450428 FMUL	D8, D6, D3

    (846) 0x45042c FADD	D7, D2, D8

    (846) 0x450430 FADD	D1, D4, D8

    (846) 0x450434 FADD	D0, D5, D8

    (846) 0x450438 STR	D7, [X19, X16,LSL #3]

    (846) 0x45043c CMP	X2, X15

    (846) 0x450440 B.NE	45038c

  (845) 0x450444 B	44fd84

  (843) 0x450448 LDP	X30, X16, [SP, #328]

  (843) 0x45044c ADD	X8, X30, X2

  (843) 0x450450 LDR	X2, [X16, X2]

  (843) 0x450454 LDR	X30, [X8, #8]

  (843) 0x450458 ADD	X16, X2, X30

  (843) 0x45045c CMP	X2, X16

  (843) 0x450460 B.GE	44fe14

  (843) 0x450464 LDR	X30, [SP, #176]

  (843) 0x450468 LDR	X8, [SP, #344]

  (843) 0x45046c LDR	X8, [X8, X30]

  (843) 0x450470 SUB	X30, X16, X2

  (843) 0x450474 ANDS	X30, X30, #4160

  (843) 0x450478 B.EQ	4505ac

  (843) 0x45047c CMP	X30, #1

  (843) 0x450480 B.EQ	4504ec

  (843) 0x450484 CMP	X30, #2

  (843) 0x450488 B.EQ	4504bc

  (843) 0x45048c LDR	D8, [X27, X1,LSL #3]

  (843) 0x450490 LDR	D17, [X14, X2,LSL #3]

  (843) 0x450494 LDR	X30, [X8, X2,LSL #3]

  (843) 0x450498 FMUL	D18, D8, D17

  (843) 0x45049c TBNZ	X30, #63, 4506c0

  (843) 0x4504a0 LDR	X30, [X22, X30,LSL #3]

  (843) 0x4504a4 LDR	D19, [X19, X30,LSL #3]

  (843) 0x4504a8 FADD	D20, D19, D18

  (843) 0x4504ac STR	D20, [X19, X30,LSL #3]

  (843) 0x4504b0 FADD	D1, D1, D18

  (843) 0x4504b4 FADD	D0, D0, D18

  (843) 0x4504b8 ADD	X2, X2, #1

  (843) 0x4504bc LDR	D23, [X27, X1,LSL #3]

  (843) 0x4504c0 LDR	D24, [X14, X2,LSL #3]

  (843) 0x4504c4 LDR	X30, [X8, X2,LSL #3]

  (843) 0x4504c8 FMUL	D25, D23, D24

  (843) 0x4504cc TBNZ	X30, #63, 4506a0

  (843) 0x4504d0 LDR	X30, [X22, X30,LSL #3]

  (843) 0x4504d4 LDR	D26, [X19, X30,LSL #3]

  (843) 0x4504d8 FADD	D27, D26, D25

  (843) 0x4504dc STR	D27, [X19, X30,LSL #3]

  (843) 0x4504e0 FADD	D1, D1, D25

  (843) 0x4504e4 FADD	D0, D0, D25

  (843) 0x4504e8 ADD	X2, X2, #1

  (843) 0x4504ec LDR	D30, [X27, X1,LSL #3]

  (843) 0x4504f0 LDR	D31, [X14, X2,LSL #3]

  (843) 0x4504f4 LDR	X30, [X8, X2,LSL #3]

  (843) 0x4504f8 FMUL	D8, D30, D31

  (843) 0x4504fc TBNZ	X30, #63, 450688

  (843) 0x450500 LDR	X30, [X22, X30,LSL #3]

  (843) 0x450504 LDR	D4, [X19, X30,LSL #3]

  (843) 0x450508 FADD	D5, D4, D8

  (843) 0x45050c STR	D5, [X19, X30,LSL #3]

  (843) 0x450510 ADD	X2, X2, #1

  (843) 0x450514 FADD	D1, D1, D8

  (843) 0x450518 FADD	D0, D0, D8

  (843) 0x45051c CMP	X16, X2

  (843) 0x450520 B.NE	4505ac

  (843) 0x450524 B	44fe14

    (844) 0x450528 LDR	X30, [X22, X30,LSL #3]

    (844) 0x45052c FADD	D28, D1, D22

    (844) 0x450530 FADD	D29, D0, D22

    (844) 0x450534 LDR	D23, [X19, X30,LSL #3]

    (844) 0x450538 FADD	D24, D23, D22

    (844) 0x45053c STR	D24, [X19, X30,LSL #3]

    (844) 0x450540 ADD	X30, X2, #1

    (844) 0x450544 LDR	D27, [X27, X1,LSL #3]

    (844) 0x450548 LDR	D30, [X14, X30,LSL #3]

    (844) 0x45054c LDR	X30, [X8, X30,LSL #3]

    (844) 0x450550 FMUL	D31, D27, D30

    (844) 0x450554 TBNZ	X30, #63, 450624

    (844) 0x450558 LDR	X30, [X22, X30,LSL #3]

    (844) 0x45055c FADD	D16, D28, D31

    (844) 0x450560 FADD	D17, D29, D31

    (844) 0x450564 LDR	D4, [X19, X30,LSL #3]

    (844) 0x450568 FADD	D5, D4, D31

    (844) 0x45056c STR	D5, [X19, X30,LSL #3]

    (844) 0x450570 ADD	X30, X2, #2

    (844) 0x450574 LDR	D7, [X27, X1,LSL #3]

    (844) 0x450578 LDR	D2, [X14, X30,LSL #3]

    (844) 0x45057c LDR	X30, [X8, X30,LSL #3]

    (844) 0x450580 FMUL	D8, D7, D2

    (844) 0x450584 TBNZ	X30, #63, 450658

    (844) 0x450588 LDR	X30, [X22, X30,LSL #3]

    (844) 0x45058c LDR	D18, [X19, X30,LSL #3]

    (844) 0x450590 FADD	D19, D18, D8

    (844) 0x450594 STR	D19, [X19, X30,LSL #3]

    (844) 0x450598 ADD	X2, X2, #3

    (844) 0x45059c FADD	D1, D16, D8

    (844) 0x4505a0 FADD	D0, D17, D8

    (844) 0x4505a4 CMP	X16, X2

    (844) 0x4505a8 B.EQ	44fe14

    (844) 0x4505ac LDR	D2, [X27, X1,LSL #3]

    (844) 0x4505b0 LDR	D7, [X14, X2,LSL #3]

    (844) 0x4505b4 LDR	X30, [X8, X2,LSL #3]

    (844) 0x4505b8 FMUL	D16, D2, D7

    (844) 0x4505bc TBNZ	X30, #63, 450670

    (844) 0x4505c0 LDR	X30, [X22, X30,LSL #3]

    (844) 0x4505c4 LDR	D8, [X19, X30,LSL #3]

    (844) 0x4505c8 FADD	D17, D8, D16

    (844) 0x4505cc STR	D17, [X19, X30,LSL #3]

    (844) 0x4505d0 ADD	X2, X2, #1

    (844) 0x4505d4 LDR	D20, [X27, X1,LSL #3]

    (844) 0x4505d8 FADD	D1, D1, D16

    (844) 0x4505dc FADD	D0, D0, D16

    (844) 0x4505e0 LDR	D21, [X14, X2,LSL #3]

    (844) 0x4505e4 LDR	X30, [X8, X2,LSL #3]

    (844) 0x4505e8 FMUL	D22, D20, D21

    (844) 0x4505ec TBZ	X30, #63, 450528

    (844) 0x4505f0 ORN	X30, XZR, X30

    (844) 0x4505f4 FADD	D28, D1, D22

    (844) 0x4505f8 FADD	D29, D0, D22

    (844) 0x4505fc LDR	X30, [X23, X30,LSL #3]

    (844) 0x450600 LDR	D25, [X20, X30,LSL #3]

    (844) 0x450604 FADD	D26, D25, D22

    (844) 0x450608 STR	D26, [X20, X30,LSL #3]

    (844) 0x45060c ADD	X30, X2, #1

    (844) 0x450610 LDR	D27, [X27, X1,LSL #3]

    (844) 0x450614 LDR	D30, [X14, X30,LSL #3]

    (844) 0x450618 LDR	X30, [X8, X30,LSL #3]

    (844) 0x45061c FMUL	D31, D27, D30

    (844) 0x450620 TBZ	X30, #63, 450558

    (844) 0x450624 ORN	X30, XZR, X30

    (844) 0x450628 FADD	D16, D28, D31

    (844) 0x45062c FADD	D17, D29, D31

    (844) 0x450630 LDR	X30, [X23, X30,LSL #3]

    (844) 0x450634 LDR	D6, [X20, X30,LSL #3]

    (844) 0x450638 FADD	D3, D6, D31

    (844) 0x45063c STR	D3, [X20, X30,LSL #3]

    (844) 0x450640 ADD	X30, X2, #2

    (844) 0x450644 LDR	D7, [X27, X1,LSL #3]

    (844) 0x450648 LDR	D2, [X14, X30,LSL #3]

    (844) 0x45064c LDR	X30, [X8, X30,LSL #3]

    (844) 0x450650 FMUL	D8, D7, D2

    (844) 0x450654 TBZ	X30, #63, 450588

    (844) 0x450658 ORN	X30, XZR, X30

    (844) 0x45065c LDR	X30, [X23, X30,LSL #3]

    (844) 0x450660 LDR	D20, [X20, X30,LSL #3]

    (844) 0x450664 FADD	D1, D20, D8

    (844) 0x450668 STR	D1, [X20, X30,LSL #3]

    (844) 0x45066c B	450598

    (844) 0x450670 ORN	X30, XZR, X30

    (844) 0x450674 LDR	X30, [X23, X30,LSL #3]

    (844) 0x450678 LDR	D18, [X20, X30,LSL #3]

    (844) 0x45067c FADD	D19, D18, D16

    (844) 0x450680 STR	D19, [X20, X30,LSL #3]

    (844) 0x450684 B	4505d0

  (843) 0x450688 ORN	X30, XZR, X30

  (843) 0x45068c LDR	X30, [X23, X30,LSL #3]

  (843) 0x450690 LDR	D6, [X20, X30,LSL #3]

  (843) 0x450694 FADD	D3, D6, D8

  (843) 0x450698 STR	D3, [X20, X30,LSL #3]

  (843) 0x45069c B	450510

  (843) 0x4506a0 ORN	X30, XZR, X30

  (843) 0x4506a4 LDR	X30, [X23, X30,LSL #3]

  (843) 0x4506a8 LDR	D28, [X20, X30,LSL #3]

  (843) 0x4506ac FADD	D29, D28, D25

  (843) 0x4506b0 STR	D29, [X20, X30,LSL #3]

  (843) 0x4506b4 B	4504e0

(840) 0x4506b8 LDR	X4, [SP, #136]

(840) 0x4506bc B	44fa6c

  (843) 0x4506c0 ORN	X30, XZR, X30

  (843) 0x4506c4 LDR	X30, [X23, X30,LSL #3]

  (843) 0x4506c8 LDR	D21, [X20, X30,LSL #3]

  (843) 0x4506cc FADD	D22, D21, D18

  (843) 0x4506d0 STR	D22, [X20, X30,LSL #3]

  (843) 0x4506d4 B	4504b0

0x4506d8 ORR	X0, XZR, X22

0x4506dc STP	X9, X10, [SP, #200]

0x4506e0 STR	X2, [SP, #264]

0x4506e4 STR	X12, [SP, #352]

0x4506e8 STR	X13, [SP, #368]

0x4506ec B	44f818

0x4506f0 ORR	X0, XZR, X23

0x4506f4 MOVZ	X1, #8

0x4506f8 STP	X3, X9, [SP, #200]

0x4506fc STR	X10, [SP, #264]

0x450700 STR	X2, [SP, #352]

0x450704 STP	X12, X13, [SP, #368]

0x450708 BL	51674c

0x45070c ORR	X23, XZR, X0

0x450710 LDP	X3, X9, [SP, #200]

0x450714 LDP	X12, X13, [SP, #368]

0x450718 LDR	X10, [SP, #264]

0x45071c LDR	X2, [SP, #352]

0x450720 B	44f7fc

0x450724 MOVZ	X1, #8

0x450728 STP	X3, X9, [SP, #200]

0x45072c STR	X10, [SP, #264]

0x450730 STR	X2, [SP, #352]

0x450734 STP	X12, X13, [SP, #368]

0x450738 BL	51674c

0x45073c STR	X0, [SP, #128]

0x450740 LDP	X3, X9, [SP, #200]

0x450744 LDP	X12, X13, [SP, #368]

0x450748 LDR	X10, [SP, #264]

0x45074c LDR	X2, [SP, #352]

0x450750 B	44f7f8

0x450754 ORR	X0, XZR, X2

0x450758 MOVZ	X1, #8

0x45075c STR	X2, [SP, #128]

0x450760 STP	X3, X9, [SP, #200]

0x450764 STR	X10, [SP, #264]

0x450768 STR	X12, [SP, #352]

0x45076c STR	X13, [SP, #368]

0x450770 BL	51674c

0x450774 ORR	X26, XZR, X0

0x450778 LDR	X2, [SP, #128]

0x45077c LDP	X3, X9, [SP, #200]

0x450780 LDR	X10, [SP, #264]

0x450784 LDR	X12, [SP, #352]

0x450788 LDR	X13, [SP, #368]

0x45078c B	44f7ec

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	par_multi_interp.c:1737-1881
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1737,1746-1881.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 50.83 to 20.00 cycles (2.54x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 50.83 to 10.00 cycles (5.08x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 50.83 to 5.50 cycles (9.24x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 808 bytes. The binary function is storing 696 bytes.

General properties

nb instructions	215
loop length	860
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

26.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	11.50	11.50	13.00	13.00	13.00	13.00	0.50	0.50	0.00	0.00	50.83	50.50	50.67	35.00	35.00
cycles	11.50	11.50	13.00	13.00	13.00	13.00	0.50	0.50	0.00	0.00	50.83	50.50	50.67	35.00	35.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	26.88
Overall L1	50.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 50.83 cycles. At this rate:

16% of peak load performance is reached (15.90 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
28% of peak store performance is reached (13.69 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 44f6c4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #640]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X1, [X0, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X0, #88]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [X0, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X5, [X0, #104]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X6, [X0, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X7, [X0, #128]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X5, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X0, #152]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X3, [SP, #120]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X7, [SP, #152]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [SP, #232]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X1, [SP, #240]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X20, [X0, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X25, X19, [X0, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X24, [X0, #160]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X0, #272]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X11, X12, [X0, #168]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X22, [X0, #280]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X11, [SP, #336]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [X0, #184]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X10, X9, [X0, #296]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X14, [X0, #192]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X13, [SP, #160]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [X0, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X0, #208]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X14, [SP, #360]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X17, [X0, #216]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X15, [SP, #176]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X0, #224]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X16, [SP, #224]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X0, #232]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X17, [SP, #216]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X26, [X0, #240]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X18, [SP, #296]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X27, [X0, #248]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X21, [SP, #288]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X28, [X0, #256]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X26, [SP, #344]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X30, [X0, #264]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X27, [SP, #328]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X1, [X0, #312]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X28, [SP, #280]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X0, #320]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X30, [SP, #184]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X1, [SP, #272]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [X0, #328]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X0, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X4, [SP, #168]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X28, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X0, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X6, [SP, #192]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X0, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X0, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X7, [SP, #320]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X11, [X0, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [X0, #56]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #256]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X5, [X0, #72]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X11, [SP, #312]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X0, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X5, [SP, #304]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X0, [SP, #248]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBNZ X2, 450754 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1090>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X26, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X0, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X0, 450724 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1060>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR XZR, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBNZ X23, 4506f0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x102c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X3, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 4506d8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1014>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STP X9, X10, [SP, #200]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X2, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X12, [SP, #352]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X13, [SP, #368]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 51674c <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [SP, #264]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP X14, X15, [SP, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X4, [SP, #352]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [SP, #368]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X18, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 44f864 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X2, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #255	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STP X14, X15, [SP, #200]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X0, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X4, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X5, [SP, #352]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f370 <@plt_start@+0x180>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X14, X15, [SP, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X4, [SP, #264]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [SP, #352]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 44f898 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X2, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #255	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X0, [SP, #128]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X14, X15, [SP, #200]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X5, [SP, #352]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f370 <@plt_start@+0x180>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X14, X15, [SP, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X4, [SP, #264]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [SP, #352]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X14, X15, [SP, #200]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X5, [SP, #352]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 519580 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 519560 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X6, X7, [SP, #168]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SUB X2, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP X9, X10, [SP, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SDIV X0, X6, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	5-20	5-20
LDR X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [SP, #264]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X3, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X11, [X7, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X14, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
STR X3, [SP, #176]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X18, X14, X0, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR X13, [SP, #352]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X4, X0, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X5, X11, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X15, X6, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X1, X4, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CSEL X6, X15, X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X6, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 4500ec <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xa28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X17, [SP, #360]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X16, X25, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB X18, X24, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR D8, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
LDR X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X16, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X30, X17, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X7, X17, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB X0, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X30, [SP, #168]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X7, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR D8, [SP, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ORR X0, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 516820 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [SP, #128]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 516820 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 516820 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #384	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 516820 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STP X9, X10, [SP, #200]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X2, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X12, [SP, #352]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X13, [SP, #368]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 44f818 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STP X3, X9, [SP, #200]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X10, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X2, [SP, #352]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X12, X13, [SP, #368]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 51674c <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP X3, X9, [SP, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X12, X13, [SP, #368]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X10, [SP, #264]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [SP, #352]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 44f7fc <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STP X3, X9, [SP, #200]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X10, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X2, [SP, #352]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X12, X13, [SP, #368]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 51674c <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X3, X9, [SP, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X12, X13, [SP, #368]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X10, [SP, #264]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [SP, #352]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 44f7f8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X2, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X3, X9, [SP, #200]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X10, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X12, [SP, #352]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X13, [SP, #368]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 51674c <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR X26, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X2, [SP, #128]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X3, X9, [SP, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X10, [SP, #264]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [SP, #352]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [SP, #368]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 44f7ec <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	par_multi_interp.c:1737-1881
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1737,1746-1881.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 50.83 to 5.50 cycles (9.24x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 808 bytes. The binary function is storing 696 bytes.

General properties

nb instructions	215
loop length	860
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

26.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	11.50	11.50	13.00	13.00	13.00	13.00	0.50	0.50	0.00	0.00	50.83	50.50	50.67	35.00	35.00
cycles	11.50	11.50	13.00	13.00	13.00	13.00	0.50	0.50	0.00	0.00	50.83	50.50	50.67	35.00	35.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	26.88
Overall L1	50.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 50.83 cycles. At this rate:

16% of peak load performance is reached (15.90 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
28% of peak store performance is reached (13.69 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 44f6c4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #640]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X1, [X0, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X0, #88]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [X0, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X5, [X0, #104]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X6, [X0, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X7, [X0, #128]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X5, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X0, #152]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X3, [SP, #120]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X7, [SP, #152]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [SP, #232]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X1, [SP, #240]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X20, [X0, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X25, X19, [X0, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X24, [X0, #160]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X0, #272]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X11, X12, [X0, #168]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X22, [X0, #280]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X11, [SP, #336]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [X0, #184]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X10, X9, [X0, #296]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X14, [X0, #192]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X13, [SP, #160]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [X0, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X0, #208]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X14, [SP, #360]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X17, [X0, #216]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X15, [SP, #176]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X0, #224]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X16, [SP, #224]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X0, #232]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X17, [SP, #216]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X26, [X0, #240]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X18, [SP, #296]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X27, [X0, #248]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X21, [SP, #288]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X28, [X0, #256]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X26, [SP, #344]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X30, [X0, #264]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X27, [SP, #328]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X1, [X0, #312]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X28, [SP, #280]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X0, #320]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X30, [SP, #184]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X1, [SP, #272]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [X0, #328]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X0, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X4, [SP, #168]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X28, [X0, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X0, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X6, [SP, #192]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X0, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X0, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X7, [SP, #320]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X11, [X0, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [X0, #56]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #256]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X5, [X0, #72]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X11, [SP, #312]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X0, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X5, [SP, #304]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X0, [SP, #248]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBNZ X2, 450754 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1090>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X26, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X0, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X0, 450724 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1060>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR XZR, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBNZ X23, 4506f0 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x102c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X3, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 4506d8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1014>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STP X9, X10, [SP, #200]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X2, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X12, [SP, #352]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X13, [SP, #368]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 51674c <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [SP, #264]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP X14, X15, [SP, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X4, [SP, #352]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [SP, #368]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X18, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 44f864 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X2, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #255	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STP X14, X15, [SP, #200]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X0, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X4, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X5, [SP, #352]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f370 <@plt_start@+0x180>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X14, X15, [SP, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X4, [SP, #264]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [SP, #352]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 44f898 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x1d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X2, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #255	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X0, [SP, #128]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X14, X15, [SP, #200]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X5, [SP, #352]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f370 <@plt_start@+0x180>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X14, X15, [SP, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X4, [SP, #264]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [SP, #352]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X14, X15, [SP, #200]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X5, [SP, #352]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 519580 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 519560 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X6, X7, [SP, #168]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SUB X2, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP X9, X10, [SP, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SDIV X0, X6, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	5-20	5-20
LDR X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [SP, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [SP, #264]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X3, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X11, [X7, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X14, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
STR X3, [SP, #176]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X18, X14, X0, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR X13, [SP, #352]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X4, X0, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X5, X11, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X15, X6, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X1, X4, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CSEL X6, X15, X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X6, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 4500ec <hypre_BoomerAMGBuildMultipass._omp_fn.10+0xa28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X17, [SP, #360]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X16, X25, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB X18, X24, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR D8, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50
LDR X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X16, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X30, X17, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X7, X17, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB X0, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X30, [SP, #168]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X7, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR D8, [SP, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ORR X0, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 516820 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [SP, #128]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 516820 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 516820 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #384	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 516820 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STP X9, X10, [SP, #200]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X2, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X12, [SP, #352]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X13, [SP, #368]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 44f818 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x154>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STP X3, X9, [SP, #200]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X10, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X2, [SP, #352]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X12, X13, [SP, #368]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 51674c <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP X3, X9, [SP, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X12, X13, [SP, #368]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X10, [SP, #264]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [SP, #352]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 44f7fc <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STP X3, X9, [SP, #200]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X10, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X2, [SP, #352]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X12, X13, [SP, #368]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 51674c <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X3, X9, [SP, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X12, X13, [SP, #368]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X10, [SP, #264]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [SP, #352]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 44f7f8 <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X2, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X3, X9, [SP, #200]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X10, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X12, [SP, #352]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X13, [SP, #368]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 51674c <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR X26, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X2, [SP, #128]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X3, X9, [SP, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X10, [SP, #264]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [SP, #352]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [SP, #368]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 44f7ec <hypre_BoomerAMGBuildMultipass._omp_fn.10+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGBuildMultipass._omp_fn.10–	1.13	0.43
▼Loop 840 - par_multi_interp.c:1774-1876 - exec–	0.17	0.06
▼Loop 845 - par_multi_interp.c:1811-1837 - exec–	0.65	0.21
○Loop 847 - par_multi_interp.c:1816-1822 - exec	0	0
○Loop 846 - par_multi_interp.c:1824-1830 - exec	0	0
○Loop 849 - par_multi_interp.c:1799-1803 - exec	0.31	0.1
○Loop 841 - par_multi_interp.c:1875-1876 - exec	0	0
○Loop 851 - par_multi_interp.c:1782-1787 - exec	0	0
○Loop 850 - par_multi_interp.c:1792-1797 - exec	0	0
○Loop 848 - par_multi_interp.c:1805-1809 - exec	0	0
○Loop 842 - par_multi_interp.c:1873-1874 - exec	0	0
▼Loop 843 - par_multi_interp.c:1840-1867 - exec–	0	0
○Loop 844 - par_multi_interp.c:1851-1860 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code