OV - exec - Function hypre_BoomerAMGBuildMultipass._omp

	Function: hypre_BoomerAMGBuildMultipass._omp_fn.5	Module: exec	Source: par_multi_interp.c:891-1134 [...]	Coverage: 1.09%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 891 - 1134

--------------------------------------------------------------------------------

891:       #pragma omp parallel private(i,my_thread_num,num_threads,thread_start,thread_stop,cnt_nz,cnt_nz_offd,i1,j,j1,j_start,j_end,k1,k,P_marker,P_marker_offd)

[...]

900:           my_thread_num = hypre_GetThreadNum();

901:           num_threads = hypre_NumActiveThreads();

902:           thread_start = (pass_length/num_threads)*my_thread_num;

903:           if (my_thread_num == num_threads-1)

904:           {  thread_stop = pass_length; }

905:           else

906:           {  thread_stop = (pass_length/num_threads)*(my_thread_num+1); }

907:           thread_start += pass_pointer[pass];

908:           thread_stop += pass_pointer[pass];

909:

910:           /* Local initializations */

911:           cnt_nz = 0;

912:           cnt_nz_offd = 0;

913:

914:           /* This block of code is to go to the top of the parallel region starting before

915:            * the loop over num_passes. */

916:           P_marker = hypre_CTAlloc(HYPRE_Int, n_coarse); /* marks points to see if they're counted */

917:           for (i=0; i < n_coarse; i++)

918:           {   P_marker[i] = -1; }

919:           if (new_num_cols_offd == local_index+1)

920:           {

921:              P_marker_offd = hypre_CTAlloc(HYPRE_Int,new_num_cols_offd);

922:              for (i=0; i < new_num_cols_offd; i++)

923:              {   P_marker_offd[i] = -1; }

924:           }

925:           else if (n_coarse_offd)

926:           {

927:              P_marker_offd = hypre_CTAlloc(HYPRE_Int, n_coarse_offd);

[...]

939:           for (i=thread_start; i < thread_stop; i++)

940:           {

941:              i1 = pass_array[i];

942:              P_diag_start[i1] = cnt_nz;

943:              P_offd_start[i1] = cnt_nz_offd;

944:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

945:              {

946:                 j1 = S_diag_j[j];

947:                 if (assigned[j1] == pass-1)

948:                 {

949:                    j_start = P_diag_start[j1];

950:                    j_end = j_start+P_diag_i[j1+1];

951:                    for (k=j_start; k < j_end; k++)

952:                    {

953:                       k1 = P_diag_pass[pass-1][k];

954:                       if (P_marker[k1] != i1)

955:                       {

956:                          cnt_nz++;

957:                          P_diag_i[i1+1]++;

958:                          P_marker[k1] = i1;

959:                       }

960:                    }

961:                    j_start = P_offd_start[j1];

962:                    j_end = j_start+P_offd_i[j1+1];

963:                    for (k=j_start; k < j_end; k++)

964:                    {

965:                       k1 = P_offd_pass[pass-1][k];

966:                       if (P_marker_offd[k1] != i1)

967:                       {

968:                          cnt_nz_offd++;

969:                          P_offd_i[i1+1]++;

970:                          P_marker_offd[k1] = i1;

[...]

976:              for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

977:              {

978:                 j1 = S_offd_j[j];

979:                 if (assigned_offd[j1] == pass-1)

980:                 {

981:                    j_start = Pext_start[j1];

982:                    j_end = j_start+Pext_i[j1+1];

983:                    for (k=j_start; k < j_end; k++)

984:                    {

985:                       k1 = Pext_pass[pass][k];

986:                       if (k1 < 0)

987:                       {

988:                          if (P_marker[-k1-1] != i1)

989:                          {

990:                             cnt_nz++;

991:                             P_diag_i[i1+1]++;

992:                             P_marker[-k1-1] = i1;

993:                          }

994:                       }

995:                       else if (P_marker_offd[k1] != i1)

996:                       {

997:                          cnt_nz_offd++;

998:                          P_offd_i[i1+1]++;

999:                          P_marker_offd[k1] = i1;

[...]

1008:           if(my_thread_num == 0)

1009:           {   max_num_threads[0] = num_threads; }

1010:           cnt_nz_offd_per_thread[my_thread_num] = cnt_nz_offd;

1011:           cnt_nz_per_thread[my_thread_num] = cnt_nz;

1012: #ifdef HYPRE_USING_OPENMP

1013: #pragma omp barrier

1014: #endif

1015:           if(my_thread_num == 0)

1016:           {

1017:               for(i = 1; i < max_num_threads[0]; i++)

1018:               {

1019:                   cnt_nz_offd_per_thread[i] += cnt_nz_offd_per_thread[i-1];

1020:                   cnt_nz_per_thread[i] += cnt_nz_per_thread[i-1];

1021:               }

1022:           }

1023: #ifdef HYPRE_USING_OPENMP

1024: #pragma omp barrier

1025: #endif

1026:           if(my_thread_num > 0)

1027:           {

1028:               /* update this thread's section of P_diag_start and P_offd_start

1029:                * with the num of nz's counted by previous threads */

1030:               for (i=thread_start; i < thread_stop; i++)

1031:                {

1032:                    i1 = pass_array[i];

1033:                    P_diag_start[i1] += cnt_nz_per_thread[my_thread_num-1];

1034:                    P_offd_start[i1] += cnt_nz_offd_per_thread[my_thread_num-1];

[...]

1040:               cnt_nz = cnt_nz_per_thread[max_num_threads[0]-1];

1041:               cnt_nz_offd = cnt_nz_offd_per_thread[max_num_threads[0]-1];

1042:

1043:               /* Updated total nz count */

1044:               total_nz += cnt_nz;

1045:               total_nz_offd += cnt_nz_offd;

1046:

1047:               /* Allocate P_diag_pass and P_offd_pass for all threads */

1048:               P_diag_pass[pass] = hypre_CTAlloc(HYPRE_Int, cnt_nz);

1049:               if (cnt_nz_offd)

1050:                  P_offd_pass[pass] = hypre_CTAlloc(HYPRE_Int, cnt_nz_offd);

1051:               else if (num_procs > 1)

1052:                  P_offd_pass[pass] = NULL;

1053:           }

1054: #ifdef HYPRE_USING_OPENMP

1055: #pragma omp barrier

[...]

1062:               cnt_nz = cnt_nz_per_thread[my_thread_num-1];

1063:               cnt_nz_offd = cnt_nz_offd_per_thread[my_thread_num-1];

1064:           }

1065:           else

1066:           {

1067:               cnt_nz = 0;

1068:               cnt_nz_offd = 0;

1069:           }

1070:

1071:           /* Set P_diag_pass and P_offd_pass */

1072:           for (i=thread_start; i < thread_stop; i++)

1073:           {

1074:              i1 = pass_array[i];

1075:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1076:              {

1077:                 j1 = S_diag_j[j];

1078:                 if (assigned[j1] == pass-1)

1079:                 {

1080:                    j_start = P_diag_start[j1];

1081:                    j_end = j_start+P_diag_i[j1+1];

1082:                    for (k=j_start; k < j_end; k++)

1083:                    {

1084:                       k1 = P_diag_pass[pass-1][k];

1085:                       if (P_marker[k1] != -i1-1)

1086:                       {

1087:                           P_diag_pass[pass][cnt_nz++] = k1;

1088:                           P_marker[k1] = -i1-1;

1089:                       }

1090:                    }

1091:                    j_start = P_offd_start[j1];

1092:                    j_end = j_start+P_offd_i[j1+1];

1093:                    for (k=j_start; k < j_end; k++)

1094:                    {

1095:                       k1 = P_offd_pass[pass-1][k];

1096:                       if (P_marker_offd[k1] != -i1-1)

1097:                       {

1098:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1099:                          P_marker_offd[k1] = -i1-1;

1100:                       }

1101:                    }

1102:                 }

1103:              }

1104:              for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

1105:              {

1106:                 j1 = S_offd_j[j];

1107:                 if (assigned_offd[j1] == pass-1)

1108:                 {

1109:                    j_start = Pext_start[j1];

1110:                    j_end = j_start+Pext_i[j1+1];

1111:                    for (k=j_start; k < j_end; k++)

1112:                    {

1113:                       k1 = Pext_pass[pass][k];

1114:                       if (k1 < 0)

1115:                       {

1116:                          if (P_marker[-k1-1] != -i1-1)

1117:                          {

1118:                             P_diag_pass[pass][cnt_nz++] = -k1-1;

1119:                             P_marker[-k1-1] = -i1-1;

1120:                          }

1121:                       }

1122:                       else if (P_marker_offd[k1] != -i1-1)

1123:                       {

1124:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1125:                          P_marker_offd[k1] = -i1-1;

[...]

1132:           hypre_TFree(P_marker);

1133:           if ( (n_coarse_offd) || (new_num_cols_offd  == local_index+1) )

1134:           {    hypre_TFree(P_marker_offd); }

0x44c340 STP	X29, X30, [SP, #736]!

0x44c344 ADD	X29, SP, #0

0x44c348 STP	X25, X26, [SP, #64]

0x44c34c STP	X27, X28, [SP, #80]

0x44c350 LDP	X7, X27, [X0]

0x44c354 LDP	X6, X26, [X0, #16]

0x44c358 LDP	X9, X8, [X0, #72]

0x44c35c STP	X19, X20, [SP, #16]

0x44c360 LDR	X1, [X0, #48]

0x44c364 STP	X21, X22, [SP, #32]

0x44c368 LDR	X2, [X0, #56]

0x44c36c STP	X23, X24, [SP, #48]

0x44c370 LDR	X3, [X0, #64]

0x44c374 STR	X2, [SP, #104]

0x44c378 STR	X1, [SP, #128]

0x44c37c STP	X9, X6, [SP, #248]

0x44c380 STR	X3, [SP, #112]

0x44c384 STR	X7, [SP, #264]

0x44c388 STR	X0, [SP, #280]

0x44c38c LDP	X23, X21, [X0, #32]

0x44c390 LDR	X20, [X0, #200]

0x44c394 STR	X8, [SP, #240]

0x44c398 LDP	X5, X4, [X0, #88]

0x44c39c LDP	X28, X11, [X0, #136]

0x44c3a0 LDP	X25, X24, [X0, #152]

0x44c3a4 STR	X11, [SP, #216]

0x44c3a8 LDR	X10, [X0, #104]

0x44c3ac STR	X5, [SP, #232]

0x44c3b0 LDR	X13, [X0, #112]

0x44c3b4 LDR	X15, [X0, #128]

0x44c3b8 STR	X10, [SP, #96]

0x44c3bc LDR	X12, [X0, #184]

0x44c3c0 STR	X13, [SP, #120]

0x44c3c4 LDR	X14, [X0, #192]

0x44c3c8 UBFM	X22, X15, #61, #60

0x44c3cc STR	X15, [SP, #176]

0x44c3d0 LDR	X16, [X0, #208]

0x44c3d4 LDP	X17, X0, [X0, #216]

0x44c3d8 STP	X12, X4, [SP, #136]

0x44c3dc STP	X0, X17, [SP, #160]

0x44c3e0 STR	X14, [SP, #208]

0x44c3e4 STR	X16, [SP, #224]

0x44c3e8 BL	519580

0x44c3ec STR	X0, [SP, #152]

0x44c3f0 BL	519560

0x44c3f4 ORR	X18, XZR, X0

0x44c3f8 LDR	X6, [SP, #112]

0x44c3fc ORR	X0, XZR, X28

0x44c400 SUB	X7, X18, #1

0x44c404 SDIV	X3, X20, X18

0x44c408 LDR	X1, [SP, #176]

0x44c40c STR	X18, [SP, #272]

0x44c410 LDR	X8, [SP, #152]

0x44c414 LDR	X9, [X6, X1,LSL #3]

0x44c418 MOVZ	X1, #8

0x44c41c CMP	X8, X7

0x44c420 MADD	X2, X8, X3, XZR

0x44c424 ADD	X4, X2, X9

0x44c428 ADD	X5, X3, X2

0x44c42c CSEL	X20, X5, X20, #1

0x44c430 ADD	X10, X20, X9

0x44c434 STP	X2, X20, [SP, #184]

0x44c438 STR	X10, [SP, #112]

0x44c43c STR	X4, [SP, #200]

0x44c440 BL	51674c

0x44c444 CMP	X28, #0

0x44c448 ORR	X20, XZR, X0

0x44c44c LDR	X12, [SP, #144]

0x44c450 LDP	X14, X8, [SP, #232]

0x44c454 LDP	X9, X6, [SP, #248]

0x44c458 LDR	X7, [SP, #264]

0x44c45c B.LE	44c48c

0x44c460 UBFM	X2, X28, #61, #60

0x44c464 MOVZ	W1, #255

0x44c468 STR	X12, [SP, #144]

0x44c46c STP	X14, X8, [SP, #232]

0x44c470 STP	X9, X6, [SP, #248]

0x44c474 STR	X7, [SP, #264]

0x44c478 BL	40f370

0x44c47c LDR	X12, [SP, #144]

0x44c480 LDP	X14, X8, [SP, #232]

0x44c484 LDP	X9, X6, [SP, #248]

0x44c488 LDR	X7, [SP, #264]

0x44c48c LDR	X30, [SP, #136]

0x44c490 LDR	X28, [SP, #208]

0x44c494 ADD	X11, X30, #1

0x44c498 STR	X11, [SP, #232]

0x44c49c CMP	X28, X11

0x44c4a0 B.EQ	44d584

0x44c4a4 LDR	X0, [SP, #216]

0x44c4a8 CBNZ	X0, 44d538

(801) 0x44c4ac LDP	X13, X15, [SP, #176]

(801) 0x44c4b0 ADD	X16, X14, X22

(801) 0x44c4b4 ADD	X17, X12, X22

(801) 0x44c4b8 MOVZ	X10, #0

(801) 0x44c4bc MOVZ	X11, #0

(801) 0x44c4c0 STR	X16, [SP, #136]

(801) 0x44c4c4 LDR	X0, [SP, #192]

(801) 0x44c4c8 STR	X17, [SP, #144]

(801) 0x44c4cc SUB	X13, X13, #1

(801) 0x44c4d0 LDR	X18, [SP, #200]

(801) 0x44c4d4 CMP	X0, X15

(801) 0x44c4d8 B.LE	44c958

(801) 0x44c4dc LDP	X28, X30, [SP, #120]

(801) 0x44c4e0 STP	X12, X14, [SP, #240]

  (810) 0x44c4e4 LDR	X1, [SP, #104]

  (810) 0x44c4e8 LDR	X0, [X1, X18,LSL #3]

  (810) 0x44c4ec UBFM	X3, X0, #61, #60

  (810) 0x44c4f0 STR	X11, [X9, X0,LSL #3]

  (810) 0x44c4f4 ADD	X1, X3, #8

  (810) 0x44c4f8 STR	X10, [X8, X0,LSL #3]

  (810) 0x44c4fc LDR	X15, [X7, X1]

  (810) 0x44c500 ADD	X17, X7, X1

  (810) 0x44c504 LDR	X2, [X7, X0,LSL #3]

  (810) 0x44c508 CMP	X2, X15

  (810) 0x44c50c B.LT	44c520

  (810) 0x44c510 B	44c820

    (813) 0x44c514 ADD	X2, X2, #1

    (813) 0x44c518 CMP	X2, X15

    (813) 0x44c51c B.GE	44c820

    (813) 0x44c520 LDR	X3, [X27, X2,LSL #3]

    (813) 0x44c524 LDR	X4, [X25, X3,LSL #3]

    (813) 0x44c528 UBFM	X5, X3, #61, #60

    (813) 0x44c52c CMP	X4, X13

    (813) 0x44c530 B.NE	44c514

    (813) 0x44c534 ADD	X5, X5, #8

    (813) 0x44c538 LDR	X15, [X9, X3,LSL #3]

    (813) 0x44c53c LDR	X12, [X23, X5]

    (813) 0x44c540 ADD	X14, X15, X12

    (813) 0x44c544 CMP	X15, X14

    (813) 0x44c548 B.GE	44c6a4

    (813) 0x44c54c LDR	X16, [SP, #136]

    (813) 0x44c550 LDUR	X16, [X16, #504]

    (813) 0x44c554 ADD	X14, X16, X14,LSL #3

    (813) 0x44c558 ADD	X4, X16, X15,LSL #3

    (813) 0x44c55c SUB	X12, X14, X4

    (813) 0x44c560 SUB	X12, X12, #8

    (813) 0x44c564 UBFM	X12, X12, #3, #63

    (813) 0x44c568 ADD	X12, X12, #1

    (813) 0x44c56c ANDS	X12, X12, #4160

    (813) 0x44c570 B.EQ	44c604

    (813) 0x44c574 CMP	X12, #1

    (813) 0x44c578 B.EQ	44c5d4

    (813) 0x44c57c CMP	X12, #2

    (813) 0x44c580 B.EQ	44c5ac

    (813) 0x44c584 LDR	X16, [X16, X15,LSL #3]

    (813) 0x44c588 LDR	X15, [X20, X16,LSL #3]

    (813) 0x44c58c CMP	X0, X15

    (813) 0x44c590 B.EQ	44c5a8

    (813) 0x44c594 LDR	X12, [X23, X1]

    (813) 0x44c598 ADD	X11, X11, #1

    (813) 0x44c59c ADD	X15, X12, #1

    (813) 0x44c5a0 STR	X15, [X23, X1]

    (813) 0x44c5a4 STR	X0, [X20, X16,LSL #3]

    (813) 0x44c5a8 ADD	X4, X4, #8

    (813) 0x44c5ac LDR	X16, [X4]

    (813) 0x44c5b0 LDR	X12, [X20, X16,LSL #3]

    (813) 0x44c5b4 CMP	X0, X12

    (813) 0x44c5b8 B.EQ	44c5d0

    (813) 0x44c5bc LDR	X15, [X23, X1]

    (813) 0x44c5c0 ADD	X11, X11, #1

    (813) 0x44c5c4 ADD	X12, X15, #1

    (813) 0x44c5c8 STR	X12, [X23, X1]

    (813) 0x44c5cc STR	X0, [X20, X16,LSL #3]

    (813) 0x44c5d0 ADD	X4, X4, #8

    (813) 0x44c5d4 LDR	X16, [X4]

    (813) 0x44c5d8 LDR	X15, [X20, X16,LSL #3]

    (813) 0x44c5dc CMP	X0, X15

    (813) 0x44c5e0 B.EQ	44c5f8

    (813) 0x44c5e4 LDR	X12, [X23, X1]

    (813) 0x44c5e8 ADD	X11, X11, #1

    (813) 0x44c5ec ADD	X15, X12, #1

    (813) 0x44c5f0 STR	X15, [X23, X1]

    (813) 0x44c5f4 STR	X0, [X20, X16,LSL #3]

    (813) 0x44c5f8 ADD	X4, X4, #8

    (813) 0x44c5fc CMP	X14, X4

    (813) 0x44c600 B.EQ	44c6a4

      (815) 0x44c604 LDR	X16, [X4]

      (815) 0x44c608 LDR	X12, [X20, X16,LSL #3]

      (815) 0x44c60c CMP	X0, X12

      (815) 0x44c610 B.EQ	44c628

      (815) 0x44c614 LDR	X15, [X23, X1]

      (815) 0x44c618 ADD	X11, X11, #1

      (815) 0x44c61c ADD	X12, X15, #1

      (815) 0x44c620 STR	X12, [X23, X1]

      (815) 0x44c624 STR	X0, [X20, X16,LSL #3]

      (815) 0x44c628 LDR	X16, [X4, #8]

      (815) 0x44c62c ADD	X12, X4, #8

      (815) 0x44c630 LDR	X4, [X20, X16,LSL #3]

      (815) 0x44c634 CMP	X0, X4

      (815) 0x44c638 B.EQ	44c650

      (815) 0x44c63c LDR	X15, [X23, X1]

      (815) 0x44c640 ADD	X11, X11, #1

      (815) 0x44c644 ADD	X4, X15, #1

      (815) 0x44c648 STR	X4, [X23, X1]

      (815) 0x44c64c STR	X0, [X20, X16,LSL #3]

      (815) 0x44c650 LDR	X15, [X12, #8]

      (815) 0x44c654 ADD	X4, X12, #24

      (815) 0x44c658 LDR	X16, [X20, X15,LSL #3]

      (815) 0x44c65c CMP	X0, X16

      (815) 0x44c660 B.EQ	44c678

      (815) 0x44c664 LDR	X16, [X23, X1]

      (815) 0x44c668 ADD	X11, X11, #1

      (815) 0x44c66c ADD	X16, X16, #1

      (815) 0x44c670 STR	X16, [X23, X1]

      (815) 0x44c674 STR	X0, [X20, X15,LSL #3]

      (815) 0x44c678 LDR	X12, [X12, #16]

      (815) 0x44c67c LDR	X15, [X20, X12,LSL #3]

      (815) 0x44c680 CMP	X0, X15

      (815) 0x44c684 B.EQ	44c69c

      (815) 0x44c688 LDR	X16, [X23, X1]

      (815) 0x44c68c ADD	X11, X11, #1

      (815) 0x44c690 ADD	X15, X16, #1

      (815) 0x44c694 STR	X15, [X23, X1]

      (815) 0x44c698 STR	X0, [X20, X12,LSL #3]

      (815) 0x44c69c CMP	X14, X4

      (815) 0x44c6a0 B.NE	44c604

    (813) 0x44c6a4 LDR	X12, [X8, X3,LSL #3]

    (813) 0x44c6a8 LDR	X3, [X21, X5]

    (813) 0x44c6ac ADD	X5, X12, X3

    (813) 0x44c6b0 CMP	X12, X5

    (813) 0x44c6b4 B.GE	44c810

    (813) 0x44c6b8 LDR	X14, [SP, #144]

    (813) 0x44c6bc LDUR	X16, [X14, #504]

    (813) 0x44c6c0 ADD	X15, X16, X5,LSL #3

    (813) 0x44c6c4 ADD	X3, X16, X12,LSL #3

    (813) 0x44c6c8 SUB	X4, X15, X3

    (813) 0x44c6cc SUB	X5, X4, #8

    (813) 0x44c6d0 UBFM	X14, X5, #3, #63

    (813) 0x44c6d4 ADD	X4, X14, #1

    (813) 0x44c6d8 ANDS	X5, X4, #4160

    (813) 0x44c6dc B.EQ	44c770

    (813) 0x44c6e0 CMP	X5, #1

    (813) 0x44c6e4 B.EQ	44c740

    (813) 0x44c6e8 CMP	X5, #2

    (813) 0x44c6ec B.EQ	44c718

    (813) 0x44c6f0 LDR	X16, [X16, X12,LSL #3]

    (813) 0x44c6f4 LDR	X12, [X19, X16,LSL #3]

    (813) 0x44c6f8 CMP	X0, X12

    (813) 0x44c6fc B.EQ	44c714

    (813) 0x44c700 LDR	X14, [X21, X1]

    (813) 0x44c704 ADD	X10, X10, #1

    (813) 0x44c708 ADD	X4, X14, #1

    (813) 0x44c70c STR	X4, [X21, X1]

    (813) 0x44c710 STR	X0, [X19, X16,LSL #3]

    (813) 0x44c714 ADD	X3, X3, #8

    (813) 0x44c718 LDR	X5, [X3]

    (813) 0x44c71c LDR	X16, [X19, X5,LSL #3]

    (813) 0x44c720 CMP	X0, X16

    (813) 0x44c724 B.EQ	44c73c

    (813) 0x44c728 LDR	X12, [X21, X1]

    (813) 0x44c72c ADD	X10, X10, #1

    (813) 0x44c730 ADD	X14, X12, #1

    (813) 0x44c734 STR	X14, [X21, X1]

    (813) 0x44c738 STR	X0, [X19, X5,LSL #3]

    (813) 0x44c73c ADD	X3, X3, #8

    (813) 0x44c740 LDR	X4, [X3]

    (813) 0x44c744 LDR	X5, [X19, X4,LSL #3]

    (813) 0x44c748 CMP	X0, X5

    (813) 0x44c74c B.EQ	44c764

    (813) 0x44c750 LDR	X16, [X21, X1]

    (813) 0x44c754 ADD	X10, X10, #1

    (813) 0x44c758 ADD	X12, X16, #1

    (813) 0x44c75c STR	X12, [X21, X1]

    (813) 0x44c760 STR	X0, [X19, X4,LSL #3]

    (813) 0x44c764 ADD	X3, X3, #8

    (813) 0x44c768 CMP	X15, X3

    (813) 0x44c76c B.EQ	44c810

      (814) 0x44c770 LDR	X14, [X3]

      (814) 0x44c774 LDR	X4, [X19, X14,LSL #3]

      (814) 0x44c778 CMP	X0, X4

      (814) 0x44c77c B.EQ	44c794

      (814) 0x44c780 LDR	X5, [X21, X1]

      (814) 0x44c784 ADD	X10, X10, #1

      (814) 0x44c788 ADD	X16, X5, #1

      (814) 0x44c78c STR	X16, [X21, X1]

      (814) 0x44c790 STR	X0, [X19, X14,LSL #3]

      (814) 0x44c794 LDR	X12, [X3, #8]

      (814) 0x44c798 ADD	X4, X3, #8

      (814) 0x44c79c LDR	X3, [X19, X12,LSL #3]

      (814) 0x44c7a0 CMP	X0, X3

      (814) 0x44c7a4 B.EQ	44c7bc

      (814) 0x44c7a8 LDR	X14, [X21, X1]

      (814) 0x44c7ac ADD	X10, X10, #1

      (814) 0x44c7b0 ADD	X5, X14, #1

      (814) 0x44c7b4 STR	X5, [X21, X1]

      (814) 0x44c7b8 STR	X0, [X19, X12,LSL #3]

      (814) 0x44c7bc LDR	X16, [X4, #8]

      (814) 0x44c7c0 ADD	X3, X4, #24

      (814) 0x44c7c4 LDR	X12, [X19, X16,LSL #3]

      (814) 0x44c7c8 CMP	X0, X12

      (814) 0x44c7cc B.EQ	44c7e4

      (814) 0x44c7d0 LDR	X14, [X21, X1]

      (814) 0x44c7d4 ADD	X10, X10, #1

      (814) 0x44c7d8 ADD	X5, X14, #1

      (814) 0x44c7dc STR	X5, [X21, X1]

      (814) 0x44c7e0 STR	X0, [X19, X16,LSL #3]

      (814) 0x44c7e4 LDR	X4, [X4, #16]

      (814) 0x44c7e8 LDR	X16, [X19, X4,LSL #3]

      (814) 0x44c7ec CMP	X0, X16

      (814) 0x44c7f0 B.EQ	44c808

      (814) 0x44c7f4 LDR	X12, [X21, X1]

      (814) 0x44c7f8 ADD	X10, X10, #1

      (814) 0x44c7fc ADD	X14, X12, #1

      (814) 0x44c800 STR	X14, [X21, X1]

      (814) 0x44c804 STR	X0, [X19, X4,LSL #3]

      (814) 0x44c808 CMP	X15, X3

      (814) 0x44c80c B.NE	44c770

    (813) 0x44c810 LDR	X15, [X17]

    (813) 0x44c814 ADD	X2, X2, #1

    (813) 0x44c818 CMP	X2, X15

    (813) 0x44c81c B.LT	44c520

  (810) 0x44c820 LDR	X2, [X6, X0,LSL #3]

  (810) 0x44c824 ADD	X15, X6, X1

  (810) 0x44c828 LDR	X14, [X6, X1]

  (810) 0x44c82c CMP	X2, X14

  (810) 0x44c830 B.LT	44c844

  (810) 0x44c834 B	44c944

    (811) 0x44c838 ADD	X2, X2, #1

    (811) 0x44c83c CMP	X2, X14

    (811) 0x44c840 B.GE	44c944

    (811) 0x44c844 LDR	X17, [X26, X2,LSL #3]

    (811) 0x44c848 LDR	X3, [X24, X17,LSL #3]

    (811) 0x44c84c UBFM	X5, X17, #61, #60

    (811) 0x44c850 CMP	X3, X13

    (811) 0x44c854 B.NE	44c838

    (811) 0x44c858 ADD	X4, X28, X5

    (811) 0x44c85c LDR	X16, [X30, X17,LSL #3]

    (811) 0x44c860 LDR	X12, [X4, #8]

    (811) 0x44c864 ADD	X17, X16, X12

    (811) 0x44c868 CMP	X16, X17

    (811) 0x44c86c B.GE	44c838

    (811) 0x44c870 LDR	X14, [SP, #96]

    (811) 0x44c874 LDR	X12, [X14, X22]

    (811) 0x44c878 ADD	X5, X12, X17,LSL #3

    (811) 0x44c87c ADD	X3, X12, X16,LSL #3

    (811) 0x44c880 SUB	X4, X5, X3

    (811) 0x44c884 SUB	X17, X4, #8

    (811) 0x44c888 UBFM	X14, X17, #3, #63

    (811) 0x44c88c ADD	X4, X14, #1

    (811) 0x44c890 ANDS	X17, X4, #4160

    (811) 0x44c894 B.EQ	44cb74

    (811) 0x44c898 CMP	X17, #1

    (811) 0x44c89c B.EQ	44c900

    (811) 0x44c8a0 CMP	X17, #2

    (811) 0x44c8a4 B.EQ	44c8d4

    (811) 0x44c8a8 LDR	X16, [X12, X16,LSL #3]

    (811) 0x44c8ac TBNZ	X16, #63, 44cc7c

    (811) 0x44c8b0 LDR	X12, [X19, X16,LSL #3]

    (811) 0x44c8b4 CMP	X0, X12

    (811) 0x44c8b8 B.EQ	44c8d0

    (811) 0x44c8bc LDR	X14, [X21, X1]

    (811) 0x44c8c0 ADD	X10, X10, #1

    (811) 0x44c8c4 ADD	X4, X14, #1

    (811) 0x44c8c8 STR	X4, [X21, X1]

    (811) 0x44c8cc STR	X0, [X19, X16,LSL #3]

    (811) 0x44c8d0 ADD	X3, X3, #8

    (811) 0x44c8d4 LDR	X4, [X3]

    (811) 0x44c8d8 TBNZ	X4, #63, 44cc54

    (811) 0x44c8dc LDR	X17, [X19, X4,LSL #3]

    (811) 0x44c8e0 CMP	X0, X17

    (811) 0x44c8e4 B.EQ	44c8fc

    (811) 0x44c8e8 LDR	X16, [X21, X1]

    (811) 0x44c8ec ADD	X10, X10, #1

    (811) 0x44c8f0 ADD	X12, X16, #1

    (811) 0x44c8f4 STR	X12, [X21, X1]

    (811) 0x44c8f8 STR	X0, [X19, X4,LSL #3]

    (811) 0x44c8fc ADD	X3, X3, #8

    (811) 0x44c900 LDR	X14, [X3]

    (811) 0x44c904 TBNZ	X14, #63, 44cc2c

    (811) 0x44c908 LDR	X12, [X19, X14,LSL #3]

    (811) 0x44c90c CMP	X0, X12

    (811) 0x44c910 B.EQ	44c928

    (811) 0x44c914 LDR	X4, [X21, X1]

    (811) 0x44c918 ADD	X10, X10, #1

    (811) 0x44c91c ADD	X17, X4, #1

    (811) 0x44c920 STR	X17, [X21, X1]

    (811) 0x44c924 STR	X0, [X19, X14,LSL #3]

    (811) 0x44c928 ADD	X3, X3, #8

    (811) 0x44c92c CMP	X5, X3

    (811) 0x44c930 B.NE	44cb74

    (811) 0x44c934 LDR	X14, [X15]

    (811) 0x44c938 ADD	X2, X2, #1

    (811) 0x44c93c CMP	X2, X14

    (811) 0x44c940 B.LT	44c844

  (810) 0x44c944 LDR	X5, [SP, #112]

  (810) 0x44c948 ADD	X18, X18, #1

  (810) 0x44c94c CMP	X5, X18

  (810) 0x44c950 B.GT	44c4e4

(801) 0x44c954 LDP	X12, X14, [SP, #240]

(801) 0x44c958 LDR	X4, [SP, #152]

(801) 0x44c95c CBNZ	X4, 44cca4

(801) 0x44c960 LDR	X1, [SP, #224]

(801) 0x44c964 LDP	X5, X28, [SP, #160]

(801) 0x44c968 STR	X14, [SP, #152]

(801) 0x44c96c LDR	X0, [SP, #272]

(801) 0x44c970 STP	X8, X9, [SP, #240]

(801) 0x44c974 STP	X6, X7, [SP, #256]

(801) 0x44c978 STR	X0, [X1]

(801) 0x44c97c STR	X10, [X5], #504

(801) 0x44c980 STR	X11, [X28], #504

(801) 0x44c984 STP	X5, X12, [SP, #136]

(801) 0x44c988 BL	40f590

(801) 0x44c98c LDR	X12, [SP, #224]

(801) 0x44c990 MOVZ	X4, #1

(801) 0x44c994 LDP	X13, X14, [SP, #136]

(801) 0x44c998 LDP	X8, X9, [SP, #240]

(801) 0x44c99c LDP	X6, X7, [SP, #256]

(801) 0x44c9a0 LDR	X10, [X12]

(801) 0x44c9a4 LDR	X15, [SP, #152]

(801) 0x44c9a8 CMP	X10, X4

(801) 0x44c9ac B.LE	44c9f0

(801) 0x44c9b0 LDP	X17, X30, [SP, #160]

(801) 0x44c9b4 LDR	X3, [SP, #224]

(801) 0x44c9b8 HINT	#0

(801) 0x44c9bc HINT	#0

  (809) 0x44c9c0 LDR	X16, [X17, X4,LSL #3]

  (809) 0x44c9c4 LDR	X11, [X13, X4,LSL #3]

  (809) 0x44c9c8 ADD	X18, X16, X11

  (809) 0x44c9cc STR	X18, [X17, X4,LSL #3]

  (809) 0x44c9d0 LDR	X2, [X30, X4,LSL #3]

  (809) 0x44c9d4 LDR	X5, [X28, X4,LSL #3]

  (809) 0x44c9d8 ADD	X1, X2, X5

  (809) 0x44c9dc STR	X1, [X30, X4,LSL #3]

  (809) 0x44c9e0 ADD	X4, X4, #1

  (809) 0x44c9e4 LDR	X0, [X3]

  (809) 0x44c9e8 CMP	X0, X4

  (809) 0x44c9ec B.GT	44c9c0

(801) 0x44c9f0 STP	X14, X15, [SP, #136]

(801) 0x44c9f4 STR	X8, [SP, #152]

(801) 0x44c9f8 STP	X9, X6, [SP, #240]

(801) 0x44c9fc STR	X7, [SP, #256]

(801) 0x44ca00 BL	40f590

(801) 0x44ca04 LDP	X18, X5, [SP, #136]

(801) 0x44ca08 LDP	X9, X6, [SP, #240]

(801) 0x44ca0c LDR	X8, [SP, #152]

(801) 0x44ca10 LDR	X7, [SP, #256]

(801) 0x44ca14 STR	X8, [SP, #152]

(801) 0x44ca18 MOVZ	X1, #8

(801) 0x44ca1c LDR	X28, [SP, #224]

(801) 0x44ca20 STP	X9, X6, [SP, #240]

(801) 0x44ca24 LDR	X8, [SP, #160]

(801) 0x44ca28 STR	X7, [SP, #256]

(801) 0x44ca2c LDR	X13, [X28]

(801) 0x44ca30 STP	X18, X5, [SP, #136]

(801) 0x44ca34 LDR	X12, [SP, #168]

(801) 0x44ca38 UBFM	X14, X13, #61, #60

(801) 0x44ca3c LDR	X9, [SP, #280]

(801) 0x44ca40 SUB	X15, X14, #8

(801) 0x44ca44 LDR	X28, [X8, X15]

(801) 0x44ca48 LDR	X0, [X12, X15]

(801) 0x44ca4c LDR	X6, [X9, #120]

(801) 0x44ca50 LDR	X7, [X9, #176]

(801) 0x44ca54 ADD	X10, X6, X0

(801) 0x44ca58 ADD	X4, X7, X28

(801) 0x44ca5c STR	X10, [X9, #120]

(801) 0x44ca60 STR	X4, [X9, #176]

(801) 0x44ca64 BL	51674c

(801) 0x44ca68 LDP	X11, X18, [SP, #136]

(801) 0x44ca6c LDP	X5, X13, [SP, #240]

(801) 0x44ca70 LDR	X3, [SP, #176]

(801) 0x44ca74 LDR	X2, [SP, #152]

(801) 0x44ca78 LDR	X14, [SP, #256]

(801) 0x44ca7c STR	X0, [X18, X3,LSL #3]

(801) 0x44ca80 CBNZ	X28, 44d5e4

(801) 0x44ca84 LDR	X17, [SP, #280]

(801) 0x44ca88 LDR	X30, [X17, #168]

(801) 0x44ca8c LDR	X16, [X30]

(801) 0x44ca90 CMP	X16, #1

(801) 0x44ca94 B.LE	44ca9c

(801) 0x44ca98 STR	XZR, [X11, X3,LSL #3]

(801) 0x44ca9c STP	X11, X18, [SP, #136]

(801) 0x44caa0 STP	X2, X5, [SP, #152]

(801) 0x44caa4 STR	X13, [SP, #168]

(801) 0x44caa8 STR	X14, [SP, #224]

(801) 0x44caac BL	40f590

(801) 0x44cab0 MOVZ	X1, #0

(801) 0x44cab4 MOVZ	X3, #0

(801) 0x44cab8 LDP	X4, X5, [SP, #136]

(801) 0x44cabc LDP	X15, X9, [SP, #152]

(801) 0x44cac0 LDR	X6, [SP, #168]

(801) 0x44cac4 LDR	X7, [SP, #224]

(801) 0x44cac8 B	44cecc

      (812) 0x44cacc LDR	X16, [X19, X17,LSL #3]

      (812) 0x44cad0 CMP	X0, X16

      (812) 0x44cad4 B.EQ	44caec

      (812) 0x44cad8 LDR	X14, [X21, X1]

      (812) 0x44cadc ADD	X10, X10, #1

      (812) 0x44cae0 ADD	X12, X14, #1

      (812) 0x44cae4 STR	X12, [X21, X1]

      (812) 0x44cae8 STR	X0, [X19, X17,LSL #3]

      (812) 0x44caec LDR	X4, [X3, #8]

      (812) 0x44caf0 ADD	X3, X3, #8

      (812) 0x44caf4 TBNZ	X4, #63, 44cbac

      (812) 0x44caf8 LDR	X12, [X19, X4,LSL #3]

      (812) 0x44cafc CMP	X0, X12

      (812) 0x44cb00 B.EQ	44cb18

      (812) 0x44cb04 LDR	X17, [X21, X1]

      (812) 0x44cb08 ADD	X10, X10, #1

      (812) 0x44cb0c ADD	X16, X17, #1

      (812) 0x44cb10 STR	X16, [X21, X1]

      (812) 0x44cb14 STR	X0, [X19, X4,LSL #3]

      (812) 0x44cb18 LDR	X16, [X3, #8]

      (812) 0x44cb1c TBNZ	X16, #63, 44cbd8

      (812) 0x44cb20 LDR	X14, [X19, X16,LSL #3]

      (812) 0x44cb24 CMP	X0, X14

      (812) 0x44cb28 B.EQ	44cb40

      (812) 0x44cb2c LDR	X4, [X21, X1]

      (812) 0x44cb30 ADD	X10, X10, #1

      (812) 0x44cb34 ADD	X12, X4, #1

      (812) 0x44cb38 STR	X12, [X21, X1]

      (812) 0x44cb3c STR	X0, [X19, X16,LSL #3]

      (812) 0x44cb40 LDR	X17, [X3, #16]

      (812) 0x44cb44 TBNZ	X17, #63, 44cc04

      (812) 0x44cb48 LDR	X12, [X19, X17,LSL #3]

      (812) 0x44cb4c CMP	X0, X12

      (812) 0x44cb50 B.EQ	44cb68

      (812) 0x44cb54 LDR	X16, [X21, X1]

      (812) 0x44cb58 ADD	X10, X10, #1

      (812) 0x44cb5c ADD	X14, X16, #1

      (812) 0x44cb60 STR	X14, [X21, X1]

      (812) 0x44cb64 STR	X0, [X19, X17,LSL #3]

      (812) 0x44cb68 ADD	X3, X3, #24

      (812) 0x44cb6c CMP	X5, X3

      (812) 0x44cb70 B.EQ	44c934

      (812) 0x44cb74 LDR	X17, [X3]

      (812) 0x44cb78 TBZ	X17, #63, 44cacc

      (812) 0x44cb7c ORN	X4, XZR, X17

      (812) 0x44cb80 LDR	X17, [X20, X4,LSL #3]

      (812) 0x44cb84 CMP	X0, X17

      (812) 0x44cb88 B.EQ	44caec

      (812) 0x44cb8c LDR	X16, [X23, X1]

      (812) 0x44cb90 ADD	X11, X11, #1

      (812) 0x44cb94 ADD	X3, X3, #8

      (812) 0x44cb98 ADD	X14, X16, #1

      (812) 0x44cb9c STR	X14, [X23, X1]

      (812) 0x44cba0 STR	X0, [X20, X4,LSL #3]

      (812) 0x44cba4 LDR	X4, [X3]

      (812) 0x44cba8 TBZ	X4, #63, 44caf8

      (812) 0x44cbac ORN	X14, XZR, X4

      (812) 0x44cbb0 LDR	X4, [X20, X14,LSL #3]

      (812) 0x44cbb4 CMP	X0, X4

      (812) 0x44cbb8 B.EQ	44cb18

      (812) 0x44cbbc LDR	X12, [X23, X1]

      (812) 0x44cbc0 ADD	X11, X11, #1

      (812) 0x44cbc4 ADD	X17, X12, #1

      (812) 0x44cbc8 STR	X17, [X23, X1]

      (812) 0x44cbcc STR	X0, [X20, X14,LSL #3]

      (812) 0x44cbd0 LDR	X16, [X3, #8]

      (812) 0x44cbd4 TBZ	X16, #63, 44cb20

      (812) 0x44cbd8 ORN	X17, XZR, X16

      (812) 0x44cbdc LDR	X16, [X20, X17,LSL #3]

      (812) 0x44cbe0 CMP	X0, X16

      (812) 0x44cbe4 B.EQ	44cb40

      (812) 0x44cbe8 LDR	X14, [X23, X1]

      (812) 0x44cbec ADD	X11, X11, #1

      (812) 0x44cbf0 ADD	X4, X14, #1

      (812) 0x44cbf4 STR	X4, [X23, X1]

      (812) 0x44cbf8 STR	X0, [X20, X17,LSL #3]

      (812) 0x44cbfc LDR	X17, [X3, #16]

      (812) 0x44cc00 TBZ	X17, #63, 44cb48

      (812) 0x44cc04 ORN	X4, XZR, X17

      (812) 0x44cc08 LDR	X17, [X20, X4,LSL #3]

      (812) 0x44cc0c CMP	X0, X17

      (812) 0x44cc10 B.EQ	44cb68

      (812) 0x44cc14 LDR	X12, [X23, X1]

      (812) 0x44cc18 ADD	X11, X11, #1

      (812) 0x44cc1c ADD	X16, X12, #1

      (812) 0x44cc20 STR	X16, [X23, X1]

      (812) 0x44cc24 STR	X0, [X20, X4,LSL #3]

      (812) 0x44cc28 B	44cb68

    (811) 0x44cc2c ORN	X16, XZR, X14

    (811) 0x44cc30 LDR	X14, [X20, X16,LSL #3]

    (811) 0x44cc34 CMP	X0, X14

    (811) 0x44cc38 B.EQ	44c928

    (811) 0x44cc3c LDR	X12, [X23, X1]

    (811) 0x44cc40 ADD	X11, X11, #1

    (811) 0x44cc44 ADD	X4, X12, #1

    (811) 0x44cc48 STR	X4, [X23, X1]

    (811) 0x44cc4c STR	X0, [X20, X16,LSL #3]

    (811) 0x44cc50 B	44c928

    (811) 0x44cc54 ORN	X14, XZR, X4

    (811) 0x44cc58 LDR	X4, [X20, X14,LSL #3]

    (811) 0x44cc5c CMP	X0, X4

    (811) 0x44cc60 B.EQ	44c8fc

    (811) 0x44cc64 LDR	X17, [X23, X1]

    (811) 0x44cc68 ADD	X11, X11, #1

    (811) 0x44cc6c ADD	X16, X17, #1

    (811) 0x44cc70 STR	X16, [X23, X1]

    (811) 0x44cc74 STR	X0, [X20, X14,LSL #3]

    (811) 0x44cc78 B	44c8fc

    (811) 0x44cc7c ORN	X17, XZR, X16

    (811) 0x44cc80 LDR	X16, [X20, X17,LSL #3]

    (811) 0x44cc84 CMP	X0, X16

    (811) 0x44cc88 B.EQ	44c8d0

    (811) 0x44cc8c LDR	X12, [X23, X1]

    (811) 0x44cc90 ADD	X11, X11, #1

    (811) 0x44cc94 ADD	X14, X12, #1

    (811) 0x44cc98 STR	X14, [X23, X1]

    (811) 0x44cc9c STR	X0, [X20, X17,LSL #3]

    (811) 0x44cca0 B	44c8d0

(801) 0x44cca4 LDR	X17, [SP, #160]

(801) 0x44cca8 UBFM	X28, X4, #61, #60

(801) 0x44ccac STP	X12, X14, [SP, #136]

(801) 0x44ccb0 STP	X8, X9, [SP, #240]

(801) 0x44ccb4 STR	X10, [X17, X4,LSL #3]

(801) 0x44ccb8 LDR	X10, [SP, #168]

(801) 0x44ccbc STP	X6, X7, [SP, #256]

(801) 0x44ccc0 STR	X11, [X10, X4,LSL #3]

(801) 0x44ccc4 BL	40f590

(801) 0x44ccc8 BL	40f590

(801) 0x44cccc LDR	X11, [SP, #152]

(801) 0x44ccd0 LDP	X18, X5, [SP, #136]

(801) 0x44ccd4 LDP	X8, X9, [SP, #240]

(801) 0x44ccd8 LDP	X6, X7, [SP, #256]

(801) 0x44ccdc CMP	X11, #0

(801) 0x44cce0 B.LE	44ca14

(801) 0x44cce4 SUB	X28, X28, #8

(801) 0x44cce8 LDR	X3, [SP, #160]

(801) 0x44ccec LDR	X12, [SP, #168]

(801) 0x44ccf0 LDR	X16, [SP, #184]

(801) 0x44ccf4 ADD	X1, X3, X28

(801) 0x44ccf8 LDR	X0, [SP, #192]

(801) 0x44ccfc ADD	X2, X12, X28

(801) 0x44cd00 CMP	X0, X16

(801) 0x44cd04 B.LE	44ce98

(801) 0x44cd08 LDP	X15, X30, [SP, #104]

(801) 0x44cd0c LDR	X14, [SP, #200]

(801) 0x44cd10 LDR	X13, [X2]

(801) 0x44cd14 LDR	X4, [X15, X14,LSL #3]

(801) 0x44cd18 ORN	X17, XZR, X14

(801) 0x44cd1c ADD	X0, X14, #1

(801) 0x44cd20 ADD	X10, X17, X30

(801) 0x44cd24 AND	X16, X10, #4160

(801) 0x44cd28 UBFM	X11, X4, #61, #60

(801) 0x44cd2c ADD	X12, X9, X11

(801) 0x44cd30 ADD	X3, X8, X11

(801) 0x44cd34 LDR	X15, [X12]

(801) 0x44cd38 ADD	X13, X15, X13

(801) 0x44cd3c STR	X13, [X12]

(801) 0x44cd40 LDR	X14, [X1]

(801) 0x44cd44 LDR	X4, [X3]

(801) 0x44cd48 ADD	X17, X4, X14

(801) 0x44cd4c STR	X17, [X3]

(801) 0x44cd50 CMP	X30, X0

(801) 0x44cd54 B.LE	44ce98

(801) 0x44cd58 CBZ	X16, 44d5d8

(801) 0x44cd5c CMP	X16, #1

(801) 0x44cd60 B.EQ	44cda4

(801) 0x44cd64 CMP	X16, #2

(801) 0x44cd68 B.NE	44d59c

(801) 0x44cd6c LDR	X10, [SP, #104]

(801) 0x44cd70 LDR	X30, [X2]

(801) 0x44cd74 LDR	X16, [X10, X0,LSL #3]

(801) 0x44cd78 ADD	X0, X0, #1

(801) 0x44cd7c UBFM	X12, X16, #61, #60

(801) 0x44cd80 ADD	X11, X9, X12

(801) 0x44cd84 ADD	X3, X8, X12

(801) 0x44cd88 LDR	X15, [X11]

(801) 0x44cd8c ADD	X13, X15, X30

(801) 0x44cd90 STR	X13, [X11]

(801) 0x44cd94 LDR	X14, [X1]

(801) 0x44cd98 LDR	X4, [X3]

(801) 0x44cd9c ADD	X17, X4, X14

(801) 0x44cda0 STR	X17, [X3]

(801) 0x44cda4 LDR	X10, [SP, #104]

(801) 0x44cda8 LDR	X30, [X2]

(801) 0x44cdac LDR	X16, [X10, X0,LSL #3]

(801) 0x44cdb0 ADD	X0, X0, #1

(801) 0x44cdb4 UBFM	X12, X16, #61, #60

(801) 0x44cdb8 ADD	X11, X9, X12

(801) 0x44cdbc ADD	X3, X8, X12

(801) 0x44cdc0 LDR	X15, [X11]

(801) 0x44cdc4 ADD	X13, X15, X30

(801) 0x44cdc8 LDR	X30, [SP, #112]

(801) 0x44cdcc STR	X13, [X11]

(801) 0x44cdd0 LDR	X14, [X1]

(801) 0x44cdd4 LDR	X4, [X3]

(801) 0x44cdd8 ADD	X17, X4, X14

(801) 0x44cddc STR	X17, [X3]

(801) 0x44cde0 CMP	X30, X0

(801) 0x44cde4 B.LE	44ce98

(801) 0x44cde8 LDR	X10, [SP, #104]

(801) 0x44cdec ORR	X12, XZR, X30

  (808) 0x44cdf0 ADD	X15, X0, #1

  (808) 0x44cdf4 ADD	X13, X0, #3

  (808) 0x44cdf8 LDR	X3, [X10, X0,LSL #3]

  (808) 0x44cdfc ADD	X14, X15, #1

  (808) 0x44ce00 ADD	X0, X0, #4

  (808) 0x44ce04 LDR	X16, [X2]

  (808) 0x44ce08 LDR	X11, [X9, X3,LSL #3]

  (808) 0x44ce0c ADD	X4, X11, X16

  (808) 0x44ce10 STR	X4, [X9, X3,LSL #3]

  (808) 0x44ce14 LDR	X17, [X8, X3,LSL #3]

  (808) 0x44ce18 LDR	X30, [X1]

  (808) 0x44ce1c ADD	X11, X17, X30

  (808) 0x44ce20 STR	X11, [X8, X3,LSL #3]

  (808) 0x44ce24 LDR	X3, [X10, X15,LSL #3]

  (808) 0x44ce28 LDR	X15, [X2]

  (808) 0x44ce2c LDR	X16, [X9, X3,LSL #3]

  (808) 0x44ce30 ADD	X4, X16, X15

  (808) 0x44ce34 STR	X4, [X9, X3,LSL #3]

  (808) 0x44ce38 LDR	X17, [X8, X3,LSL #3]

  (808) 0x44ce3c LDR	X30, [X1]

  (808) 0x44ce40 ADD	X11, X17, X30

  (808) 0x44ce44 STR	X11, [X8, X3,LSL #3]

  (808) 0x44ce48 LDR	X3, [X10, X14,LSL #3]

  (808) 0x44ce4c LDR	X14, [X2]

  (808) 0x44ce50 LDR	X16, [X9, X3,LSL #3]

  (808) 0x44ce54 ADD	X15, X16, X14

  (808) 0x44ce58 STR	X15, [X9, X3,LSL #3]

  (808) 0x44ce5c LDR	X4, [X8, X3,LSL #3]

  (808) 0x44ce60 LDR	X17, [X1]

  (808) 0x44ce64 ADD	X30, X4, X17

  (808) 0x44ce68 STR	X30, [X8, X3,LSL #3]

  (808) 0x44ce6c LDR	X3, [X10, X13,LSL #3]

  (808) 0x44ce70 LDR	X13, [X2]

  (808) 0x44ce74 LDR	X11, [X9, X3,LSL #3]

  (808) 0x44ce78 ADD	X16, X11, X13

  (808) 0x44ce7c STR	X16, [X9, X3,LSL #3]

  (808) 0x44ce80 LDR	X14, [X8, X3,LSL #3]

  (808) 0x44ce84 LDR	X15, [X1]

  (808) 0x44ce88 ADD	X4, X14, X15

  (808) 0x44ce8c STR	X4, [X8, X3,LSL #3]

  (808) 0x44ce90 CMP	X12, X0

  (808) 0x44ce94 B.GT	44cdf0

(801) 0x44ce98 STP	X18, X5, [SP, #136]

(801) 0x44ce9c STR	X8, [SP, #152]

(801) 0x44cea0 STR	X9, [SP, #224]

(801) 0x44cea4 STP	X6, X7, [SP, #240]

(801) 0x44cea8 BL	40f590

(801) 0x44ceac LDR	X2, [SP, #160]

(801) 0x44ceb0 LDP	X4, X5, [SP, #136]

(801) 0x44ceb4 LDP	X6, X7, [SP, #240]

(801) 0x44ceb8 LDR	X18, [SP, #168]

(801) 0x44cebc LDR	X1, [X2, X28]

(801) 0x44cec0 LDR	X15, [SP, #152]

(801) 0x44cec4 LDR	X3, [X18, X28]

(801) 0x44cec8 LDR	X9, [SP, #224]

(801) 0x44cecc LDP	X0, X12, [SP, #176]

(801) 0x44ced0 ADD	X8, X5, X22

(801) 0x44ced4 ADD	X28, X4, X22

(801) 0x44ced8 STR	X8, [SP, #144]

(801) 0x44cedc LDR	X10, [SP, #192]

(801) 0x44cee0 STR	X28, [SP, #152]

(801) 0x44cee4 SUB	X13, X0, #1

(801) 0x44cee8 CMP	X10, X12

(801) 0x44ceec B.LE	44d338

(801) 0x44cef0 LDR	X18, [SP, #200]

(801) 0x44cef4 STR	X15, [SP, #136]

(801) 0x44cef8 HINT	#0

(801) 0x44cefc HINT	#0

  (802) 0x44cf00 LDR	X17, [SP, #104]

  (802) 0x44cf04 LDR	X10, [X17, X18,LSL #3]

  (802) 0x44cf08 UBFM	X30, X10, #61, #60

  (802) 0x44cf0c LDR	X2, [X7, X10,LSL #3]

  (802) 0x44cf10 ORN	X0, XZR, X10

  (802) 0x44cf14 ADD	X16, X30, #8

  (802) 0x44cf18 LDR	X28, [X7, X16]

  (802) 0x44cf1c ADD	X30, X7, X16

  (802) 0x44cf20 CMP	X28, X2

  (802) 0x44cf24 B.GT	44cf38

  (802) 0x44cf28 B	44d204

    (805) 0x44cf2c ADD	X2, X2, #1

    (805) 0x44cf30 CMP	X2, X28

    (805) 0x44cf34 B.GE	44d204

    (805) 0x44cf38 LDR	X8, [X27, X2,LSL #3]

    (805) 0x44cf3c LDR	X11, [X25, X8,LSL #3]

    (805) 0x44cf40 UBFM	X15, X8, #61, #60

    (805) 0x44cf44 CMP	X11, X13

    (805) 0x44cf48 B.NE	44cf2c

    (805) 0x44cf4c ADD	X12, X15, #8

    (805) 0x44cf50 LDR	X17, [X9, X8,LSL #3]

    (805) 0x44cf54 LDR	X14, [X23, X12]

    (805) 0x44cf58 ADD	X15, X17, X14

    (805) 0x44cf5c CMP	X17, X15

    (805) 0x44cf60 B.GE	44d0a0

    (805) 0x44cf64 LDR	X28, [SP, #144]

    (805) 0x44cf68 LDUR	X28, [X28, #504]

    (805) 0x44cf6c ADD	X15, X28, X15,LSL #3

    (805) 0x44cf70 ADD	X11, X28, X17,LSL #3

    (805) 0x44cf74 SUB	X14, X15, X11

    (805) 0x44cf78 SUB	X14, X14, #8

    (805) 0x44cf7c UBFM	X14, X14, #3, #63

    (805) 0x44cf80 ADD	X14, X14, #1

    (805) 0x44cf84 ANDS	X14, X14, #4160

    (805) 0x44cf88 B.EQ	44d010

    (805) 0x44cf8c CMP	X14, #1

    (805) 0x44cf90 B.EQ	44cfe4

    (805) 0x44cf94 CMP	X14, #2

    (805) 0x44cf98 B.EQ	44cfc0

    (805) 0x44cf9c LDR	X28, [X28, X17,LSL #3]

    (805) 0x44cfa0 LDR	X17, [X20, X28,LSL #3]

    (805) 0x44cfa4 CMP	X17, X0

    (805) 0x44cfa8 B.EQ	44cfbc

    (805) 0x44cfac LDR	X14, [X5, X22]

    (805) 0x44cfb0 STR	X28, [X14, X3,LSL #3]

    (805) 0x44cfb4 ADD	X3, X3, #1

    (805) 0x44cfb8 STR	X0, [X20, X28,LSL #3]

    (805) 0x44cfbc ADD	X11, X11, #8

    (805) 0x44cfc0 LDR	X28, [X11]

    (805) 0x44cfc4 LDR	X17, [X20, X28,LSL #3]

    (805) 0x44cfc8 CMP	X17, X0

    (805) 0x44cfcc B.EQ	44cfe0

    (805) 0x44cfd0 LDR	X14, [X5, X22]

    (805) 0x44cfd4 STR	X28, [X14, X3,LSL #3]

    (805) 0x44cfd8 ADD	X3, X3, #1

    (805) 0x44cfdc STR	X0, [X20, X28,LSL #3]

    (805) 0x44cfe0 ADD	X11, X11, #8

    (805) 0x44cfe4 LDR	X28, [X11]

    (805) 0x44cfe8 LDR	X17, [X20, X28,LSL #3]

    (805) 0x44cfec CMP	X17, X0

    (805) 0x44cff0 B.EQ	44d004

    (805) 0x44cff4 LDR	X14, [X5, X22]

    (805) 0x44cff8 STR	X28, [X14, X3,LSL #3]

    (805) 0x44cffc ADD	X3, X3, #1

    (805) 0x44d000 STR	X0, [X20, X28,LSL #3]

    (805) 0x44d004 ADD	X11, X11, #8

    (805) 0x44d008 CMP	X15, X11

    (805) 0x44d00c B.EQ	44d0a0

      (807) 0x44d010 LDR	X28, [X11]

      (807) 0x44d014 LDR	X17, [X20, X28,LSL #3]

      (807) 0x44d018 CMP	X17, X0

      (807) 0x44d01c B.EQ	44d030

      (807) 0x44d020 LDR	X14, [X5, X22]

      (807) 0x44d024 STR	X28, [X14, X3,LSL #3]

      (807) 0x44d028 ADD	X3, X3, #1

      (807) 0x44d02c STR	X0, [X20, X28,LSL #3]

      (807) 0x44d030 LDR	X28, [X11, #8]

      (807) 0x44d034 ADD	X14, X11, #8

      (807) 0x44d038 LDR	X11, [X20, X28,LSL #3]

      (807) 0x44d03c CMP	X11, X0

      (807) 0x44d040 B.EQ	44d054

      (807) 0x44d044 LDR	X17, [X5, X22]

      (807) 0x44d048 STR	X28, [X17, X3,LSL #3]

      (807) 0x44d04c ADD	X3, X3, #1

      (807) 0x44d050 STR	X0, [X20, X28,LSL #3]

      (807) 0x44d054 LDR	X17, [X14, #8]

      (807) 0x44d058 ADD	X11, X14, #24

      (807) 0x44d05c LDR	X28, [X20, X17,LSL #3]

      (807) 0x44d060 CMP	X28, X0

      (807) 0x44d064 B.EQ	44d078

      (807) 0x44d068 LDR	X28, [X5, X22]

      (807) 0x44d06c STR	X17, [X28, X3,LSL #3]

      (807) 0x44d070 ADD	X3, X3, #1

      (807) 0x44d074 STR	X0, [X20, X17,LSL #3]

      (807) 0x44d078 LDR	X14, [X14, #16]

      (807) 0x44d07c LDR	X17, [X20, X14,LSL #3]

      (807) 0x44d080 CMP	X17, X0

      (807) 0x44d084 B.EQ	44d098

      (807) 0x44d088 LDR	X28, [X5, X22]

      (807) 0x44d08c STR	X14, [X28, X3,LSL #3]

      (807) 0x44d090 ADD	X3, X3, #1

      (807) 0x44d094 STR	X0, [X20, X14,LSL #3]

      (807) 0x44d098 CMP	X15, X11

      (807) 0x44d09c B.NE	44d010

    (805) 0x44d0a0 LDR	X15, [SP, #136]

    (805) 0x44d0a4 LDR	X12, [X21, X12]

    (805) 0x44d0a8 LDR	X14, [X15, X8,LSL #3]

    (805) 0x44d0ac ADD	X11, X14, X12

    (805) 0x44d0b0 CMP	X14, X11

    (805) 0x44d0b4 B.GE	44d1f4

    (805) 0x44d0b8 LDR	X8, [SP, #152]

    (805) 0x44d0bc LDUR	X17, [X8, #504]

    (805) 0x44d0c0 ADD	X28, X17, X11,LSL #3

    (805) 0x44d0c4 ADD	X8, X17, X14,LSL #3

    (805) 0x44d0c8 SUB	X12, X28, X8

    (805) 0x44d0cc SUB	X15, X12, #8

    (805) 0x44d0d0 UBFM	X11, X15, #3, #63

    (805) 0x44d0d4 ADD	X12, X11, #1

    (805) 0x44d0d8 ANDS	X15, X12, #4160

    (805) 0x44d0dc B.EQ	44d164

    (805) 0x44d0e0 CMP	X15, #1

    (805) 0x44d0e4 B.EQ	44d138

    (805) 0x44d0e8 CMP	X15, #2

    (805) 0x44d0ec B.EQ	44d114

    (805) 0x44d0f0 LDR	X17, [X17, X14,LSL #3]

    (805) 0x44d0f4 LDR	X14, [X19, X17,LSL #3]

    (805) 0x44d0f8 CMP	X14, X0

    (805) 0x44d0fc B.EQ	44d110

    (805) 0x44d100 LDR	X11, [X4, X22]

    (805) 0x44d104 STR	X17, [X11, X1,LSL #3]

    (805) 0x44d108 ADD	X1, X1, #1

    (805) 0x44d10c STR	X0, [X19, X17,LSL #3]

    (805) 0x44d110 ADD	X8, X8, #8

    (805) 0x44d114 LDR	X12, [X8]

    (805) 0x44d118 LDR	X15, [X19, X12,LSL #3]

    (805) 0x44d11c CMP	X15, X0

    (805) 0x44d120 B.EQ	44d134

    (805) 0x44d124 LDR	X17, [X4, X22]

    (805) 0x44d128 STR	X12, [X17, X1,LSL #3]

    (805) 0x44d12c ADD	X1, X1, #1

    (805) 0x44d130 STR	X0, [X19, X12,LSL #3]

    (805) 0x44d134 ADD	X8, X8, #8

    (805) 0x44d138 LDR	X11, [X8]

    (805) 0x44d13c LDR	X14, [X19, X11,LSL #3]

    (805) 0x44d140 CMP	X14, X0

    (805) 0x44d144 B.EQ	44d158

    (805) 0x44d148 LDR	X12, [X4, X22]

    (805) 0x44d14c STR	X11, [X12, X1,LSL #3]

    (805) 0x44d150 ADD	X1, X1, #1

    (805) 0x44d154 STR	X0, [X19, X11,LSL #3]

    (805) 0x44d158 ADD	X8, X8, #8

    (805) 0x44d15c CMP	X8, X28

    (805) 0x44d160 B.EQ	44d1f4

      (806) 0x44d164 LDR	X15, [X8]

      (806) 0x44d168 LDR	X17, [X19, X15,LSL #3]

      (806) 0x44d16c CMP	X17, X0

      (806) 0x44d170 B.EQ	44d184

      (806) 0x44d174 LDR	X11, [X4, X22]

      (806) 0x44d178 STR	X15, [X11, X1,LSL #3]

      (806) 0x44d17c ADD	X1, X1, #1

      (806) 0x44d180 STR	X0, [X19, X15,LSL #3]

      (806) 0x44d184 LDR	X14, [X8, #8]

      (806) 0x44d188 ADD	X12, X8, #8

      (806) 0x44d18c LDR	X8, [X19, X14,LSL #3]

      (806) 0x44d190 CMP	X8, X0

      (806) 0x44d194 B.EQ	44d1a8

      (806) 0x44d198 LDR	X15, [X4, X22]

      (806) 0x44d19c STR	X14, [X15, X1,LSL #3]

      (806) 0x44d1a0 ADD	X1, X1, #1

      (806) 0x44d1a4 STR	X0, [X19, X14,LSL #3]

      (806) 0x44d1a8 LDR	X17, [X12, #8]

      (806) 0x44d1ac ADD	X8, X12, #24

      (806) 0x44d1b0 LDR	X11, [X19, X17,LSL #3]

      (806) 0x44d1b4 CMP	X11, X0

      (806) 0x44d1b8 B.EQ	44d1cc

      (806) 0x44d1bc LDR	X14, [X4, X22]

      (806) 0x44d1c0 STR	X17, [X14, X1,LSL #3]

      (806) 0x44d1c4 ADD	X1, X1, #1

      (806) 0x44d1c8 STR	X0, [X19, X17,LSL #3]

      (806) 0x44d1cc LDR	X12, [X12, #16]

      (806) 0x44d1d0 LDR	X15, [X19, X12,LSL #3]

      (806) 0x44d1d4 CMP	X15, X0

      (806) 0x44d1d8 B.EQ	44d1ec

      (806) 0x44d1dc LDR	X17, [X4, X22]

      (806) 0x44d1e0 STR	X12, [X17, X1,LSL #3]

      (806) 0x44d1e4 ADD	X1, X1, #1

      (806) 0x44d1e8 STR	X0, [X19, X12,LSL #3]

      (806) 0x44d1ec CMP	X8, X28

      (806) 0x44d1f0 B.NE	44d164

    (805) 0x44d1f4 LDR	X28, [X30]

    (805) 0x44d1f8 ADD	X2, X2, #1

    (805) 0x44d1fc CMP	X2, X28

    (805) 0x44d200 B.LT	44cf38

  (802) 0x44d204 LDR	X0, [X6, X10,LSL #3]

  (802) 0x44d208 ADD	X14, X6, X16

  (802) 0x44d20c ORN	X10, XZR, X10

  (802) 0x44d210 LDR	X15, [X6, X16]

  (802) 0x44d214 CMP	X15, X0

  (802) 0x44d218 B.GT	44d22c

  (802) 0x44d21c B	44d328

    (803) 0x44d220 ADD	X0, X0, #1

    (803) 0x44d224 CMP	X0, X15

    (803) 0x44d228 B.GE	44d328

    (803) 0x44d22c LDR	X16, [X26, X0,LSL #3]

    (803) 0x44d230 LDR	X30, [X24, X16,LSL #3]

    (803) 0x44d234 UBFM	X11, X16, #61, #60

    (803) 0x44d238 CMP	X30, X13

    (803) 0x44d23c B.NE	44d220

    (803) 0x44d240 LDR	X8, [SP, #120]

    (803) 0x44d244 LDR	X28, [SP, #128]

    (803) 0x44d248 ADD	X12, X8, X11

    (803) 0x44d24c LDR	X17, [X12, #8]

    (803) 0x44d250 LDR	X16, [X28, X16,LSL #3]

    (803) 0x44d254 ADD	X30, X16, X17

    (803) 0x44d258 CMP	X16, X30

    (803) 0x44d25c B.GE	44d220

    (803) 0x44d260 LDR	X15, [SP, #96]

    (803) 0x44d264 LDR	X12, [X15, X22]

    (803) 0x44d268 ADD	X11, X12, X30,LSL #3

    (803) 0x44d26c ADD	X2, X12, X16,LSL #3

    (803) 0x44d270 SUB	X8, X11, X2

    (803) 0x44d274 SUB	X17, X8, #8

    (803) 0x44d278 UBFM	X28, X17, #3, #63

    (803) 0x44d27c ADD	X30, X28, #1

    (803) 0x44d280 ANDS	X15, X30, #4160

    (803) 0x44d284 B.EQ	44d3e8

    (803) 0x44d288 CMP	X15, #1

    (803) 0x44d28c B.EQ	44d2e8

    (803) 0x44d290 CMP	X15, #2

    (803) 0x44d294 B.EQ	44d2c0

    (803) 0x44d298 LDR	X16, [X12, X16,LSL #3]

    (803) 0x44d29c TBNZ	X16, #63, 44d4f8

    (803) 0x44d2a0 LDR	X12, [X19, X16,LSL #3]

    (803) 0x44d2a4 CMP	X12, X10

    (803) 0x44d2a8 B.EQ	44d2bc

    (803) 0x44d2ac LDR	X8, [X4, X22]

    (803) 0x44d2b0 STR	X16, [X8, X1,LSL #3]

    (803) 0x44d2b4 ADD	X1, X1, #1

    (803) 0x44d2b8 STR	X10, [X19, X16,LSL #3]

    (803) 0x44d2bc ADD	X2, X2, #8

    (803) 0x44d2c0 LDR	X16, [X2]

    (803) 0x44d2c4 TBNZ	X16, #63, 44d4d4

    (803) 0x44d2c8 LDR	X12, [X19, X16,LSL #3]

    (803) 0x44d2cc CMP	X12, X10

    (803) 0x44d2d0 B.EQ	44d2e4

    (803) 0x44d2d4 LDR	X8, [X4, X22]

    (803) 0x44d2d8 STR	X16, [X8, X1,LSL #3]

    (803) 0x44d2dc ADD	X1, X1, #1

    (803) 0x44d2e0 STR	X10, [X19, X16,LSL #3]

    (803) 0x44d2e4 ADD	X2, X2, #8

    (803) 0x44d2e8 LDR	X16, [X2]

    (803) 0x44d2ec TBNZ	X16, #63, 44d4b0

    (803) 0x44d2f0 LDR	X12, [X19, X16,LSL #3]

    (803) 0x44d2f4 CMP	X12, X10

    (803) 0x44d2f8 B.EQ	44d30c

    (803) 0x44d2fc LDR	X8, [X4, X22]

    (803) 0x44d300 STR	X16, [X8, X1,LSL #3]

    (803) 0x44d304 ADD	X1, X1, #1

    (803) 0x44d308 STR	X10, [X19, X16,LSL #3]

    (803) 0x44d30c ADD	X2, X2, #8

    (803) 0x44d310 CMP	X11, X2

    (803) 0x44d314 B.NE	44d3e8

    (803) 0x44d318 LDR	X15, [X14]

    (803) 0x44d31c ADD	X0, X0, #1

    (803) 0x44d320 CMP	X0, X15

    (803) 0x44d324 B.LT	44d22c

  (802) 0x44d328 LDR	X11, [SP, #112]

  (802) 0x44d32c ADD	X18, X18, #1

  (802) 0x44d330 CMP	X11, X18

  (802) 0x44d334 B.GT	44cf00

(801) 0x44d338 ORR	X0, XZR, X20

(801) 0x44d33c BL	516820

(801) 0x44d340 LDR	X27, [SP, #216]

(801) 0x44d344 LDR	X23, [SP, #208]

(801) 0x44d348 LDR	X26, [SP, #232]

(801) 0x44d34c CMP	X27, #0

(801) 0x44d350 CCMP	X23, X26, #4, #0

(801) 0x44d354 B.NE	44d51c

0x44d358 ORR	X0, XZR, X19

0x44d35c LDP	X19, X20, [SP, #16]

0x44d360 LDP	X21, X22, [SP, #32]

0x44d364 LDP	X23, X24, [SP, #48]

0x44d368 LDP	X25, X26, [SP, #64]

0x44d36c LDP	X27, X28, [SP, #80]

0x44d370 LDP	X29, X30, [SP], #288

0x44d374 B	516820

      (804) 0x44d378 LDR	X12, [X19, X16,LSL #3]

      (804) 0x44d37c CMP	X12, X10

      (804) 0x44d380 B.EQ	44d394

      (804) 0x44d384 LDR	X8, [X4, X22]

      (804) 0x44d388 STR	X16, [X8, X1,LSL #3]

      (804) 0x44d38c ADD	X1, X1, #1

      (804) 0x44d390 STR	X10, [X19, X16,LSL #3]

      (804) 0x44d394 LDR	X16, [X2, #8]

      (804) 0x44d398 TBNZ	X16, #63, 44d440

      (804) 0x44d39c LDR	X12, [X19, X16,LSL #3]

      (804) 0x44d3a0 CMP	X12, X10

      (804) 0x44d3a4 B.EQ	44d3b8

      (804) 0x44d3a8 LDR	X8, [X4, X22]

      (804) 0x44d3ac STR	X16, [X8, X1,LSL #3]

      (804) 0x44d3b0 ADD	X1, X1, #1

      (804) 0x44d3b4 STR	X10, [X19, X16,LSL #3]

      (804) 0x44d3b8 LDR	X16, [X2, #16]

      (804) 0x44d3bc TBNZ	X16, #63, 44d468

      (804) 0x44d3c0 LDR	X12, [X19, X16,LSL #3]

      (804) 0x44d3c4 CMP	X12, X10

      (804) 0x44d3c8 B.EQ	44d3dc

      (804) 0x44d3cc LDR	X8, [X4, X22]

      (804) 0x44d3d0 STR	X16, [X8, X1,LSL #3]

      (804) 0x44d3d4 ADD	X1, X1, #1

      (804) 0x44d3d8 STR	X10, [X19, X16,LSL #3]

      (804) 0x44d3dc ADD	X2, X2, #24

      (804) 0x44d3e0 CMP	X11, X2

      (804) 0x44d3e4 B.EQ	44d318

      (804) 0x44d3e8 LDR	X16, [X2]

      (804) 0x44d3ec TBNZ	X16, #63, 44d48c

      (804) 0x44d3f0 LDR	X12, [X19, X16,LSL #3]

      (804) 0x44d3f4 CMP	X12, X10

      (804) 0x44d3f8 B.EQ	44d40c

      (804) 0x44d3fc LDR	X8, [X4, X22]

      (804) 0x44d400 STR	X16, [X8, X1,LSL #3]

      (804) 0x44d404 ADD	X1, X1, #1

      (804) 0x44d408 STR	X10, [X19, X16,LSL #3]

      (804) 0x44d40c LDR	X16, [X2, #8]

      (804) 0x44d410 ADD	X2, X2, #8

      (804) 0x44d414 TBZ	X16, #63, 44d378

      (804) 0x44d418 ORN	X17, XZR, X16

      (804) 0x44d41c LDR	X28, [X20, X17,LSL #3]

      (804) 0x44d420 CMP	X28, X10

      (804) 0x44d424 B.EQ	44d394

      (804) 0x44d428 LDR	X30, [X5, X22]

      (804) 0x44d42c STR	X17, [X30, X3,LSL #3]

      (804) 0x44d430 ADD	X3, X3, #1

      (804) 0x44d434 STR	X10, [X20, X17,LSL #3]

      (804) 0x44d438 LDR	X16, [X2, #8]

      (804) 0x44d43c TBZ	X16, #63, 44d39c

      (804) 0x44d440 ORN	X17, XZR, X16

      (804) 0x44d444 LDR	X28, [X20, X17,LSL #3]

      (804) 0x44d448 CMP	X28, X10

      (804) 0x44d44c B.EQ	44d3b8

      (804) 0x44d450 LDR	X30, [X5, X22]

      (804) 0x44d454 STR	X17, [X30, X3,LSL #3]

      (804) 0x44d458 ADD	X3, X3, #1

      (804) 0x44d45c STR	X10, [X20, X17,LSL #3]

      (804) 0x44d460 LDR	X16, [X2, #16]

      (804) 0x44d464 TBZ	X16, #63, 44d3c0

      (804) 0x44d468 ORN	X17, XZR, X16

      (804) 0x44d46c LDR	X28, [X20, X17,LSL #3]

      (804) 0x44d470 CMP	X28, X10

      (804) 0x44d474 B.EQ	44d3dc

      (804) 0x44d478 LDR	X30, [X5, X22]

      (804) 0x44d47c STR	X17, [X30, X3,LSL #3]

      (804) 0x44d480 ADD	X3, X3, #1

      (804) 0x44d484 STR	X10, [X20, X17,LSL #3]

      (804) 0x44d488 B	44d3dc

      (804) 0x44d48c ORN	X17, XZR, X16

      (804) 0x44d490 LDR	X28, [X20, X17,LSL #3]

      (804) 0x44d494 CMP	X28, X10

      (804) 0x44d498 B.EQ	44d40c

      (804) 0x44d49c LDR	X30, [X5, X22]

      (804) 0x44d4a0 STR	X17, [X30, X3,LSL #3]

      (804) 0x44d4a4 ADD	X3, X3, #1

      (804) 0x44d4a8 STR	X10, [X20, X17,LSL #3]

      (804) 0x44d4ac B	44d40c

    (803) 0x44d4b0 ORN	X17, XZR, X16

    (803) 0x44d4b4 LDR	X28, [X20, X17,LSL #3]

    (803) 0x44d4b8 CMP	X28, X10

    (803) 0x44d4bc B.EQ	44d30c

    (803) 0x44d4c0 LDR	X30, [X5, X22]

    (803) 0x44d4c4 STR	X17, [X30, X3,LSL #3]

    (803) 0x44d4c8 ADD	X3, X3, #1

    (803) 0x44d4cc STR	X10, [X20, X17,LSL #3]

    (803) 0x44d4d0 B	44d30c

    (803) 0x44d4d4 ORN	X17, XZR, X16

    (803) 0x44d4d8 LDR	X28, [X20, X17,LSL #3]

    (803) 0x44d4dc CMP	X28, X10

    (803) 0x44d4e0 B.EQ	44d2e4

    (803) 0x44d4e4 LDR	X30, [X5, X22]

    (803) 0x44d4e8 STR	X17, [X30, X3,LSL #3]

    (803) 0x44d4ec ADD	X3, X3, #1

    (803) 0x44d4f0 STR	X10, [X20, X17,LSL #3]

    (803) 0x44d4f4 B	44d2e4

    (803) 0x44d4f8 ORN	X17, XZR, X16

    (803) 0x44d4fc LDR	X28, [X20, X17,LSL #3]

    (803) 0x44d500 CMP	X28, X10

    (803) 0x44d504 B.EQ	44d2bc

    (803) 0x44d508 LDR	X30, [X5, X22]

    (803) 0x44d50c STR	X17, [X30, X3,LSL #3]

    (803) 0x44d510 ADD	X3, X3, #1

    (803) 0x44d514 STR	X10, [X20, X17,LSL #3]

    (803) 0x44d518 B	44d2bc

(801) 0x44d51c LDP	X19, X20, [SP, #16]

(801) 0x44d520 LDP	X21, X22, [SP, #32]

(801) 0x44d524 LDP	X23, X24, [SP, #48]

(801) 0x44d528 LDP	X25, X26, [SP, #64]

(801) 0x44d52c LDP	X27, X28, [SP, #80]

(801) 0x44d530 LDP	X29, X30, [SP], #288

(801) 0x44d534 RET

(801) 0x44d538 MOVZ	X1, #8

(801) 0x44d53c ORR	X28, XZR, X0

(801) 0x44d540 STP	X12, X14, [SP, #136]

(801) 0x44d544 STP	X8, X9, [SP, #240]

(801) 0x44d548 STP	X6, X7, [SP, #256]

(801) 0x44d54c BL	51674c

(801) 0x44d550 CMP	X28, #0

(801) 0x44d554 ORR	X19, XZR, X0

(801) 0x44d558 LDP	X12, X14, [SP, #136]

(801) 0x44d55c LDP	X8, X9, [SP, #240]

(801) 0x44d560 LDP	X6, X7, [SP, #256]

(801) 0x44d564 B.LE	44c4ac

(801) 0x44d568 UBFM	X2, X28, #61, #60

(801) 0x44d56c MOVZ	W1, #255

(801) 0x44d570 BL	40f370

(801) 0x44d574 LDP	X12, X14, [SP, #136]

(801) 0x44d578 LDP	X8, X9, [SP, #240]

(801) 0x44d57c LDP	X6, X7, [SP, #256]

(801) 0x44d580 B	44c4ac

0x44d584 MOVZ	X1, #8

0x44d588 ORR	X0, XZR, X28

0x44d58c STP	X12, X14, [SP, #136]

0x44d590 STP	X8, X9, [SP, #240]

0x44d594 STP	X6, X7, [SP, #256]

0x44d598 B	44d54c

(801) 0x44d59c LDR	X10, [SP, #104]

(801) 0x44d5a0 LDR	X30, [X2]

(801) 0x44d5a4 LDR	X16, [X10, X0,LSL #3]

(801) 0x44d5a8 ADD	X0, X0, #1

(801) 0x44d5ac UBFM	X12, X16, #61, #60

(801) 0x44d5b0 ADD	X11, X9, X12

(801) 0x44d5b4 ADD	X3, X8, X12

(801) 0x44d5b8 LDR	X15, [X11]

(801) 0x44d5bc ADD	X13, X15, X30

(801) 0x44d5c0 STR	X13, [X11]

(801) 0x44d5c4 LDR	X14, [X1]

(801) 0x44d5c8 LDR	X4, [X3]

(801) 0x44d5cc ADD	X17, X4, X14

(801) 0x44d5d0 STR	X17, [X3]

(801) 0x44d5d4 B	44cd6c

(801) 0x44d5d8 ORR	X12, XZR, X30

(801) 0x44d5dc LDR	X10, [SP, #104]

(801) 0x44d5e0 B	44cdf0

(801) 0x44d5e4 MOVZ	X1, #8

(801) 0x44d5e8 ORR	X0, XZR, X28

(801) 0x44d5ec STP	X11, X18, [SP, #136]

(801) 0x44d5f0 STP	X2, X5, [SP, #152]

(801) 0x44d5f4 STR	X13, [SP, #168]

(801) 0x44d5f8 STR	X14, [SP, #224]

(801) 0x44d5fc BL	51674c

(801) 0x44d600 LDP	X11, X18, [SP, #136]

(801) 0x44d604 LDP	X13, X1, [SP, #168]

(801) 0x44d608 LDP	X2, X5, [SP, #152]

(801) 0x44d60c STR	X0, [X11, X1,LSL #3]

(801) 0x44d610 LDR	X14, [SP, #224]

(801) 0x44d614 B	44ca9c

0x44d618 HINT	#0

0x44d61c HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	par_multi_interp.c:891-1134
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:891,900-927,939-970,976-999,1008-1034,1040-1055,1062-1125,1132-1134.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 24.83 to 10.00 cycles (2.48x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 24.83 to 2.00 cycles (12.42x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 456 bytes. The binary function is storing 400 bytes.

General properties

nb instructions	107
loop length	428
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	6.75	6.75	6.75	6.75	0.00	0.00	0.00	0.00	24.83	24.50	24.67	17.50	17.50
cycles	4.50	4.50	6.75	6.75	6.75	6.75	0.00	0.00	0.00	0.00	24.83	24.50	24.67	17.50	17.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	13.13
Overall L1	24.83

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 24.83 cycles. At this rate:

19% of peak load performance is reached (18.36 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.11 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 44c340

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #736]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X7, X27, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X6, X26, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X9, X8, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X1, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X2, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X2, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X1, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X9, X6, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X3, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X7, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X0, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X23, X21, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X20, [X0, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X5, X4, [X0, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X11, [X0, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X24, [X0, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X11, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X0, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X5, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [X0, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X0, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X0, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X13, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X0, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X22, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X15, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X0, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X17, X0, [X0, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X12, X4, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X0, X17, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X14, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X16, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 519580 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 519560 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X18, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X6, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X0, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X7, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV X3, X20, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
LDR X1, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X18, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MADD X2, X8, X3, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X4, X2, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X3, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X20, X5, X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X20, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X2, X20, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X10, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 51674c <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X28, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X14, X8, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X9, X6, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X7, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.LE 44c48c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x14c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X2, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #255	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X12, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X14, X8, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X9, X6, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X7, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f370 <@plt_start@+0x180>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X12, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X14, X8, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X9, X6, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X7, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X11, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X28, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 44d584 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1244>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X0, 44d538 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x11f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #288	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 516820 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X12, X14, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X8, X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X6, X7, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 44d54c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x120c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Source file and lines	par_multi_interp.c:891-1134
Module	exec

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 24.83 to 2.00 cycles (12.42x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 456 bytes. The binary function is storing 400 bytes.

General properties

nb instructions	107
loop length	428
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	6.75	6.75	6.75	6.75	0.00	0.00	0.00	0.00	24.83	24.50	24.67	17.50	17.50
cycles	4.50	4.50	6.75	6.75	6.75	6.75	0.00	0.00	0.00	0.00	24.83	24.50	24.67	17.50	17.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	13.13
Overall L1	24.83

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 24.83 cycles. At this rate:

19% of peak load performance is reached (18.36 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.11 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 44c340

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #736]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X7, X27, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X6, X26, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X9, X8, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X1, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X2, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X2, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X1, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X9, X6, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X3, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X7, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X0, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X23, X21, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X20, [X0, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X5, X4, [X0, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X11, [X0, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X24, [X0, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X11, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X0, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X5, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [X0, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X0, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X0, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X13, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X0, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X22, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X15, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [X0, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X17, X0, [X0, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X12, X4, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X0, X17, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X14, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X16, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 519580 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 519560 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X18, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X6, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X0, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X7, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV X3, X20, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
LDR X1, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X18, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MADD X2, X8, X3, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X4, X2, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X3, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X20, X5, X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X20, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X2, X20, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X10, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 51674c <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X28, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X14, X8, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X9, X6, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X7, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.LE 44c48c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x14c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X2, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #255	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X12, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X14, X8, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X9, X6, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X7, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f370 <@plt_start@+0x180>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X12, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X14, X8, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X9, X6, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X7, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X11, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X28, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 44d584 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x1244>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X0, 44d538 <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x11f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #288	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 516820 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X12, X14, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X8, X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X6, X7, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 44d54c <hypre_BoomerAMGBuildMultipass._omp_fn.5+0x120c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGBuildMultipass._omp_fn.5–	1.09	0.41
▼Loop 801 - par_multi_interp.c:891-1133 - exec–	0	0
▼Loop 810 - par_multi_interp.c:939-999 - exec–	0.05	0.02
▼Loop 813 - par_multi_interp.c:944-970 - exec–	0.49	0.16
○Loop 815 - par_multi_interp.c:951-958 - exec	0	0
○Loop 814 - par_multi_interp.c:963-970 - exec	0	0
▼Loop 811 - par_multi_interp.c:976-999 - exec–	0	0
○Loop 812 - par_multi_interp.c:983-999 - exec	0	0
▼Loop 802 - par_multi_interp.c:1072-1125 - exec–	0.03	0.01
▼Loop 805 - par_multi_interp.c:1075-1099 - exec–	0.49	0.16
○Loop 807 - par_multi_interp.c:1082-1088 - exec	0	0.01
○Loop 806 - par_multi_interp.c:1093-1099 - exec	0	0
▼Loop 803 - par_multi_interp.c:1104-1125 - exec–	0	0
○Loop 804 - par_multi_interp.c:1111-1125 - exec	0	0
○Loop 808 - par_multi_interp.c:1030-1034 - exec	0.02	0.01
○Loop 809 - par_multi_interp.c:1017-1020 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code