OV - exec - Function hypre_BoomerAMGBuildMultipass._omp

	Function: hypre_BoomerAMGBuildMultipass._omp_fn.6	Module: exec	Source: par_multi_interp.c:1167-1173	Coverage: 0.23%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1167 - 1173

--------------------------------------------------------------------------------

1167: #pragma omp parallel for private(i,i1) HYPRE_SMP_SCHEDULE

1168: #endif

1169:    for (i=0; i < n_coarse; i++)

1170:    {

1171:       i1 = C_array[i];

1172:       P_diag_j[P_diag_i[i1]] = fine_to_coarse[i1];

1173:       P_diag_data[P_diag_i[i1]] = 1.0;

0x44bd90 STP	X29, X30, [SP, #976]!

0x44bd94 ADD	X29, SP, #0

0x44bd98 STR	X21, [SP, #32]

0x44bd9c LDR	X21, [X0, #32]

0x44bda0 STP	X19, X20, [SP, #16]

0x44bda4 ORR	X20, XZR, X0

0x44bda8 BL	40f6a0

0x44bdac SBFM	X19, X0, #0, #31

0x44bdb0 BL	40f540

0x44bdb4 SDIV	X3, X21, X19

0x44bdb8 SBFM	X1, X0, #0, #31

0x44bdbc MSUB	X2, X3, X19, X21

0x44bdc0 CMP	X1, X2

0x44bdc4 B.LT	44bee0

(797) 0x44bdc8 MADD	X7, X3, X1, X2

(797) 0x44bdcc ADD	X8, X3, X7

(797) 0x44bdd0 CMP	X7, X8

(797) 0x44bdd4 B.GE	44bed0

(797) 0x44bdd8 LDP	X5, X0, [X20, #16]

(797) 0x44bddc FMOV	D0, #1.0000000

(797) 0x44bde0 LDP	X4, X11, [X20]

(797) 0x44bde4 ADD	X1, X0, X7,LSL #3

(797) 0x44bde8 ADD	X12, X0, X8,LSL #3

(797) 0x44bdec LDR	X6, [X20, #40]

(797) 0x44bdf0 SUB	X9, X12, X1

(797) 0x44bdf4 SUB	X10, X9, #8

(797) 0x44bdf8 UBFM	X13, X10, #3, #63

(797) 0x44bdfc ADD	X14, X13, #1

(797) 0x44be00 ANDS	X15, X14, #4160

(797) 0x44be04 B.EQ	44be60

(797) 0x44be08 CMP	X15, #1

(797) 0x44be0c B.EQ	44be38

(797) 0x44be10 CMP	X15, #2

(797) 0x44be14 B.NE	44beec

(797) 0x44be18 LDR	X19, [X1], #8

(797) 0x44be1c UBFM	X3, X19, #61, #60

(797) 0x44be20 ADD	X2, X11, X3

(797) 0x44be24 LDR	X7, [X6, X3]

(797) 0x44be28 LDR	X8, [X2]

(797) 0x44be2c STR	X7, [X5, X8,LSL #3]

(797) 0x44be30 LDR	X0, [X2]

(797) 0x44be34 STR	D0, [X4, X0,LSL #3]

(797) 0x44be38 LDR	X9, [X1], #8

(797) 0x44be3c UBFM	X10, X9, #61, #60

(797) 0x44be40 ADD	X13, X11, X10

(797) 0x44be44 LDR	X14, [X6, X10]

(797) 0x44be48 LDR	X15, [X13]

(797) 0x44be4c STR	X14, [X5, X15,LSL #3]

(797) 0x44be50 LDR	X16, [X13]

(797) 0x44be54 STR	D0, [X4, X16,LSL #3]

(797) 0x44be58 CMP	X12, X1

(797) 0x44be5c B.EQ	44bed0

  (798) 0x44be60 ORR	X17, XZR, X1

  (798) 0x44be64 ADD	X1, X1, #32

  (798) 0x44be68 LDR	X18, [X17], #8

  (798) 0x44be6c LDR	X30, [X6, X18,LSL #3]

  (798) 0x44be70 LDR	X20, [X11, X18,LSL #3]

  (798) 0x44be74 STR	X30, [X5, X20,LSL #3]

  (798) 0x44be78 LDUR	X19, [X1, #488]

  (798) 0x44be7c LDR	X21, [X11, X18,LSL #3]

  (798) 0x44be80 LDR	X3, [X6, X19,LSL #3]

  (798) 0x44be84 LDR	X2, [X11, X19,LSL #3]

  (798) 0x44be88 STR	D0, [X4, X21,LSL #3]

  (798) 0x44be8c STR	X3, [X5, X2,LSL #3]

  (798) 0x44be90 LDR	X7, [X17, #8]

  (798) 0x44be94 LDR	X9, [X11, X19,LSL #3]

  (798) 0x44be98 LDR	X8, [X6, X7,LSL #3]

  (798) 0x44be9c LDR	X0, [X11, X7,LSL #3]

  (798) 0x44bea0 STR	D0, [X4, X9,LSL #3]

  (798) 0x44bea4 STR	X8, [X5, X0,LSL #3]

  (798) 0x44bea8 LDUR	X13, [X1, #504]

  (798) 0x44beac LDR	X10, [X11, X7,LSL #3]

  (798) 0x44beb0 LDR	X14, [X6, X13,LSL #3]

  (798) 0x44beb4 LDR	X15, [X11, X13,LSL #3]

  (798) 0x44beb8 STR	D0, [X4, X10,LSL #3]

  (798) 0x44bebc STR	X14, [X5, X15,LSL #3]

  (798) 0x44bec0 LDR	X16, [X11, X13,LSL #3]

  (798) 0x44bec4 STR	D0, [X4, X16,LSL #3]

  (798) 0x44bec8 CMP	X12, X1

  (798) 0x44becc B.NE	44be60

(797) 0x44bed0 LDP	X19, X20, [SP, #16]

(797) 0x44bed4 LDR	X21, [SP, #32]

(797) 0x44bed8 LDP	X29, X30, [SP], #48

(797) 0x44bedc RET

(797) 0x44bee0 ADD	X3, X3, #1

(797) 0x44bee4 MOVZ	X2, #0

(797) 0x44bee8 B	44bdc8

(797) 0x44beec LDR	X16, [X1], #8

(797) 0x44bef0 UBFM	X17, X16, #61, #60

(797) 0x44bef4 ADD	X18, X11, X17

(797) 0x44bef8 LDR	X30, [X6, X17]

(797) 0x44befc LDR	X20, [X18]

(797) 0x44bf00 STR	X30, [X5, X20,LSL #3]

(797) 0x44bf04 LDR	X21, [X18]

(797) 0x44bf08 STR	D0, [X4, X21,LSL #3]

(797) 0x44bf0c B	44be18

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	par_multi_interp.c:1167-1173
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1167-1173.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 20.00 to 10.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 44bd90

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X21, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X0, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40f6a0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40f540 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SDIV X3, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MSUB X2, X3, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP X1, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 44bee0 <hypre_BoomerAMGBuildMultipass._omp_fn.6+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	par_multi_interp.c:1167-1173
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1167-1173.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 44bd90

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X21, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X0, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40f6a0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40f540 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SDIV X3, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MSUB X2, X3, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP X1, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 44bee0 <hypre_BoomerAMGBuildMultipass._omp_fn.6+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGBuildMultipass._omp_fn.6–	0.23	0.09
▼Loop 797 - par_multi_interp.c:1167-1173 - exec–	0	0
○Loop 798 - par_multi_interp.c:1172-1173 - exec	0.23	0.07

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code