OV - exec - Function hypre

	Function: hypre_qsort2abs	Module: exec	Source: par_interp.c:3178-3192	Coverage: 0.01%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_interp.c: 3178 - 3192

--------------------------------------------------------------------------------

3178: {

3179:    HYPRE_Int i, last;

3180:    if (left >= right)

3181:       return;

3182:    hypre_swap2( v, w, left, (left+right)/2);

3183:    last = left;

3184:    for (i = left+1; i <= right; i++)

3185:       if (fabs(w[i]) > fabs(w[left]))

3186:       {

3187:          hypre_swap2(v, w, ++last, i);

3188:       }

3189:    hypre_swap2(v, w, left, last);

3190:    hypre_qsort2abs(v, w, left, last-1);

3191:    hypre_qsort2abs(v, w, last+1, right);

3192: }

0x447440 STP	X29, X30, [SP, #928]!

0x447444 ADD	X29, SP, #0

0x447448 STP	X19, X20, [SP, #16]

0x44744c ORR	X20, XZR, X1

0x447450 STP	X21, X22, [SP, #32]

0x447454 ORR	X22, XZR, X2

0x447458 STP	X23, X24, [SP, #48]

0x44745c ORR	X24, XZR, X0

0x447460 STP	X25, X26, [SP, #64]

0x447464 ORR	X25, XZR, X3

0x447468 STR	X27, [SP, #80]

(720) 0x44746c CMP	X25, X22

(720) 0x447470 B.LE	4476f0

  (721) 0x447474 ADD	X3, X25, X22

  (721) 0x447478 ORR	X2, XZR, X22

  (721) 0x44747c ADD	X4, X3, X3,LSR #63

  (721) 0x447480 ORR	X1, XZR, X20

  (721) 0x447484 ORR	X0, XZR, X24

  (721) 0x447488 ADD	X19, X22, #1

  (721) 0x44748c SBFM	X3, X4, #1, #63

  (721) 0x447490 BL	516f00

  (721) 0x447494 CMP	X25, X19

  (721) 0x447498 B.LT	44787c

  (721) 0x44749c LDR	D1, [X20, X19,LSL #3]

  (721) 0x4474a0 UBFM	X27, X22, #61, #60

  (721) 0x4474a4 SUB	X23, X25, X19

  (721) 0x4474a8 ADD	X26, X20, X27

  (721) 0x4474ac AND	X23, X23, #4224

  (721) 0x4474b0 LDR	D0, [X20, X22,LSL #3]

  (721) 0x4474b4 ORR	X21, XZR, X22

  (721) 0x4474b8 FABS	D2, D1

  (721) 0x4474bc FABS	D3, D0

  (721) 0x4474c0 FCMPE	D2, D3

  (721) 0x4474c4 B.GT	44777c

  (721) 0x4474c8 ADD	X19, X19, #1

  (721) 0x4474cc CMP	X25, X19

  (721) 0x4474d0 B.LT	4476bc

  (721) 0x4474d4 CBZ	X23, 4475d4

      (723) 0x4474d8 CMP	X23, #1

      (723) 0x4474dc B.EQ	4475b0

    (725) 0x4474e0 CMP	X23, #2

    (725) 0x4474e4 B.EQ	447594

    (725) 0x4474e8 CMP	X23, #3

    (725) 0x4474ec B.EQ	447578

    (725) 0x4474f0 CMP	X23, #4

    (725) 0x4474f4 B.EQ	44755c

    (725) 0x4474f8 CMP	X23, #5

    (725) 0x4474fc B.EQ	447540

    (725) 0x447500 CMP	X23, #6

    (725) 0x447504 B.EQ	447524

    (725) 0x447508 LDR	D4, [X20, X19,LSL #3]

    (725) 0x44750c LDR	D5, [X20, X27]

    (725) 0x447510 FABS	D6, D4

    (725) 0x447514 FABS	D7, D5

    (725) 0x447518 FCMPE	D6, D7

    (725) 0x44751c B.GT	4478b4

    (725) 0x447520 ADD	X19, X19, #1

    (725) 0x447524 LDR	D16, [X20, X19,LSL #3]

    (725) 0x447528 LDR	D17, [X20, X27]

    (725) 0x44752c FABS	D18, D16

    (725) 0x447530 FABS	D19, D17

    (725) 0x447534 FCMPE	D18, D19

    (725) 0x447538 B.GT	447898

    (725) 0x44753c ADD	X19, X19, #1

    (725) 0x447540 LDR	D20, [X20, X19,LSL #3]

    (725) 0x447544 LDR	D21, [X20, X27]

    (725) 0x447548 FABS	D22, D20

    (725) 0x44754c FABS	D23, D21

    (725) 0x447550 FCMPE	D22, D23

    (725) 0x447554 B.GT	447760

    (725) 0x447558 ADD	X19, X19, #1

    (725) 0x44755c LDR	D24, [X20, X19,LSL #3]

    (725) 0x447560 LDR	D25, [X20, X27]

    (725) 0x447564 FABS	D26, D24

    (725) 0x447568 FABS	D27, D25

    (725) 0x44756c FCMPE	D26, D27

    (725) 0x447570 B.GT	447744

    (725) 0x447574 ADD	X19, X19, #1

    (725) 0x447578 LDR	D28, [X20, X19,LSL #3]

    (725) 0x44757c LDR	D29, [X20, X27]

    (725) 0x447580 FABS	D30, D28

    (725) 0x447584 FABS	D31, D29

    (725) 0x447588 FCMPE	D30, D31

    (725) 0x44758c B.GT	447728

    (725) 0x447590 ADD	X19, X19, #1

    (725) 0x447594 LDR	D1, [X20, X19,LSL #3]

    (725) 0x447598 LDR	D0, [X20, X27]

    (725) 0x44759c FABS	D2, D1

    (725) 0x4475a0 FABS	D3, D0

    (725) 0x4475a4 FCMPE	D2, D3

    (725) 0x4475a8 B.GT	44770c

    (725) 0x4475ac ADD	X19, X19, #1

      (723) 0x4475b0 LDR	D4, [X20, X19,LSL #3]

      (723) 0x4475b4 LDR	D5, [X20, X27]

      (723) 0x4475b8 FABS	D6, D4

      (723) 0x4475bc FABS	D7, D5

      (723) 0x4475c0 FCMPE	D6, D7

      (723) 0x4475c4 B.GT	447860

(720) 0x4475c8 ADD	X19, X19, #1

(720) 0x4475cc CMP	X25, X19

(720) 0x4475d0 B.LT	4476bc

    (722) 0x4475d4 LDR	D16, [X20, X19,LSL #3]

    (722) 0x4475d8 LDR	D18, [X26]

    (722) 0x4475dc FABS	D17, D16

    (722) 0x4475e0 FABS	D19, D18

    (722) 0x4475e4 FCMPE	D17, D19

    (722) 0x4475e8 B.GT	4477e4

    (722) 0x4475ec ADD	X19, X19, #1

    (722) 0x4475f0 LDR	D22, [X26]

    (722) 0x4475f4 LDR	D20, [X20, X19,LSL #3]

    (722) 0x4475f8 FABS	D23, D22

    (722) 0x4475fc FABS	D21, D20

    (722) 0x447600 FCMPE	D21, D23

    (722) 0x447604 B.GT	4477c8

    (722) 0x447608 ADD	X3, X19, #1

    (722) 0x44760c LDR	D26, [X26]

    (722) 0x447610 LDR	D24, [X20, X3,LSL #3]

    (722) 0x447614 FABS	D27, D26

    (722) 0x447618 FABS	D25, D24

    (722) 0x44761c FCMPE	D25, D27

    (722) 0x447620 B.GT	447848

    (722) 0x447624 ADD	X3, X19, #2

    (722) 0x447628 LDR	D30, [X26]

    (722) 0x44762c LDR	D28, [X20, X3,LSL #3]

    (722) 0x447630 FABS	D31, D30

    (722) 0x447634 FABS	D29, D28

    (722) 0x447638 FCMPE	D29, D31

    (722) 0x44763c B.GT	447830

    (722) 0x447640 ADD	X3, X19, #3

    (722) 0x447644 LDR	D0, [X26]

    (722) 0x447648 LDR	D1, [X20, X3,LSL #3]

    (722) 0x44764c FABS	D3, D0

    (722) 0x447650 FABS	D2, D1

    (722) 0x447654 FCMPE	D2, D3

    (722) 0x447658 B.GT	447818

    (722) 0x44765c ADD	X3, X19, #4

    (722) 0x447660 LDR	D6, [X26]

    (722) 0x447664 LDR	D4, [X20, X3,LSL #3]

    (722) 0x447668 FABS	D7, D6

    (722) 0x44766c FABS	D5, D4

    (722) 0x447670 FCMPE	D5, D7

    (722) 0x447674 B.GT	447800

    (722) 0x447678 ADD	X3, X19, #5

    (722) 0x44767c LDR	D18, [X26]

    (722) 0x447680 LDR	D16, [X20, X3,LSL #3]

    (722) 0x447684 FABS	D19, D18

    (722) 0x447688 FABS	D17, D16

    (722) 0x44768c FCMPE	D17, D19

    (722) 0x447690 B.GT	4477b0

    (722) 0x447694 ADD	X3, X19, #6

    (722) 0x447698 LDR	D22, [X26]

    (722) 0x44769c LDR	D20, [X20, X3,LSL #3]

    (722) 0x4476a0 FABS	D23, D22

    (722) 0x4476a4 FABS	D21, D20

    (722) 0x4476a8 FCMPE	D21, D23

    (722) 0x4476ac B.GT	447798

    (722) 0x4476b0 ADD	X19, X19, #7

    (722) 0x4476b4 CMP	X25, X19

    (722) 0x4476b8 B.GE	4475d4

  (721) 0x4476bc ORR	X2, XZR, X22

  (721) 0x4476c0 ORR	X3, XZR, X21

  (721) 0x4476c4 ORR	X1, XZR, X20

  (721) 0x4476c8 ORR	X0, XZR, X24

  (721) 0x4476cc BL	516f00

  (721) 0x4476d0 ORR	X2, XZR, X22

  (721) 0x4476d4 SUB	X3, X21, #1

  (721) 0x4476d8 ORR	X1, XZR, X20

  (721) 0x4476dc ORR	X0, XZR, X24

  (721) 0x4476e0 ADD	X22, X21, #1

  (721) 0x4476e4 BL	447440

  (721) 0x4476e8 CMP	X22, X25

  (721) 0x4476ec B.LT	447474

  (726) 0x4476f0 LDP	X19, X20, [SP, #16]

  (726) 0x4476f4 LDP	X21, X22, [SP, #32]

  (726) 0x4476f8 LDP	X23, X24, [SP, #48]

  (726) 0x4476fc LDP	X25, X26, [SP, #64]

  (726) 0x447700 LDR	X27, [SP, #80]

  (726) 0x447704 LDP	X29, X30, [SP], #96

  (726) 0x447708 RET

  (724) 0x44770c ADD	X21, X21, #1

  (724) 0x447710 ORR	X3, XZR, X19

  (724) 0x447714 ORR	X2, XZR, X21

  (724) 0x447718 ORR	X1, XZR, X20

  (724) 0x44771c ORR	X0, XZR, X24

  (724) 0x447720 BL	516f00

  (724) 0x447724 B	4475ac

    (725) 0x447728 ADD	X21, X21, #1

    (725) 0x44772c ORR	X3, XZR, X19

    (725) 0x447730 ORR	X2, XZR, X21

    (725) 0x447734 ORR	X1, XZR, X20

    (725) 0x447738 ORR	X0, XZR, X24

    (725) 0x44773c BL	516f00

    (725) 0x447740 B	447590

    (725) 0x447744 ADD	X21, X21, #1

    (725) 0x447748 ORR	X3, XZR, X19

    (725) 0x44774c ORR	X2, XZR, X21

    (725) 0x447750 ORR	X1, XZR, X20

    (725) 0x447754 ORR	X0, XZR, X24

    (725) 0x447758 BL	516f00

    (725) 0x44775c B	447574

    (725) 0x447760 ADD	X21, X21, #1

    (725) 0x447764 ORR	X3, XZR, X19

    (725) 0x447768 ORR	X2, XZR, X21

    (725) 0x44776c ORR	X1, XZR, X20

    (725) 0x447770 ORR	X0, XZR, X24

    (725) 0x447774 BL	516f00

    (725) 0x447778 B	447558

  (721) 0x44777c ORR	X3, XZR, X19

  (721) 0x447780 ORR	X2, XZR, X19

  (721) 0x447784 ORR	X1, XZR, X20

  (721) 0x447788 ORR	X0, XZR, X24

  (721) 0x44778c ORR	X21, XZR, X19

  (721) 0x447790 BL	516f00

  (721) 0x447794 B	4474c8

    (722) 0x447798 ADD	X21, X21, #1

    (722) 0x44779c ORR	X1, XZR, X20

    (722) 0x4477a0 ORR	X2, XZR, X21

    (722) 0x4477a4 ORR	X0, XZR, X24

    (722) 0x4477a8 BL	516f00

    (722) 0x4477ac B	4476b0

    (722) 0x4477b0 ADD	X21, X21, #1

    (722) 0x4477b4 ORR	X1, XZR, X20

    (722) 0x4477b8 ORR	X2, XZR, X21

    (722) 0x4477bc ORR	X0, XZR, X24

    (722) 0x4477c0 BL	516f00

    (722) 0x4477c4 B	447694

    (722) 0x4477c8 ADD	X21, X21, #1

    (722) 0x4477cc ORR	X3, XZR, X19

    (722) 0x4477d0 ORR	X2, XZR, X21

    (722) 0x4477d4 ORR	X1, XZR, X20

    (722) 0x4477d8 ORR	X0, XZR, X24

    (722) 0x4477dc BL	516f00

    (722) 0x4477e0 B	447608

    (722) 0x4477e4 ADD	X21, X21, #1

    (722) 0x4477e8 ORR	X3, XZR, X19

    (722) 0x4477ec ORR	X2, XZR, X21

    (722) 0x4477f0 ORR	X1, XZR, X20

    (722) 0x4477f4 ORR	X0, XZR, X24

    (722) 0x4477f8 BL	516f00

    (722) 0x4477fc B	4475ec

    (722) 0x447800 ADD	X21, X21, #1

    (722) 0x447804 ORR	X1, XZR, X20

    (722) 0x447808 ORR	X2, XZR, X21

    (722) 0x44780c ORR	X0, XZR, X24

    (722) 0x447810 BL	516f00

    (722) 0x447814 B	447678

    (722) 0x447818 ADD	X21, X21, #1

    (722) 0x44781c ORR	X1, XZR, X20

    (722) 0x447820 ORR	X2, XZR, X21

    (722) 0x447824 ORR	X0, XZR, X24

    (722) 0x447828 BL	516f00

    (722) 0x44782c B	44765c

    (722) 0x447830 ADD	X21, X21, #1

    (722) 0x447834 ORR	X1, XZR, X20

    (722) 0x447838 ORR	X2, XZR, X21

    (722) 0x44783c ORR	X0, XZR, X24

    (722) 0x447840 BL	516f00

    (722) 0x447844 B	447640

    (722) 0x447848 ADD	X21, X21, #1

    (722) 0x44784c ORR	X1, XZR, X20

    (722) 0x447850 ORR	X2, XZR, X21

    (722) 0x447854 ORR	X0, XZR, X24

    (722) 0x447858 BL	516f00

    (722) 0x44785c B	447624

(720) 0x447860 ADD	X21, X21, #1

(720) 0x447864 ORR	X3, XZR, X19

(720) 0x447868 ORR	X2, XZR, X21

(720) 0x44786c ORR	X1, XZR, X20

(720) 0x447870 ORR	X0, XZR, X24

(720) 0x447874 BL	516f00

(720) 0x447878 B	4475c8

(720) 0x44787c ORR	X3, XZR, X22

(720) 0x447880 ORR	X2, XZR, X22

(720) 0x447884 ORR	X1, XZR, X20

(720) 0x447888 ORR	X0, XZR, X24

(720) 0x44788c SUB	X25, X22, #1

(720) 0x447890 BL	516f00

(720) 0x447894 B	44746c

    (725) 0x447898 ADD	X21, X21, #1

    (725) 0x44789c ORR	X3, XZR, X19

    (725) 0x4478a0 ORR	X2, XZR, X21

    (725) 0x4478a4 ORR	X1, XZR, X20

    (725) 0x4478a8 ORR	X0, XZR, X24

    (725) 0x4478ac BL	516f00

    (725) 0x4478b0 B	44753c

    (725) 0x4478b4 ADD	X21, X21, #1

    (725) 0x4478b8 ORR	X3, XZR, X19

    (725) 0x4478bc ORR	X2, XZR, X21

    (725) 0x4478c0 ORR	X1, XZR, X20

    (725) 0x4478c4 ORR	X0, XZR, X24

    (725) 0x4478c8 BL	516f00

    (725) 0x4478cc B	447520

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	par_interp.c:3178-3192
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_interp.c:3178-3192.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 3.00 to 0.75 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is storing 88 bytes.

General properties

nb instructions	11
loop length	44
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.00	0.00	1.50	1.50	1.50	1.50	0.00	0.00	0.00	0.00	3.00	3.00	0.00	3.00	3.00
cycles	0.00	0.00	1.50	1.50	1.50	1.50	0.00	0.00	0.00	0.00	3.00	3.00	0.00	3.00	3.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	1.38
Overall L1	3.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.00 cycles. At this rate:

61% of peak store performance is reached (29.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 447440

Instruction	Nb FU	P2	P3	P4	P5	P10	P11	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #928]!	1	0.25	0.25	0.25	0.25	0.50	0.50	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
ORR X20, XZR, X1	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
ORR X22, XZR, X2	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
ORR X24, XZR, X0	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
ORR X25, XZR, X3	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STR X27, [SP, #80]	1	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50

Source file and lines	par_interp.c:3178-3192
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_interp.c:3178-3192.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is storing 88 bytes.

General properties

nb instructions	11
loop length	44
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.00	0.00	1.50	1.50	1.50	1.50	0.00	0.00	0.00	0.00	3.00	3.00	0.00	3.00	3.00
cycles	0.00	0.00	1.50	1.50	1.50	1.50	0.00	0.00	0.00	0.00	3.00	3.00	0.00	3.00	3.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	1.38
Overall L1	3.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.00 cycles. At this rate:

61% of peak store performance is reached (29.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 447440

Instruction	Nb FU	P2	P3	P4	P5	P10	P11	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #928]!	1	0.25	0.25	0.25	0.25	0.50	0.50	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
ORR X20, XZR, X1	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
ORR X22, XZR, X2	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
ORR X24, XZR, X0	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50
ORR X25, XZR, X3	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
STR X27, [SP, #80]	1	0	0	0	0	0.50	0.50	0.50	0.50	1	0.50

Name	Coverage (%)	Time (s)
▼hypre_qsort2abs–	0.01	0
▼Loop 720 - par_interp.c:3180-3192 - exec–	0	0
○Loop 726 - par_interp.c:3192-3192 - exec	0	0
▼Loop 721 - par_interp.c:3180-3191 - exec–	0	0
○Loop 722 - par_interp.c:3184-3187 - exec	0	0
▼Loop 724 - par_interp.c:3184-3187 - exec–	0	0
▼Loop 725 - par_interp.c:3184-3187 - exec–	0	0
○Loop 723 - par_interp.c:3184-3185 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code