OV - exec - Function hypre_BoomerAMGCoarseParms

	Function: hypre_BoomerAMGCoarseParms	Module: exec	Source: par_coarse_parms.c:76-146 [...]	Coverage: 0.01%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarse_parms.c: 76 - 146

--------------------------------------------------------------------------------

76: {

[...]

84:    HYPRE_Int            local_coarse_size = 0;

[...]

92:    hypre_MPI_Comm_size(comm,&num_procs);

93:

94:    for (i=0; i < local_num_variables; i++)

95:    {

96:       if (CF_marker[i] == 1) local_coarse_size++;

97:    }

98:    if (num_functions > 1)

99:    {

100:       coarse_dof_func = hypre_CTAlloc(HYPRE_Int,local_coarse_size);

101:

102:       local_coarse_size = 0;

103:       for (i=0; i < local_num_variables; i++)

104:       {

105:          if (CF_marker[i] == 1)

106:             coarse_dof_func[local_coarse_size++] = dof_func[i];

107:       }

108:       *coarse_dof_func_ptr    = coarse_dof_func;

[...]

116:       coarse_pnts_global = hypre_CTAlloc(HYPRE_Int,2);

117:       hypre_MPI_Scan(&local_coarse_size, &scan_recv, 1, HYPRE_MPI_INT, hypre_MPI_SUM, comm);

118:       /* first point in my range */

119:       coarse_pnts_global[0] = scan_recv - local_coarse_size;

120:       /* first point in next proc's range */

121:       coarse_pnts_global[1] = scan_recv;

[...]

139:    *coarse_pnts_global_ptr = coarse_pnts_global;

[...]

146: }

0x42a960 ADRP	X7,

0x42a964 STP	X29, X30, [SP, #912]!

0x42a968 ADD	X29, SP, #0

0x42a96c LDR	X8, [X7, #3848]

0x42a970 STP	X19, X20, [SP, #16]

0x42a974 ORR	X20, XZR, X6

0x42a978 ORR	X19, XZR, X0

0x42a97c STP	X21, X22, [SP, #32]

0x42a980 ORR	X21, XZR, X2

0x42a984 ORR	X22, XZR, X5

0x42a988 STP	X23, X24, [SP, #48]

0x42a98c ORR	X24, XZR, X1

0x42a990 ADD	X1, SP, #80

0x42a994 ORR	X23, XZR, X4

0x42a998 STR	X25, [SP, #64]

0x42a99c LDR	X2, [X8]

0x42a9a0 STR	X2, [SP, #104]

0x42a9a4 MOVZ	X2, #0

0x42a9a8 ORR	X25, XZR, X3

0x42a9ac STR	XZR, [SP, #88]

0x42a9b0 BL	5186e0

0x42a9b4 CMP	X24, #0

0x42a9b8 B.LE	42ae74

0x42a9bc UBFM	X0, X24, #61, #60

0x42a9c0 LDR	X9, [SP, #88]

0x42a9c4 ADD	X4, X23, X24,LSL #3

0x42a9c8 SUB	X2, X0, #8

0x42a9cc ORR	X10, XZR, X23

0x42a9d0 UBFM	X3, X2, #3, #63

0x42a9d4 MOVZ	W1, #0

0x42a9d8 ADD	X5, X3, #1

0x42a9dc ANDS	X6, X5, #4224

0x42a9e0 ORR	X0, XZR, X9

0x42a9e4 B.EQ	42aa98

0x42a9e8 CMP	X6, #1

0x42a9ec B.EQ	42aa78

0x42a9f0 CMP	X6, #2

0x42a9f4 B.EQ	42aa68

0x42a9f8 CMP	X6, #3

0x42a9fc B.EQ	42aa58

0x42aa00 CMP	X6, #4

0x42aa04 B.EQ	42aa48

0x42aa08 CMP	X6, #5

0x42aa0c B.EQ	42aa38

0x42aa10 CMP	X6, #6

0x42aa14 B.EQ	42aa28

0x42aa18 LDR	X10, [X23]

0x42aa1c CMP	X10, #1

0x42aa20 B.EQ	42aeac

0x42aa24 ADD	X10, X23, #8

0x42aa28 LDR	X11, [X10]

0x42aa2c CMP	X11, #1

0x42aa30 B.EQ	42ae4c

0x42aa34 ADD	X10, X10, #8

0x42aa38 LDR	X12, [X10]

0x42aa3c CMP	X12, #1

0x42aa40 B.EQ	42ae10

0x42aa44 ADD	X10, X10, #8

0x42aa48 LDR	X13, [X10]

0x42aa4c CMP	X13, #1

0x42aa50 B.EQ	42ae00

0x42aa54 ADD	X10, X10, #8

0x42aa58 LDR	X14, [X10]

0x42aa5c CMP	X14, #1

0x42aa60 B.EQ	42adf4

0x42aa64 ADD	X10, X10, #8

0x42aa68 LDR	X15, [X10]

0x42aa6c CMP	X15, #1

0x42aa70 B.EQ	42abdc

(316) 0x42aa74 ADD	X10, X10, #8

(316) 0x42aa78 LDR	X16, [X10]

(316) 0x42aa7c CMP	X16, #1

(316) 0x42aa80 B.NE	42aa8c

(316) 0x42aa84 ADD	X0, X0, #1

(316) 0x42aa88 ORR	W1, WZR, W16

(316) 0x42aa8c ADD	X10, X10, #8

(316) 0x42aa90 CMP	X4, X10

(316) 0x42aa94 B.EQ	42ab48

  (317) 0x42aa98 LDR	X17, [X10]

  (317) 0x42aa9c CMP	X17, #1

  (317) 0x42aaa0 B.NE	42aaac

  (317) 0x42aaa4 ADD	X0, X0, #1

  (317) 0x42aaa8 ORR	W1, WZR, W17

  (317) 0x42aaac LDR	X18, [X10, #8]

  (317) 0x42aab0 ADD	X30, X10, #8

  (317) 0x42aab4 CMP	X18, #1

  (317) 0x42aab8 B.NE	42aac4

  (317) 0x42aabc ADD	X0, X0, #1

  (317) 0x42aac0 ORR	W1, WZR, W18

  (317) 0x42aac4 LDR	X7, [X30, #8]

  (317) 0x42aac8 CMP	X7, #1

  (317) 0x42aacc B.NE	42aad8

  (317) 0x42aad0 ADD	X0, X0, #1

  (317) 0x42aad4 ORR	W1, WZR, W7

  (317) 0x42aad8 LDR	X8, [X30, #16]

  (317) 0x42aadc CMP	X8, #1

  (317) 0x42aae0 B.NE	42aaec

  (317) 0x42aae4 ADD	X0, X0, #1

  (317) 0x42aae8 ORR	W1, WZR, W8

  (317) 0x42aaec LDR	X2, [X30, #24]

  (317) 0x42aaf0 CMP	X2, #1

  (317) 0x42aaf4 B.NE	42ab00

  (317) 0x42aaf8 ADD	X0, X0, #1

  (317) 0x42aafc ORR	W1, WZR, W2

  (317) 0x42ab00 LDR	X3, [X30, #32]

  (317) 0x42ab04 CMP	X3, #1

  (317) 0x42ab08 B.NE	42ab14

  (317) 0x42ab0c ADD	X0, X0, #1

  (317) 0x42ab10 ORR	W1, WZR, W3

  (317) 0x42ab14 LDR	X5, [X30, #40]

  (317) 0x42ab18 CMP	X5, #1

  (317) 0x42ab1c B.NE	42ab28

  (317) 0x42ab20 ADD	X0, X0, #1

  (317) 0x42ab24 ORR	W1, WZR, W5

  (317) 0x42ab28 LDR	X6, [X30, #48]

  (317) 0x42ab2c CMP	X6, #1

  (317) 0x42ab30 B.NE	42ab3c

  (317) 0x42ab34 ADD	X0, X0, #1

  (317) 0x42ab38 ORR	W1, WZR, W6

  (317) 0x42ab3c ADD	X10, X30, #56

  (317) 0x42ab40 CMP	X4, X10

  (317) 0x42ab44 B.NE	42aa98

(316) 0x42ab48 CBZ	W1, 42adec

(316) 0x42ab4c STR	X0, [SP, #88]

(316) 0x42ab50 CMP	X21, #1

(316) 0x42ab54 B.GT	42abe8

(316) 0x42ab58 MOVZ	X1, #8

(316) 0x42ab5c MOVZ	X0, #2

(316) 0x42ab60 BL	51674c

(316) 0x42ab64 ADRP	X23,

(316) 0x42ab68 ADRP	X25,

(316) 0x42ab6c ORR	X24, XZR, X0

(316) 0x42ab70 ORR	X5, XZR, X19

(316) 0x42ab74 LDR	X4, [X23, #3800]

(316) 0x42ab78 MOVZ	X2, #1

(316) 0x42ab7c ADD	X1, SP, #96

(316) 0x42ab80 LDR	X3, [X25, #3944]

(316) 0x42ab84 ADD	X0, SP, #88

(316) 0x42ab88 BL	5191c0

(316) 0x42ab8c LDP	X18, X7, [SP, #88]

(316) 0x42ab90 ADRP	X0,

(316) 0x42ab94 LDR	X22, [X0, #3848]

(316) 0x42ab98 SUB	X8, X7, X18

(316) 0x42ab9c STR	X8, [X24]

(316) 0x42aba0 LDR	X5, [SP, #96]

(316) 0x42aba4 STR	X5, [X24, #8]

(316) 0x42aba8 STR	X24, [X20]

(316) 0x42abac LDR	X2, [SP, #104]

(316) 0x42abb0 LDR	X1, [X22]

(316) 0x42abb4 SUBS	X2, X2, X1

(316) 0x42abb8 MOVZ	X1, #0

(316) 0x42abbc B.NE	42aee8

(316) 0x42abc0 MOVZ	X0, #0

(316) 0x42abc4 LDP	X19, X20, [SP, #16]

(316) 0x42abc8 LDP	X21, X22, [SP, #32]

(316) 0x42abcc LDP	X23, X24, [SP, #48]

(316) 0x42abd0 LDR	X25, [SP, #64]

(316) 0x42abd4 LDP	X29, X30, [SP], #112

(316) 0x42abd8 RET

(316) 0x42abdc ADD	X0, X0, #1

(316) 0x42abe0 ORR	W1, WZR, W15

(316) 0x42abe4 B	42aa74

(316) 0x42abe8 MOVZ	X1, #8

(316) 0x42abec BL	51674c

(316) 0x42abf0 ANDS	X21, X24, #4224

(316) 0x42abf4 STR	XZR, [SP, #88]

(316) 0x42abf8 MOVZ	X2, #0

(316) 0x42abfc B.EQ	42acbc

(316) 0x42ac00 CMP	X21, #1

(316) 0x42ac04 B.EQ	42ac90

(316) 0x42ac08 CMP	X21, #2

(316) 0x42ac0c B.EQ	42ac80

(316) 0x42ac10 CMP	X21, #3

(316) 0x42ac14 B.EQ	42ac70

(316) 0x42ac18 CMP	X21, #4

(316) 0x42ac1c B.EQ	42ac60

(316) 0x42ac20 CMP	X21, #5

(316) 0x42ac24 B.EQ	42ac50

(316) 0x42ac28 CMP	X21, #6

(316) 0x42ac2c B.EQ	42ac40

(316) 0x42ac30 LDR	X4, [X23]

(316) 0x42ac34 CMP	X4, #1

(316) 0x42ac38 B.EQ	42aed4

(316) 0x42ac3c MOVZ	X2, #1

(316) 0x42ac40 LDR	X11, [X23, X2,LSL #3]

(316) 0x42ac44 CMP	X11, #1

(316) 0x42ac48 B.EQ	42aebc

(316) 0x42ac4c ADD	X2, X2, #1

(316) 0x42ac50 LDR	X15, [X23, X2,LSL #3]

(316) 0x42ac54 CMP	X15, #1

(316) 0x42ac58 B.EQ	42ae94

(316) 0x42ac5c ADD	X2, X2, #1

(316) 0x42ac60 LDR	X30, [X23, X2,LSL #3]

(316) 0x42ac64 CMP	X30, #1

(316) 0x42ac68 B.EQ	42ae58

(316) 0x42ac6c ADD	X2, X2, #1

(316) 0x42ac70 LDR	X5, [X23, X2,LSL #3]

(316) 0x42ac74 CMP	X5, #1

(316) 0x42ac78 B.EQ	42ae34

(316) 0x42ac7c ADD	X2, X2, #1

(316) 0x42ac80 LDR	X21, [X23, X2,LSL #3]

(316) 0x42ac84 CMP	X21, #1

(316) 0x42ac88 B.EQ	42ae1c

(316) 0x42ac8c ADD	X2, X2, #1

(316) 0x42ac90 LDR	X12, [X23, X2,LSL #3]

(316) 0x42ac94 CMP	X12, #1

(316) 0x42ac98 B.NE	42acb0

(316) 0x42ac9c LDR	X14, [SP, #88]

(316) 0x42aca0 LDR	X13, [X25, X2,LSL #3]

(316) 0x42aca4 ADD	X15, X14, #1

(316) 0x42aca8 STR	X15, [SP, #88]

(316) 0x42acac STR	X13, [X0, X14,LSL #3]

(316) 0x42acb0 ADD	X2, X2, #1

(316) 0x42acb4 CMP	X24, X2

(316) 0x42acb8 B.EQ	42ade4

  (315) 0x42acbc LDR	X16, [X23, X2,LSL #3]

  (315) 0x42acc0 CMP	X16, #1

  (315) 0x42acc4 B.NE	42acdc

  (315) 0x42acc8 LDR	X18, [SP, #88]

  (315) 0x42accc LDR	X17, [X25, X2,LSL #3]

  (315) 0x42acd0 ADD	X30, X18, #1

  (315) 0x42acd4 STR	X30, [SP, #88]

  (315) 0x42acd8 STR	X17, [X0, X18,LSL #3]

  (315) 0x42acdc ADD	X2, X2, #1

  (315) 0x42ace0 LDR	X7, [X23, X2,LSL #3]

  (315) 0x42ace4 CMP	X7, #1

  (315) 0x42ace8 B.NE	42ad00

  (315) 0x42acec LDR	X3, [SP, #88]

  (315) 0x42acf0 LDR	X8, [X25, X2,LSL #3]

  (315) 0x42acf4 ADD	X5, X3, #1

  (315) 0x42acf8 STR	X5, [SP, #88]

  (315) 0x42acfc STR	X8, [X0, X3,LSL #3]

  (315) 0x42ad00 ADD	X6, X2, #1

  (315) 0x42ad04 LDR	X1, [X23, X6,LSL #3]

  (315) 0x42ad08 CMP	X1, #1

  (315) 0x42ad0c B.NE	42ad24

  (315) 0x42ad10 LDR	X21, [SP, #88]

  (315) 0x42ad14 LDR	X10, [X25, X6,LSL #3]

  (315) 0x42ad18 ADD	X9, X21, #1

  (315) 0x42ad1c STR	X9, [SP, #88]

  (315) 0x42ad20 STR	X10, [X0, X21,LSL #3]

  (315) 0x42ad24 ADD	X11, X2, #2

  (315) 0x42ad28 LDR	X4, [X23, X11,LSL #3]

  (315) 0x42ad2c CMP	X4, #1

  (315) 0x42ad30 B.NE	42ad48

  (315) 0x42ad34 LDR	X13, [SP, #88]

  (315) 0x42ad38 LDR	X12, [X25, X11,LSL #3]

  (315) 0x42ad3c ADD	X14, X13, #1

  (315) 0x42ad40 STR	X14, [SP, #88]

  (315) 0x42ad44 STR	X12, [X0, X13,LSL #3]

  (315) 0x42ad48 ADD	X15, X2, #3

  (315) 0x42ad4c LDR	X16, [X23, X15,LSL #3]

  (315) 0x42ad50 CMP	X16, #1

  (315) 0x42ad54 B.NE	42ad6c

  (315) 0x42ad58 LDR	X18, [SP, #88]

  (315) 0x42ad5c LDR	X17, [X25, X15,LSL #3]

  (315) 0x42ad60 ADD	X30, X18, #1

  (315) 0x42ad64 STR	X30, [SP, #88]

  (315) 0x42ad68 STR	X17, [X0, X18,LSL #3]

  (315) 0x42ad6c ADD	X7, X2, #4

  (315) 0x42ad70 LDR	X8, [X23, X7,LSL #3]

  (315) 0x42ad74 CMP	X8, #1

  (315) 0x42ad78 B.NE	42ad90

  (315) 0x42ad7c LDR	X3, [SP, #88]

  (315) 0x42ad80 LDR	X5, [X25, X7,LSL #3]

  (315) 0x42ad84 ADD	X6, X3, #1

  (315) 0x42ad88 STR	X6, [SP, #88]

  (315) 0x42ad8c STR	X5, [X0, X3,LSL #3]

  (315) 0x42ad90 ADD	X1, X2, #5

  (315) 0x42ad94 LDR	X10, [X23, X1,LSL #3]

  (315) 0x42ad98 CMP	X10, #1

  (315) 0x42ad9c B.NE	42adb4

  (315) 0x42ada0 LDR	X9, [SP, #88]

  (315) 0x42ada4 LDR	X21, [X25, X1,LSL #3]

  (315) 0x42ada8 ADD	X11, X9, #1

  (315) 0x42adac STR	X11, [SP, #88]

  (315) 0x42adb0 STR	X21, [X0, X9,LSL #3]

  (315) 0x42adb4 ADD	X4, X2, #6

  (315) 0x42adb8 LDR	X12, [X23, X4,LSL #3]

  (315) 0x42adbc CMP	X12, #1

  (315) 0x42adc0 B.NE	42add8

  (315) 0x42adc4 LDR	X14, [SP, #88]

  (315) 0x42adc8 LDR	X13, [X25, X4,LSL #3]

  (315) 0x42adcc ADD	X15, X14, #1

  (315) 0x42add0 STR	X15, [SP, #88]

  (315) 0x42add4 STR	X13, [X0, X14,LSL #3]

  (315) 0x42add8 ADD	X2, X2, #7

  (315) 0x42addc CMP	X24, X2

  (315) 0x42ade0 B.NE	42acbc

(316) 0x42ade4 STR	X0, [X22]

(316) 0x42ade8 B	42ab58

(316) 0x42adec ORR	X0, XZR, X9

(316) 0x42adf0 B	42ab50

0x42adf4 ADD	X0, X0, #1

0x42adf8 ORR	W1, WZR, W14

0x42adfc B	42aa64

0x42ae00 ADD	X0, X0, #1

0x42ae04 ORR	W1, WZR, W13

0x42ae08 ADD	X10, X10, #8

0x42ae0c B	42aa58

0x42ae10 ADD	X0, X0, #1

0x42ae14 ORR	W1, WZR, W12

0x42ae18 B	42aa44

(316) 0x42ae1c LDR	X11, [SP, #88]

(316) 0x42ae20 LDR	X9, [X25, X2,LSL #3]

(316) 0x42ae24 ADD	X4, X11, #1

(316) 0x42ae28 STR	X4, [SP, #88]

(316) 0x42ae2c STR	X9, [X0, X11,LSL #3]

(316) 0x42ae30 B	42ac8c

(316) 0x42ae34 LDR	X1, [SP, #88]

(316) 0x42ae38 LDR	X6, [X25, X2,LSL #3]

(316) 0x42ae3c ADD	X10, X1, #1

(316) 0x42ae40 STR	X10, [SP, #88]

(316) 0x42ae44 STR	X6, [X0, X1,LSL #3]

(316) 0x42ae48 B	42ac7c

0x42ae4c ADD	X0, X0, #1

0x42ae50 ORR	W1, WZR, W11

0x42ae54 B	42aa34

(316) 0x42ae58 LDR	X8, [SP, #88]

(316) 0x42ae5c LDR	X7, [X25, X2,LSL #3]

(316) 0x42ae60 ADD	X2, X2, #1

(316) 0x42ae64 ADD	X3, X8, #1

(316) 0x42ae68 STR	X3, [SP, #88]

(316) 0x42ae6c STR	X7, [X0, X8,LSL #3]

(316) 0x42ae70 B	42ac70

0x42ae74 CMP	X21, #1

0x42ae78 B.LE	42ab58

0x42ae7c MOVZ	X1, #8

0x42ae80 LDR	X0, [SP, #88]

0x42ae84 BL	51674c

0x42ae88 STR	X0, [X22]

0x42ae8c STR	XZR, [SP, #88]

0x42ae90 B	42ab58

(316) 0x42ae94 LDR	X17, [SP, #88]

(316) 0x42ae98 LDR	X16, [X25, X2,LSL #3]

(316) 0x42ae9c ADD	X18, X17, #1

(316) 0x42aea0 STR	X18, [SP, #88]

(316) 0x42aea4 STR	X16, [X0, X17,LSL #3]

(316) 0x42aea8 B	42ac5c

0x42aeac ORR	W1, WZR, W10

0x42aeb0 ADD	X0, X9, #1

0x42aeb4 ADD	X10, X23, #8

0x42aeb8 B	42aa28

(316) 0x42aebc LDR	X13, [SP, #88]

(316) 0x42aec0 LDR	X12, [X25, X2,LSL #3]

(316) 0x42aec4 ADD	X14, X13, #1

(316) 0x42aec8 STR	X14, [SP, #88]

(316) 0x42aecc STR	X12, [X0, X13,LSL #3]

(316) 0x42aed0 B	42ac4c

(316) 0x42aed4 LDR	X9, [X25]

(316) 0x42aed8 STR	X4, [SP, #88]

(316) 0x42aedc STR	X9, [X0, X2,LSL #3]

(316) 0x42aee0 MOVZ	X2, #1

(316) 0x42aee4 B	42ac40

0x42aee8 BL	40f2e0

0x42aeec HINT	#0

0x42aef0 HINT	#0

0x42aef4 HINT	#0

0x42aef8 HINT	#0

0x42aefc HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	par_coarse_parms.c:76-146
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarse_parms.c:76,84,92-108,116-121,139,146.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 14.00 to 2.72 cycles (5.15x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 14.00 to 1.50 cycles (9.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 80 bytes. The binary function is storing 104 bytes.

General properties

nb instructions	100
loop length	400
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	12.00	12.00	14.00	14.00	14.00	14.00	0.00	0.00	0.00	0.00	6.50	6.17	6.33	4.50	4.50
cycles	12.00	12.00	14.00	14.00	14.00	14.00	0.00	0.00	0.00	0.00	6.50	6.17	6.33	4.50	4.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.88
Overall L1	14.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.00 cycles. At this rate:

5% of peak load performance is reached (5.71 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
15% of peak store performance is reached (7.43 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42a960

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADRP X7, <54f960>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X7, #3848]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X21, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X24, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, SP, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X23, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X2, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X2, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR XZR, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 5186e0 <hypre_MPI_Comm_size>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X24, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 42ae74 <hypre_BoomerAMGCoarseParms+0x514>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X0, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X4, X23, X24,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X2, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X10, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X3, X2, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X6, X5, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ORR X0, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.EQ 42aa98 <hypre_BoomerAMGCoarseParms+0x138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42aa78 <hypre_BoomerAMGCoarseParms+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42aa68 <hypre_BoomerAMGCoarseParms+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42aa58 <hypre_BoomerAMGCoarseParms+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42aa48 <hypre_BoomerAMGCoarseParms+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42aa38 <hypre_BoomerAMGCoarseParms+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42aa28 <hypre_BoomerAMGCoarseParms+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42aeac <hypre_BoomerAMGCoarseParms+0x54c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X10, X23, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42ae4c <hypre_BoomerAMGCoarseParms+0x4ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42ae10 <hypre_BoomerAMGCoarseParms+0x4b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X13, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42ae00 <hypre_BoomerAMGCoarseParms+0x4a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42adf4 <hypre_BoomerAMGCoarseParms+0x494>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X15, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42abdc <hypre_BoomerAMGCoarseParms+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42aa64 <hypre_BoomerAMGCoarseParms+0x104>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42aa58 <hypre_BoomerAMGCoarseParms+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42aa44 <hypre_BoomerAMGCoarseParms+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42aa34 <hypre_BoomerAMGCoarseParms+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 42ab58 <hypre_BoomerAMGCoarseParms+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 51674c <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 42ab58 <hypre_BoomerAMGCoarseParms+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X23, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42aa28 <hypre_BoomerAMGCoarseParms+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 40f2e0 <@plt_start@+0xf0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0

Source file and lines	par_coarse_parms.c:76-146
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarse_parms.c:76,84,92-108,116-121,139,146.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 14.00 to 1.50 cycles (9.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 80 bytes. The binary function is storing 104 bytes.

General properties

nb instructions	100
loop length	400
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	12.00	12.00	14.00	14.00	14.00	14.00	0.00	0.00	0.00	0.00	6.50	6.17	6.33	4.50	4.50
cycles	12.00	12.00	14.00	14.00	14.00	14.00	0.00	0.00	0.00	0.00	6.50	6.17	6.33	4.50	4.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.88
Overall L1	14.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.00 cycles. At this rate:

5% of peak load performance is reached (5.71 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
15% of peak store performance is reached (7.43 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42a960

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADRP X7, <54f960>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X7, #3848]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X21, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X24, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, SP, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X23, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X2, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X2, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR XZR, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 5186e0 <hypre_MPI_Comm_size>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X24, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 42ae74 <hypre_BoomerAMGCoarseParms+0x514>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X0, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X4, X23, X24,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X2, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X10, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X3, X2, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X6, X5, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ORR X0, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.EQ 42aa98 <hypre_BoomerAMGCoarseParms+0x138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42aa78 <hypre_BoomerAMGCoarseParms+0x118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42aa68 <hypre_BoomerAMGCoarseParms+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42aa58 <hypre_BoomerAMGCoarseParms+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42aa48 <hypre_BoomerAMGCoarseParms+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42aa38 <hypre_BoomerAMGCoarseParms+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X6, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42aa28 <hypre_BoomerAMGCoarseParms+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42aeac <hypre_BoomerAMGCoarseParms+0x54c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X10, X23, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42ae4c <hypre_BoomerAMGCoarseParms+0x4ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42ae10 <hypre_BoomerAMGCoarseParms+0x4b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X13, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42ae00 <hypre_BoomerAMGCoarseParms+0x4a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42adf4 <hypre_BoomerAMGCoarseParms+0x494>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X15, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42abdc <hypre_BoomerAMGCoarseParms+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42aa64 <hypre_BoomerAMGCoarseParms+0x104>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42aa58 <hypre_BoomerAMGCoarseParms+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42aa44 <hypre_BoomerAMGCoarseParms+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42aa34 <hypre_BoomerAMGCoarseParms+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 42ab58 <hypre_BoomerAMGCoarseParms+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 51674c <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 42ab58 <hypre_BoomerAMGCoarseParms+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X23, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42aa28 <hypre_BoomerAMGCoarseParms+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 40f2e0 <@plt_start@+0xf0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCoarseParms–	0.01	0
▼Loop 316 - par_coarse_parms.c:94-146 - exec–	0	0
○Loop 317 - par_coarse_parms.c:94-96 - exec	0.01	0.13
○Loop 315 - par_coarse_parms.c:103-106 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code