OV - exec - Function hypre_BoomerAMGCoarsenPMIS._omp

	Function: hypre_BoomerAMGCoarsenPMIS._omp_fn.2	Module: exec	Source: par_coarsen.c:2132-2136	Coverage: 0.44%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 2132 - 2136

--------------------------------------------------------------------------------

2132: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

2133:    for (i=0; i < S_diag_i[num_variables]; i++)

2134:    {

2135: #pragma omp atomic

2136:       measure_array_temp[S_diag_j[i]]++;

0x422400 STP	X29, X30, [SP, #976]!

0x422404 ADD	X29, SP, #0

0x422408 STP	X19, X20, [SP, #16]

0x42240c ORR	X20, XZR, X0

0x422410 LDR	X0, [X0]

0x422414 LDR	X1, [X20, #16]

0x422418 STR	X21, [SP, #32]

0x42241c LDR	X21, [X0, X1,LSL #3]

0x422420 BL	40f6a0

0x422424 SBFM	X19, X0, #0, #31

0x422428 BL	40f540

0x42242c SBFM	X4, X0, #0, #31

0x422430 SDIV	X3, X21, X19

0x422434 MSUB	X2, X3, X19, X21

0x422438 CMP	X4, X2

0x42243c B.LT	422588

(180) 0x422440 MADD	X6, X3, X4, X2

(180) 0x422444 ADD	X7, X3, X6

(180) 0x422448 CMP	X6, X7

(180) 0x42244c B.GE	422578

(180) 0x422450 LDR	X5, [X20, #8]

(180) 0x422454 MOVZ	X8, #1

(180) 0x422458 LDR	X9, [X20, #24]

(180) 0x42245c ADD	X0, X5, X6,LSL #3

(180) 0x422460 ADD	X10, X5, X7,LSL #3

(180) 0x422464 SUB	X11, X10, X0

(180) 0x422468 SUB	X12, X11, #8

(180) 0x42246c UBFM	X13, X12, #3, #63

(180) 0x422470 ADD	X14, X13, X8

(180) 0x422474 ANDS	X15, X14, #4224

(180) 0x422478 B.EQ	422508

(180) 0x42247c CMP	X15, X8

(180) 0x422480 B.EQ	4224f4

(180) 0x422484 CMP	X15, #2

(180) 0x422488 B.EQ	4224e8

(180) 0x42248c CMP	X15, #3

(180) 0x422490 B.EQ	4224dc

(180) 0x422494 CMP	X15, #4

(180) 0x422498 B.EQ	4224d0

(180) 0x42249c CMP	X15, #5

(180) 0x4224a0 B.EQ	4224c4

(180) 0x4224a4 CMP	X15, #6

(180) 0x4224a8 B.EQ	4224b8

(180) 0x4224ac LDR	X16, [X0], #8

(180) 0x4224b0 ADD	X17, X9, X16,LSL #3

(180) 0x4224b4 LDADD	X8, X1, [X17]

(180) 0x4224b8 LDR	X18, [X0], #8

(180) 0x4224bc ADD	X30, X9, X18,LSL #3

(180) 0x4224c0 LDADD	X8, X1, [X30]

(180) 0x4224c4 LDR	X20, [X0], #8

(180) 0x4224c8 ADD	X1, X9, X20,LSL #3

(180) 0x4224cc LDADD	X8, X1, [X1]

(180) 0x4224d0 LDR	X21, [X0], #8

(180) 0x4224d4 ADD	X19, X9, X21,LSL #3

(180) 0x4224d8 LDADD	X8, X1, [X19]

(180) 0x4224dc LDR	X4, [X0], #8

(180) 0x4224e0 ADD	X3, X9, X4,LSL #3

(180) 0x4224e4 LDADD	X8, X1, [X3]

(180) 0x4224e8 LDR	X2, [X0], #8

(180) 0x4224ec ADD	X6, X9, X2,LSL #3

(180) 0x4224f0 LDADD	X8, X1, [X6]

(180) 0x4224f4 LDR	X7, [X0], #8

(180) 0x4224f8 ADD	X5, X9, X7,LSL #3

(180) 0x4224fc LDADD	X8, X1, [X5]

(180) 0x422500 CMP	X10, X0

(180) 0x422504 B.EQ	422578

  (181) 0x422508 ORR	X11, XZR, X0

  (181) 0x42250c LDR	X12, [X11], #8

  (181) 0x422510 ADD	X13, X9, X12,LSL #3

  (181) 0x422514 LDADD	X8, X1, [X13]

  (181) 0x422518 LDR	X14, [X0, #8]

  (181) 0x42251c ADD	X15, X9, X14,LSL #3

  (181) 0x422520 LDADD	X8, X1, [X15]

  (181) 0x422524 LDR	X16, [X11, #8]

  (181) 0x422528 ADD	X17, X9, X16,LSL #3

  (181) 0x42252c LDADD	X8, X1, [X17]

  (181) 0x422530 LDR	X18, [X0, #24]

  (181) 0x422534 ADD	X30, X9, X18,LSL #3

  (181) 0x422538 LDADD	X8, X1, [X30]

  (181) 0x42253c LDR	X20, [X0, #32]

  (181) 0x422540 ADD	X1, X9, X20,LSL #3

  (181) 0x422544 LDADD	X8, X1, [X1]

  (181) 0x422548 LDR	X21, [X0, #40]

  (181) 0x42254c ADD	X19, X9, X21,LSL #3

  (181) 0x422550 LDADD	X8, X1, [X19]

  (181) 0x422554 LDR	X4, [X0, #48]

  (181) 0x422558 ADD	X3, X9, X4,LSL #3

  (181) 0x42255c LDADD	X8, X1, [X3]

  (181) 0x422560 LDR	X2, [X0, #56]

  (181) 0x422564 ADD	X6, X9, X2,LSL #3

  (181) 0x422568 LDADD	X8, X1, [X6]

  (181) 0x42256c ADD	X0, X0, #64

  (181) 0x422570 CMP	X10, X0

  (181) 0x422574 B.NE	422508

(180) 0x422578 LDP	X19, X20, [SP, #16]

(180) 0x42257c LDR	X21, [SP, #32]

(180) 0x422580 LDP	X29, X30, [SP], #48

(180) 0x422584 RET

(180) 0x422588 ADD	X3, X3, #1

(180) 0x42258c MOVZ	X2, #0

(180) 0x422590 B	422440

0x422594 HINT	#0

0x422598 HINT	#0

0x42259c HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	par_coarsen.c:2132-2136
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2132-2136.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 20.00 to 10.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	19
loop length	76
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50
cycles	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	2.00
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

1% of peak load performance is reached (1.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 422400

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X0, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 40f6a0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f540 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X4, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV X3, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
MSUB X2, X3, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 422588 <hypre_BoomerAMGCoarsenPMIS._omp_fn.2+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Source file and lines	par_coarsen.c:2132-2136
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2132-2136.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	19
loop length	76
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50
cycles	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	2.17	1.83	2.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	2.00
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

1% of peak load performance is reached (1.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 422400

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X0, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 40f6a0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f540 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X4, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV X3, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
MSUB X2, X3, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 422588 <hypre_BoomerAMGCoarsenPMIS._omp_fn.2+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCoarsenPMIS._omp_fn.2–	0.44	0.17
▼Loop 180 - par_coarsen.c:2132-2136 - exec–	0	0
○Loop 181 - par_coarsen.c:2135-2136 - exec	0.44	0.15

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code