OV - exec - Function hypre_BoomerAMGCoarsenPMIS._omp

	Function: hypre_BoomerAMGCoarsenPMIS._omp_fn.3	Module: exec	Source: par_coarsen.c:2139-2142	Coverage: 0.07%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 2139 - 2142

--------------------------------------------------------------------------------

2139: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

2140:    for (i=0; i < num_variables; i++)

2141:    {

2142:      measure_array[i] = measure_array_temp[i];

0x421660 STP	X29, X30, [SP, #976]!

0x421664 ADD	X29, SP, #0

0x421668 STR	X21, [SP, #32]

0x42166c LDR	X21, [X0]

0x421670 STP	X19, X20, [SP, #16]

0x421674 ORR	X20, XZR, X0

0x421678 BL	40f6a0

0x42167c SBFM	X19, X0, #0, #31

0x421680 BL	40f540

0x421684 SDIV	X3, X21, X19

0x421688 SBFM	X1, X0, #0, #31

0x42168c MSUB	X2, X3, X19, X21

0x421690 CMP	X1, X2

0x421694 B.LT	4217f8

(163) 0x421698 MADD	X13, X3, X1, X2

(163) 0x42169c ADD	X11, X3, X13

(163) 0x4216a0 CMP	X13, X11

(163) 0x4216a4 B.GE	4217e8

(163) 0x4216a8 SUB	X4, X11, X13

(163) 0x4216ac LDP	X12, X0, [X20, #8]

(163) 0x4216b0 ANDS	X5, X4, #4224

(163) 0x4216b4 B.EQ	421760

(163) 0x4216b8 CMP	X5, #1

(163) 0x4216bc B.EQ	421748

(163) 0x4216c0 CMP	X5, #2

(163) 0x4216c4 B.EQ	421738

(163) 0x4216c8 CMP	X5, #3

(163) 0x4216cc B.EQ	421728

(163) 0x4216d0 CMP	X5, #4

(163) 0x4216d4 B.EQ	421718

(163) 0x4216d8 CMP	X5, #5

(163) 0x4216dc B.EQ	421708

(163) 0x4216e0 CMP	X5, #6

(163) 0x4216e4 B.EQ	4216f8

(163) 0x4216e8 LDR	D0, [X0, X13,LSL #3]

(163) 0x4216ec SCVTF	D1, D0

(163) 0x4216f0 STR	D1, [X12, X13,LSL #3]

(163) 0x4216f4 ADD	X13, X13, #1

(163) 0x4216f8 LDR	D2, [X0, X13,LSL #3]

(163) 0x4216fc SCVTF	D3, D2

(163) 0x421700 STR	D3, [X12, X13,LSL #3]

(163) 0x421704 ADD	X13, X13, #1

(163) 0x421708 LDR	D4, [X0, X13,LSL #3]

(163) 0x42170c SCVTF	D5, D4

(163) 0x421710 STR	D5, [X12, X13,LSL #3]

(163) 0x421714 ADD	X13, X13, #1

(163) 0x421718 LDR	D6, [X0, X13,LSL #3]

(163) 0x42171c SCVTF	D7, D6

(163) 0x421720 STR	D7, [X12, X13,LSL #3]

(163) 0x421724 ADD	X13, X13, #1

(163) 0x421728 LDR	D16, [X0, X13,LSL #3]

(163) 0x42172c SCVTF	D17, D16

(163) 0x421730 STR	D17, [X12, X13,LSL #3]

(163) 0x421734 ADD	X13, X13, #1

(163) 0x421738 LDR	D18, [X0, X13,LSL #3]

(163) 0x42173c SCVTF	D19, D18

(163) 0x421740 STR	D19, [X12, X13,LSL #3]

(163) 0x421744 ADD	X13, X13, #1

(163) 0x421748 LDR	D20, [X0, X13,LSL #3]

(163) 0x42174c SCVTF	D21, D20

(163) 0x421750 STR	D21, [X12, X13,LSL #3]

(163) 0x421754 ADD	X13, X13, #1

(163) 0x421758 CMP	X11, X13

(163) 0x42175c B.EQ	4217e8

  (164) 0x421760 ADD	X14, X13, #1

  (164) 0x421764 LDR	D22, [X0, X13,LSL #3]

  (164) 0x421768 ADD	X10, X13, #2

  (164) 0x42176c ADD	X9, X13, #3

  (164) 0x421770 ADD	X8, X13, #4

  (164) 0x421774 LDR	D23, [X0, X14,LSL #3]

  (164) 0x421778 ADD	X7, X13, #5

  (164) 0x42177c ADD	X6, X13, #6

  (164) 0x421780 ADD	X15, X13, #7

  (164) 0x421784 LDR	D24, [X0, X10,LSL #3]

  (164) 0x421788 SCVTF	D25, D22

  (164) 0x42178c LDR	D26, [X0, X9,LSL #3]

  (164) 0x421790 SCVTF	D27, D23

  (164) 0x421794 LDR	D28, [X0, X8,LSL #3]

  (164) 0x421798 SCVTF	D29, D24

  (164) 0x42179c LDR	D30, [X0, X7,LSL #3]

  (164) 0x4217a0 SCVTF	D31, D26

  (164) 0x4217a4 STR	D25, [X12, X13,LSL #3]

  (164) 0x4217a8 ADD	X13, X13, #8

  (164) 0x4217ac LDR	D1, [X0, X6,LSL #3]

  (164) 0x4217b0 SCVTF	D3, D28

  (164) 0x4217b4 STR	D27, [X12, X14,LSL #3]

  (164) 0x4217b8 LDR	D0, [X0, X15,LSL #3]

  (164) 0x4217bc SCVTF	D2, D30

  (164) 0x4217c0 STR	D29, [X12, X10,LSL #3]

  (164) 0x4217c4 SCVTF	D4, D1

  (164) 0x4217c8 STR	D31, [X12, X9,LSL #3]

  (164) 0x4217cc SCVTF	D5, D0

  (164) 0x4217d0 STR	D3, [X12, X8,LSL #3]

  (164) 0x4217d4 STR	D2, [X12, X7,LSL #3]

  (164) 0x4217d8 STR	D4, [X12, X6,LSL #3]

  (164) 0x4217dc STR	D5, [X12, X15,LSL #3]

  (164) 0x4217e0 CMP	X11, X13

  (164) 0x4217e4 B.NE	421760

(163) 0x4217e8 LDP	X19, X20, [SP, #16]

(163) 0x4217ec LDR	X21, [SP, #32]

(163) 0x4217f0 LDP	X29, X30, [SP], #48

(163) 0x4217f4 RET

(163) 0x4217f8 ADD	X3, X3, #1

(163) 0x4217fc MOVZ	X2, #0

(163) 0x421800 B	421698

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	par_coarsen.c:2139-2142
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2139-2142.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 20.00 to 10.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 421660

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X21, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40f6a0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40f540 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SDIV X3, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MSUB X2, X3, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP X1, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 4217f8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.3+0x198>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	par_coarsen.c:2139-2142
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2139-2142.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	14
loop length	56
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50
cycles	1.50	1.50	2.50	2.50	2.50	2.50	0.00	0.00	0.00	0.00	1.50	1.50	1.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	1.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 421660

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X21, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40f6a0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 40f540 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SDIV X3, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MSUB X2, X3, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP X1, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 4217f8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.3+0x198>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCoarsenPMIS._omp_fn.3–	0.07	0.03
▼Loop 163 - par_coarsen.c:2139-2142 - exec–	0	0
○Loop 164 - par_coarsen.c:2142-2142 - exec	0.07	0.02

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code