OV - exec - Function hypre_BoomerAMGCoarsenPMIS._omp

	Function: hypre_BoomerAMGCoarsenPMIS._omp_fn.7	Module: exec	Source: par_coarsen.c:2435-2477 [...]	Coverage: 0.38%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 2435 - 2477

--------------------------------------------------------------------------------

2435: #pragma omp parallel for private(ig, i, jS, j) HYPRE_SMP_SCHEDULE

[...]

2446:        if(measure_array[i]<1.) CF_marker[i]= F_PT;

[...]

2453:        if (CF_marker[i] > 0) CF_marker[i] = C_PT;

[...]

2465: 	 for (jS = S_diag_i[i]; jS < S_diag_i[i+1]; jS++)

2466:          {

2467: 	   /* j is the column number, or the local number of the point influencing i */

2468: 	   j = S_diag_j[jS];

2469: 	   if (CF_marker[j] > 0) /* j is a C-point */

2470: 	     CF_marker[i] = F_PT;

2471: 	 }

2472: 	 /* now the external part */

2473: 	 for (jS = S_offd_i[i]; jS < S_offd_i[i+1]; jS++)

2474: 	 {

2475: 	   j = S_offd_j[jS];

2476: 	   if (CF_marker_offd[j] > 0) /* j is a C-point */

2477: 	     CF_marker[i] = F_PT;

0x4214f0 STP	X29, X30, [SP, #976]!

0x4214f4 ADD	X29, SP, #0

0x4214f8 STP	X19, X20, [SP, #16]

0x4214fc ORR	X20, XZR, X0

0x421500 LDR	X0, [X0, #64]

0x421504 STR	X21, [SP, #32]

0x421508 LDR	X21, [X0]

0x42150c BL	40f6a0

0x421510 SBFM	X19, X0, #0, #31

0x421514 BL	40f540

0x421518 SBFM	X1, X0, #0, #31

0x42151c SDIV	X8, X21, X19

0x421520 MSUB	X2, X8, X19, X21

0x421524 CMP	X1, X2

0x421528 B.LT	42164c

0x42152c MADD	X4, X8, X1, X2

0x421530 ADD	X5, X8, X4

0x421534 CMP	X4, X5

0x421538 B.GE	421594

0x42153c LDP	X14, X6, [X20, #48]

0x421540 FMOV	D1, #1.0000000

0x421544 MOVN	X9, #0

0x421548 MOVZ	X15, #1

0x42154c LDP	X17, X12, [X20]

0x421550 ADD	X1, X6, X4,LSL #3

0x421554 LDP	X16, X11, [X20, #16]

0x421558 ADD	X8, X6, X5,LSL #3

0x42155c LDP	X3, X10, [X20, #32]

    (158) 0x421560 LDR	X18, [X1]

    (158) 0x421564 LDR	D0, [X14, X18,LSL #3]

    (158) 0x421568 UBFM	X13, X18, #61, #60

    (158) 0x42156c ADD	X7, X3, X13

    (158) 0x421570 FCMPE	D0, D1

    (158) 0x421574 B.MI	4215a4

    (158) 0x421578 LDR	X30, [X3, X18,LSL #3]

    (158) 0x42157c CMP	X30, #0

    (158) 0x421580 B.LE	4215a8

    (158) 0x421584 STR	X15, [X3, X18,LSL #3]

    (158) 0x421588 ADD	X1, X1, #8

    (158) 0x42158c CMP	X8, X1

    (158) 0x421590 B.NE	421560

(159) 0x421594 LDP	X19, X20, [SP, #16]

(159) 0x421598 LDR	X21, [SP, #32]

(159) 0x42159c LDP	X29, X30, [SP], #48

(159) 0x4215a0 RET

  (156) 0x4215a4 STR	X9, [X3, X18,LSL #3]

    (157) 0x4215a8 ADD	X20, X13, #8

    (157) 0x4215ac LDR	X0, [X17, X18,LSL #3]

    (157) 0x4215b0 ADD	X21, X17, X20

    (157) 0x4215b4 LDR	X4, [X17, X20]

    (157) 0x4215b8 CMP	X0, X4

    (157) 0x4215bc B.GE	4215e4

    (162) 0x4215c0 LDR	X19, [X12, X0,LSL #3]

    (162) 0x4215c4 LDR	X2, [X3, X19,LSL #3]

    (162) 0x4215c8 CMP	X2, #0

    (162) 0x4215cc B.LE	42163c

    (162) 0x4215d0 STR	X9, [X7]

    (162) 0x4215d4 ADD	X0, X0, #1

    (162) 0x4215d8 LDR	X4, [X21]

    (162) 0x4215dc CMP	X0, X4

    (162) 0x4215e0 B.LT	4215c0

  (156) 0x4215e4 LDR	X13, [X16, X18,LSL #3]

  (156) 0x4215e8 ADD	X5, X16, X20

  (156) 0x4215ec LDR	X30, [X16, X20]

  (156) 0x4215f0 CMP	X13, X30

  (156) 0x4215f4 B.GE	421588

    (160) 0x4215f8 LDR	X6, [X11, X13,LSL #3]

    (160) 0x4215fc LDR	X18, [X10, X6,LSL #3]

    (160) 0x421600 CMP	X18, #0

    (160) 0x421604 B.LE	42162c

    (161) 0x421608 STR	X9, [X7]

    (161) 0x42160c ADD	X13, X13, #1

    (161) 0x421610 LDR	X30, [X5]

    (161) 0x421614 CMP	X13, X30

    (161) 0x421618 B.GE	421588

    (161) 0x42161c LDR	X6, [X11, X13,LSL #3]

    (161) 0x421620 LDR	X18, [X10, X6,LSL #3]

    (161) 0x421624 CMP	X18, #0

    (161) 0x421628 B.GT	421608

    (160) 0x42162c ADD	X13, X13, #1

    (160) 0x421630 CMP	X13, X30

    (160) 0x421634 B.LT	4215f8

  (156) 0x421638 B	421588

    (162) 0x42163c ADD	X0, X0, #1

    (162) 0x421640 CMP	X0, X4

    (162) 0x421644 B.LT	4215c0

  (156) 0x421648 B	4215e4

0x42164c ADD	X8, X8, #1

0x421650 MOVZ	X2, #0

0x421654 B	42152c

0x421658 HINT	#0

0x42165c HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	par_coarsen.c:2435-2477
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2435,2446,2453,2465-2477.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 20.00 to 10.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 80 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	33
loop length	132
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.75	4.75	4.75	4.75	0.25	0.25	0.25	0.25	3.17	2.83	3.00	1.50	1.50
cycles	2.50	2.50	4.75	4.75	4.75	4.75	0.25	0.25	0.25	0.25	3.17	2.83	3.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	3.88
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

4% of peak load performance is reached (4.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4214f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 40f6a0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f540 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV X8, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
MSUB X2, X8, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X1, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42164c <hypre_BoomerAMGCoarsenPMIS._omp_fn.7+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X4, X8, X1, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X5, X8, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X4, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 421594 <hypre_BoomerAMGCoarsenPMIS._omp_fn.7+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X14, X6, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
FMOV D1, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X17, X12, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X1, X6, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X16, X11, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X8, X6, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X3, X10, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42152c <hypre_BoomerAMGCoarsenPMIS._omp_fn.7+0x3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Source file and lines	par_coarsen.c:2435-2477
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2435,2446,2453,2465-2477.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 80 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	33
loop length	132
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.75	4.75	4.75	4.75	0.25	0.25	0.25	0.25	3.17	2.83	3.00	1.50	1.50
cycles	2.50	2.50	4.75	4.75	4.75	4.75	0.25	0.25	0.25	0.25	3.17	2.83	3.00	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	3.88
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

4% of peak load performance is reached (4.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4214f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 40f6a0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f540 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV X8, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
MSUB X2, X8, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X1, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42164c <hypre_BoomerAMGCoarsenPMIS._omp_fn.7+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X4, X8, X1, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X5, X8, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X4, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 421594 <hypre_BoomerAMGCoarsenPMIS._omp_fn.7+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X14, X6, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
FMOV D1, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X17, X12, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X1, X6, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X16, X11, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X8, X6, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X3, X10, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42152c <hypre_BoomerAMGCoarsenPMIS._omp_fn.7+0x3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCoarsenPMIS._omp_fn.7–	0.38	0.14
▼Loop 159 - par_coarsen.c:2435-2477 - exec–	0	0
▼Loop 156 - par_coarsen.c:2446-2477 - exec–	0.01	0.01
○Loop 162 - par_coarsen.c:2465-2470 - exec	0.34	0.11
○Loop 158 - par_coarsen.c:2446-2453 - exec	0.03	0.01
○Loop 160 - par_coarsen.c:2473-2476 - exec	0	0
○Loop 157 - par_coarsen.c:2465-2465 - exec	0	0
○Loop 161 - par_coarsen.c:2473-2477 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

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Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code