OV - exec - Function hypre_BoomerAMGCoarsenPMIS._omp

	Function: hypre_BoomerAMGCoarsenPMIS._omp_fn.4	Module: exec	Source: par_coarsen.c:2327-2334	Coverage: 0.02%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 2327 - 2334

--------------------------------------------------------------------------------

2327: #pragma omp parallel for private(ig, i) HYPRE_SMP_SCHEDULE

2328: #endif

2329:         for (ig = 0; ig < graph_size; ig++)

2330:         {

2331:            i = graph_array[ig];

2332:            if (measure_array[i] > 1)

2333:            {

2334:               CF_marker[i] = 1;

0x4211d0 STP	X29, X30, [SP, #976]!

0x4211d4 ADD	X29, SP, #0

0x4211d8 STP	X19, X20, [SP, #16]

0x4211dc ORR	X20, XZR, X0

0x4211e0 LDR	X0, [X0, #24]

0x4211e4 STR	X21, [SP, #32]

0x4211e8 LDR	X21, [X0]

0x4211ec BL	40f6a0

0x4211f0 SBFM	X19, X0, #0, #31

0x4211f4 BL	40f540

0x4211f8 SBFM	X1, X0, #0, #31

0x4211fc SDIV	X3, X21, X19

0x421200 MSUB	X2, X3, X19, X21

0x421204 CMP	X1, X2

0x421208 B.LT	4214b8

0x42120c MADD	X7, X3, X1, X2

0x421210 ADD	X8, X3, X7

0x421214 CMP	X7, X8

0x421218 B.GE	4213bc

0x42121c LDR	X6, [X20, #16]

0x421220 MOVZ	X5, #1

0x421224 FMOV	D0, #1.0000000

0x421228 LDP	X4, X9, [X20]

0x42122c ADD	X0, X6, X7,LSL #3

0x421230 ADD	X10, X6, X8,LSL #3

0x421234 SUB	X11, X10, X0

0x421238 SUB	X12, X11, #8

0x42123c UBFM	X13, X12, #3, #63

0x421240 ADD	X14, X13, X5

0x421244 ANDS	X15, X14, #4224

0x421248 B.EQ	42132c

0x42124c CMP	X15, X5

0x421250 B.EQ	42130c

0x421254 CMP	X15, #2

0x421258 B.EQ	4212f4

0x42125c CMP	X15, #3

0x421260 B.EQ	4212dc

0x421264 CMP	X15, #4

0x421268 B.EQ	4212c4

0x42126c CMP	X15, #5

0x421270 B.EQ	4212ac

0x421274 CMP	X15, #6

0x421278 B.EQ	421294

0x42127c LDR	X16, [X0]

0x421280 UBFM	X17, X16, #61, #60

0x421284 LDR	D1, [X9, X17]

0x421288 FCMPE	D1, D0

0x42128c B.GT	4214e8

0x421290 ADD	X0, X0, #8

0x421294 LDR	X18, [X0]

0x421298 UBFM	X30, X18, #61, #60

0x42129c LDR	D2, [X9, X30]

0x4212a0 FCMPE	D2, D0

0x4212a4 B.GT	4214d4

0x4212a8 ADD	X0, X0, #8

0x4212ac LDR	X20, [X0]

0x4212b0 UBFM	X21, X20, #61, #60

0x4212b4 LDR	D3, [X9, X21]

0x4212b8 FCMPE	D3, D0

0x4212bc B.GT	4214dc

0x4212c0 ADD	X0, X0, #8

0x4212c4 LDR	X19, [X0]

0x4212c8 UBFM	X1, X19, #61, #60

0x4212cc LDR	D4, [X9, X1]

0x4212d0 FCMPE	D4, D0

0x4212d4 B.GT	4214cc

0x4212d8 ADD	X0, X0, #8

0x4212dc LDR	X3, [X0]

0x4212e0 UBFM	X2, X3, #61, #60

0x4212e4 LDR	D5, [X9, X2]

0x4212e8 FCMPE	D5, D0

0x4212ec B.GT	4214c4

0x4212f0 ADD	X0, X0, #8

0x4212f4 LDR	X7, [X0]

0x4212f8 UBFM	X8, X7, #61, #60

0x4212fc LDR	D6, [X9, X8]

0x421300 FCMPE	D6, D0

0x421304 B.GT	42148c

0x421308 ADD	X0, X0, #8

0x42130c LDR	X6, [X0]

0x421310 UBFM	X11, X6, #61, #60

0x421314 LDR	D7, [X9, X11]

0x421318 FCMPE	D7, D0

0x42131c B.GT	421494

0x421320 ADD	X0, X0, #8

0x421324 CMP	X10, X0

0x421328 B.EQ	4213bc

    (154) 0x42132c LDR	X12, [X0]

    (154) 0x421330 LDR	D16, [X9, X12,LSL #3]

    (154) 0x421334 FCMPE	D16, D0

    (154) 0x421338 B.GT	421470

    (154) 0x42133c LDR	X13, [X0, #8]

    (154) 0x421340 ADD	X0, X0, #8

    (154) 0x421344 LDR	D17, [X9, X13,LSL #3]

    (154) 0x421348 FCMPE	D17, D0

    (154) 0x42134c B.GT	421458

    (154) 0x421350 LDR	X14, [X0, #8]

    (154) 0x421354 LDR	D18, [X9, X14,LSL #3]

    (154) 0x421358 FCMPE	D18, D0

    (154) 0x42135c B.GT	421440

    (154) 0x421360 LDR	X15, [X0, #16]

    (154) 0x421364 LDR	D19, [X9, X15,LSL #3]

    (154) 0x421368 FCMPE	D19, D0

    (154) 0x42136c B.GT	421428

    (154) 0x421370 LDR	X16, [X0, #24]

    (154) 0x421374 LDR	D20, [X9, X16,LSL #3]

    (154) 0x421378 FCMPE	D20, D0

    (154) 0x42137c B.GT	421410

    (154) 0x421380 LDR	X17, [X0, #32]

    (154) 0x421384 LDR	D21, [X9, X17,LSL #3]

    (154) 0x421388 FCMPE	D21, D0

    (154) 0x42138c B.GT	4213f8

    (154) 0x421390 LDR	X18, [X0, #40]

    (154) 0x421394 LDR	D22, [X9, X18,LSL #3]

    (154) 0x421398 FCMPE	D22, D0

    (154) 0x42139c B.GT	4213e0

    (154) 0x4213a0 LDR	X30, [X0, #48]

    (154) 0x4213a4 LDR	D23, [X9, X30,LSL #3]

    (154) 0x4213a8 FCMPE	D23, D0

    (154) 0x4213ac B.GT	4213cc

    (154) 0x4213b0 ADD	X0, X0, #56

    (154) 0x4213b4 CMP	X10, X0

    (154) 0x4213b8 B.NE	42132c

(155) 0x4213bc LDP	X19, X20, [SP, #16]

(155) 0x4213c0 LDR	X21, [SP, #32]

(155) 0x4213c4 LDP	X29, X30, [SP], #48

(155) 0x4213c8 RET

  (153) 0x4213cc ADD	X0, X0, #56

  (153) 0x4213d0 STR	X5, [X4, X30,LSL #3]

  (153) 0x4213d4 CMP	X10, X0

  (153) 0x4213d8 B.NE	42132c

(155) 0x4213dc B	4213bc

    (154) 0x4213e0 STR	X5, [X4, X18,LSL #3]

    (154) 0x4213e4 LDR	X30, [X0, #48]

    (154) 0x4213e8 LDR	D23, [X9, X30,LSL #3]

    (154) 0x4213ec FCMPE	D23, D0

    (154) 0x4213f0 B.GT	4213cc

    (154) 0x4213f4 B	4213b0

    (154) 0x4213f8 STR	X5, [X4, X17,LSL #3]

    (154) 0x4213fc LDR	X18, [X0, #40]

    (154) 0x421400 LDR	D22, [X9, X18,LSL #3]

    (154) 0x421404 FCMPE	D22, D0

    (154) 0x421408 B.GT	4213e0

    (154) 0x42140c B	4213a0

    (154) 0x421410 STR	X5, [X4, X16,LSL #3]

    (154) 0x421414 LDR	X17, [X0, #32]

    (154) 0x421418 LDR	D21, [X9, X17,LSL #3]

    (154) 0x42141c FCMPE	D21, D0

    (154) 0x421420 B.GT	4213f8

    (154) 0x421424 B	421390

    (154) 0x421428 STR	X5, [X4, X15,LSL #3]

    (154) 0x42142c LDR	X16, [X0, #24]

    (154) 0x421430 LDR	D20, [X9, X16,LSL #3]

    (154) 0x421434 FCMPE	D20, D0

    (154) 0x421438 B.GT	421410

    (154) 0x42143c B	421380

    (154) 0x421440 STR	X5, [X4, X14,LSL #3]

    (154) 0x421444 LDR	X15, [X0, #16]

    (154) 0x421448 LDR	D19, [X9, X15,LSL #3]

    (154) 0x42144c FCMPE	D19, D0

    (154) 0x421450 B.GT	421428

    (154) 0x421454 B	421370

    (154) 0x421458 STR	X5, [X4, X13,LSL #3]

    (154) 0x42145c LDR	X14, [X0, #8]

    (154) 0x421460 LDR	D18, [X9, X14,LSL #3]

    (154) 0x421464 FCMPE	D18, D0

    (154) 0x421468 B.GT	421440

    (154) 0x42146c B	421360

    (154) 0x421470 STR	X5, [X4, X12,LSL #3]

    (154) 0x421474 ADD	X0, X0, #8

    (154) 0x421478 LDR	X13, [X0]

    (154) 0x42147c LDR	D17, [X9, X13,LSL #3]

    (154) 0x421480 FCMPE	D17, D0

    (154) 0x421484 B.GT	421458

    (154) 0x421488 B	421350

0x42148c STR	X5, [X4, X8]

0x421490 B	421308

0x421494 ADD	X0, X0, #8

0x421498 STR	X5, [X4, X11]

0x42149c CMP	X10, X0

0x4214a0 B.EQ	4213bc

0x4214a4 LDR	X12, [X0]

0x4214a8 LDR	D16, [X9, X12,LSL #3]

0x4214ac FCMPE	D16, D0

0x4214b0 B.GT	421470

0x4214b4 B	42133c

0x4214b8 ADD	X3, X3, #1

0x4214bc MOVZ	X2, #0

0x4214c0 B	42120c

0x4214c4 STR	X5, [X4, X2]

0x4214c8 B	4212f0

0x4214cc STR	X5, [X4, X1]

0x4214d0 B	4212d8

0x4214d4 STR	X5, [X4, X30]

0x4214d8 B	4212a8

0x4214dc ADD	X0, X0, #8

0x4214e0 STR	X5, [X4, X21]

0x4214e4 B	4212c4

0x4214e8 STR	X5, [X4, X17]

0x4214ec B	421290

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	par_coarsen.c:2327-2334
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2327-2334.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 20.00 to 3.00 cycles (6.67x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 20.00 to 10.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 168 bytes. The binary function is storing 96 bytes.

General properties

nb instructions	112
loop length	448
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

14.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	14.50	14.50	11.75	11.75	11.75	11.75	8.00	0.50	0.25	0.25	10.00	10.00	10.00	5.00	5.00
cycles	14.50	14.50	11.75	11.75	11.75	11.75	8.00	0.50	0.25	0.25	10.00	10.00	10.00	5.00	5.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	14.00
Overall L1	14.50-20.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

8% of peak load performance is reached (8.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (4.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4211d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 40f6a0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f540 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV X3, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
MSUB X2, X3, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X1, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4214b8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x2e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X7, X3, X1, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X8, X3, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X7, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4213bc <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X6, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D0, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDP X4, X9, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X0, X6, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X6, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X11, X10, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X12, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X13, X12, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X13, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X15, X14, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42132c <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42130c <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4212f4 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4212dc <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4212c4 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4212ac <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0xdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 421294 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0xc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X16, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X17, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D1, [X9, X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D1, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.GT 4214e8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x318>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X18, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X30, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D2, [X9, X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D2, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.GT 4214d4 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X20, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X21, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D3, [X9, X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D3, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.GT 4214dc <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x30c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X1, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D4, [X9, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D4, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.GT 4214cc <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x2fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X3, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X2, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D5, [X9, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D5, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.GT 4214c4 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x2f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X7, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X8, X7, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D6, [X9, X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D6, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.GT 42148c <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X6, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X11, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D7, [X9, X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D7, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.GT 421494 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x2c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X10, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4213bc <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X5, [X4, X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 421308 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X5, [X4, X11]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X10, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4213bc <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X12, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D16, [X9, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D16, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.GT 421470 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 42133c <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x16c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42120c <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X5, [X4, X2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4212f0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X5, [X4, X1]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4212d8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X5, [X4, X30]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4212a8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X5, [X4, X21]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4212c4 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X5, [X4, X17]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 421290 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0xc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	par_coarsen.c:2327-2334
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2327-2334.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 20.00 to 3.00 cycles (6.67x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 168 bytes. The binary function is storing 96 bytes.

General properties

nb instructions	112
loop length	448
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

14.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	14.50	14.50	11.75	11.75	11.75	11.75	8.00	0.50	0.25	0.25	10.00	10.00	10.00	5.00	5.00
cycles	14.50	14.50	11.75	11.75	11.75	11.75	8.00	0.50	0.25	0.25	10.00	10.00	10.00	5.00	5.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	14.00
Overall L1	14.50-20.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

8% of peak load performance is reached (8.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (4.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4211d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 40f6a0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f540 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X1, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV X3, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
MSUB X2, X3, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X1, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4214b8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x2e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X7, X3, X1, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X8, X3, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X7, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4213bc <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X6, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D0, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDP X4, X9, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X0, X6, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X6, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X11, X10, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X12, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X13, X12, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X13, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X15, X14, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42132c <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42130c <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4212f4 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4212dc <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4212c4 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4212ac <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0xdc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X15, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 421294 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0xc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X16, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X17, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D1, [X9, X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D1, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.GT 4214e8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x318>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X18, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X30, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D2, [X9, X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D2, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.GT 4214d4 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X20, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X21, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D3, [X9, X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D3, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.GT 4214dc <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x30c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X1, X19, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D4, [X9, X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D4, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.GT 4214cc <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x2fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X3, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X2, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D5, [X9, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D5, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.GT 4214c4 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x2f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X7, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X8, X7, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D6, [X9, X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D6, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.GT 42148c <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X6, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X11, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D7, [X9, X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D7, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.GT 421494 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x2c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X10, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4213bc <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X5, [X4, X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 421308 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x138>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X5, [X4, X11]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X10, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4213bc <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X12, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D16, [X9, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMPE D16, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.GT 421470 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 42133c <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x16c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42120c <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X5, [X4, X2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4212f0 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X5, [X4, X1]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4212d8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X5, [X4, X30]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4212a8 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X5, [X4, X21]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 4212c4 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X5, [X4, X17]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 421290 <hypre_BoomerAMGCoarsenPMIS._omp_fn.4+0xc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCoarsenPMIS._omp_fn.4–	0.02	0.01
▼Loop 155 - par_coarsen.c:2327-2334 - exec–	0	0
▼Loop 153 - par_coarsen.c:2332-2334 - exec–	0	0.01
○Loop 154 - par_coarsen.c:2332-2334 - exec	0.02	0.01

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code