OV - exec - Function hypre_BoomerAMGCoarsenPMIS._omp

	Function: hypre_BoomerAMGCoarsenPMIS._omp_fn.6	Module: exec	Source: par_coarsen.c:2354-2381	Coverage: 0.66%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 2354 - 2381

--------------------------------------------------------------------------------

2354: #pragma omp parallel for private(ig, i, jS, j, jj) HYPRE_SMP_SCHEDULE

2355: #endif

2356:         for (ig = 0; ig < graph_size; ig++)

2357:         {

2358:            i = graph_array[ig];

2359:            if (measure_array[i] > 1)

2360:            {

2361:               for (jS = S_diag_i[i]; jS < S_diag_i[i+1]; jS++)

2362:               {

2363:                  j = S_diag_j[jS];

2364:                  if (measure_array[j] > 1)

2365:                  {

2366:                     if (measure_array[i] > measure_array[j])

2367:                        CF_marker[j] = 0;

2368:                     else if (measure_array[j] > measure_array[i])

2369:                        CF_marker[i] = 0;

2370:                  }

2371:               } /* for each local neighbor j of i */

2372:               for (jS = S_offd_i[i]; jS < S_offd_i[i+1]; jS++)

2373:               {

2374:                  jj = S_offd_j[jS];

2375:                  j = num_variables+jj;

2376:                  if (measure_array[j] > 1)

2377:                  {

2378:                     if (measure_array[i] > measure_array[j])

2379:                        CF_marker_offd[jj] = 0;

2380:                     else if (measure_array[j] > measure_array[i])

2381:                        CF_marker[i] = 0;

0x420d00 STP	X29, X30, [SP, #976]!

0x420d04 ADD	X29, SP, #0

0x420d08 STP	X19, X20, [SP, #16]

0x420d0c ORR	X19, XZR, X0

0x420d10 LDR	X0, [X0, #72]

0x420d14 STR	X21, [SP, #32]

0x420d18 LDR	X21, [X0]

0x420d1c BL	40f6a0

0x420d20 SBFM	X20, X0, #0, #31

0x420d24 BL	40f540

0x420d28 SBFM	X3, X0, #0, #31

0x420d2c SDIV	X9, X21, X20

0x420d30 MSUB	X1, X9, X20, X21

0x420d34 CMP	X3, X1

0x420d38 B.LT	420e64

0x420d3c MADD	X2, X9, X3, X1

0x420d40 ADD	X4, X9, X2

0x420d44 CMP	X2, X4

0x420d48 B.GE	420d8c

0x420d4c LDR	X5, [X19, #64]

0x420d50 FMOV	D1, #1.0000000

0x420d54 LDP	X15, X8, [X19]

0x420d58 LDP	X14, X7, [X19, #16]

0x420d5c ADD	X3, X5, X2,LSL #3

0x420d60 ADD	X18, X5, X4,LSL #3

0x420d64 LDP	X6, X11, [X19, #32]

0x420d68 LDP	X16, X17, [X19, #48]

    (146) 0x420d6c LDR	X30, [X3]

    (146) 0x420d70 LDR	D2, [X17, X30,LSL #3]

    (146) 0x420d74 UBFM	X10, X30, #61, #60

    (146) 0x420d78 FCMPE	D2, D1

    (146) 0x420d7c B.GT	420d9c

    (146) 0x420d80 ADD	X3, X3, #8

    (146) 0x420d84 CMP	X18, X3

    (146) 0x420d88 B.NE	420d6c

(147) 0x420d8c LDP	X19, X20, [SP, #16]

(147) 0x420d90 LDR	X21, [SP, #32]

(147) 0x420d94 LDP	X29, X30, [SP], #48

(147) 0x420d98 RET

  (145) 0x420d9c ADD	X12, X10, #8

  (145) 0x420da0 LDR	X0, [X15, X30,LSL #3]

  (145) 0x420da4 ADD	X13, X15, X12

  (145) 0x420da8 LDR	X21, [X15, X12]

  (145) 0x420dac CMP	X0, X21

  (145) 0x420db0 B.GE	420ddc

  (145) 0x420db4 HINT	#0

  (145) 0x420db8 HINT	#0

  (145) 0x420dbc HINT	#0

    (149) 0x420dc0 LDR	X19, [X8, X0,LSL #3]

    (149) 0x420dc4 LDR	D0, [X17, X19,LSL #3]

    (149) 0x420dc8 FCMPE	D0, D1

    (149) 0x420dcc B.GT	420e14

    (149) 0x420dd0 ADD	X0, X0, #1

    (149) 0x420dd4 CMP	X0, X21

    (149) 0x420dd8 B.LT	420dc0

  (145) 0x420ddc LDR	X4, [X14, X30,LSL #3]

  (145) 0x420de0 ADD	X20, X14, X12

  (145) 0x420de4 LDR	X2, [X14, X12]

  (145) 0x420de8 CMP	X4, X2

  (145) 0x420dec B.GE	420d80

    (148) 0x420df0 LDR	X9, [X7, X4,LSL #3]

    (148) 0x420df4 ADD	X1, X6, X9

    (148) 0x420df8 LDR	D3, [X17, X1,LSL #3]

    (148) 0x420dfc FCMPE	D3, D1

    (148) 0x420e00 B.GT	420e30

    (148) 0x420e04 ADD	X4, X4, #1

    (148) 0x420e08 CMP	X4, X2

    (148) 0x420e0c B.LT	420df0

  (145) 0x420e10 B	420d80

    (149) 0x420e14 FCMPE	D2, D0

    (149) 0x420e18 B.GT	420e58

    (149) 0x420e1c B.MI	420e24

    (149) 0x420e20 B	420dd0

    (149) 0x420e24 STR	XZR, [X11, X10]

    (149) 0x420e28 LDR	X21, [X13]

    (149) 0x420e2c B	420dd0

    (148) 0x420e30 FCMPE	D2, D3

    (148) 0x420e34 B.GT	420e4c

    (148) 0x420e38 B.MI	420e40

    (148) 0x420e3c B	420e04

    (148) 0x420e40 STR	XZR, [X11, X10]

    (148) 0x420e44 LDR	X2, [X20]

    (148) 0x420e48 B	420e04

    (148) 0x420e4c STR	XZR, [X16, X9,LSL #3]

    (148) 0x420e50 LDR	X2, [X20]

    (148) 0x420e54 B	420e04

    (149) 0x420e58 STR	XZR, [X11, X19,LSL #3]

    (149) 0x420e5c LDR	X21, [X13]

    (149) 0x420e60 B	420dd0

0x420e64 ADD	X9, X9, #1

0x420e68 MOVZ	X1, #0

0x420e6c B	420d3c

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	par_coarsen.c:2354-2381
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2354-2381.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 20.00 to 10.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 88 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.25	4.25	4.25	4.25	0.25	0.25	0.25	0.25	3.50	3.17	3.33	1.50	1.50
cycles	2.50	2.50	4.25	4.25	4.25	4.25	0.25	0.25	0.25	0.25	3.50	3.17	3.33	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	3.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

4% of peak load performance is reached (4.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 420d00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 40f6a0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X20, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f540 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X3, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV X9, X21, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
MSUB X1, X9, X20, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X3, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 420e64 <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X2, X9, X3, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X4, X9, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X2, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 420d8c <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0x8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X5, [X19, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FMOV D1, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDP X15, X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X14, X7, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X3, X5, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X5, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X6, X11, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X16, X17, [X19, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 420d3c <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0x3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	par_coarsen.c:2354-2381
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2354-2381.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 1.00 cycles (20.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 88 bytes. The binary function is storing 40 bytes.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	4.25	4.25	4.25	4.25	0.25	0.25	0.25	0.25	3.50	3.17	3.33	1.50	1.50
cycles	2.50	2.50	4.25	4.25	4.25	4.25	0.25	0.25	0.25	0.25	3.50	3.17	3.33	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	3.75
Overall L1	5.00-20.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

4% of peak load performance is reached (4.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 420d00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X21, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 40f6a0 <@plt_start@+0x4b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X20, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f540 <@plt_start@+0x350>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X3, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV X9, X21, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
MSUB X1, X9, X20, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X3, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 420e64 <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD X2, X9, X3, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X4, X9, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X2, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 420d8c <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0x8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X5, [X19, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FMOV D1, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDP X15, X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X14, X7, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X3, X5, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X5, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X6, X11, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X16, X17, [X19, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 420d3c <hypre_BoomerAMGCoarsenPMIS._omp_fn.6+0x3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCoarsenPMIS._omp_fn.6–	0.66	0.25
▼Loop 147 - par_coarsen.c:2354-2381 - exec–	0	0
▼Loop 145 - par_coarsen.c:2359-2381 - exec–	0.03	0.01
○Loop 149 - par_coarsen.c:2361-2369 - exec	0.63	0.21
○Loop 146 - par_coarsen.c:2359-2359 - exec	0.01	0.01
○Loop 148 - par_coarsen.c:2372-2381 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code