OV - exec - Function hypre

	Function: hypre_Rand	Module: exec	Source: random.c:76-116 [...]	Coverage: 0.02%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/utilities/random.c: 76 - 116

--------------------------------------------------------------------------------

76:    high = Seed / q;

77:    low = Seed % q;

78:    test = a * low - r * high;

[...]

85:       Seed = test + m;

[...]

115:    return ((HYPRE_Real)(hypre_RandI()) / m);

116: }

0x5194c4 ADRP	X5,

0x5194c8 MOVZ	X0, #64377

0x5194cc LDR	X4, [X5, #768]

0x5194d0 MOVK	X0, #8163

0x5194d4 MOVZ	X1, #62237

0x5194d8 MOVK	X0, #1455

0x5194dc MOVK	X1, #1

0x5194e0 MOVK	X0, #16807

0x5194e4 MOVN	X7, #2835

0x5194e8 ORR	X3, XZR, #5738

0x5194ec MOVZ	X6, #16807

0x5194f0 MOVK	X3, #16863

0x5194f4 ORR	X2, XZR, #6016

0x5194f8 SMULH	X8, X4, X0

0x5194fc FMOV	D0, X3

0x519500 SBFM	X9, X8, #15, #63

0x519504 SUB	X10, X9, X4,ASR #63

0x519508 MSUB	X11, X10, X1, X4

0x51950c MADD	X12, X10, X7, XZR

0x519510 MADD	X13, X11, X6, X12

0x519514 CMP	X13, #0

0x519518 ADD	X14, X13, X2

0x51951c CSEL	X15, X14, X13, #13

0x519520 SCVTF	D1, X15

0x519524 STR	X15, [X5, #768]

0x519528 FDIV	D0, D1, D0

0x51952c RET

0x519530 HINT	#0

0x519534 HINT	#0

0x519538 HINT	#0

0x51953c HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	random.c:76-116
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/utilities/random.c:76-78,85,115-116.

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 5.50 to 1.75 cycles (3.15x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Conversion instructions

Detected expensive conversion instructions.

Details

SCVTF: 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: divide

The binary function is loading 8 bytes. The binary function is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	5.50	5.50	5.50	5.50	0.50	0.50	0.50	0.50	0.83	0.50	0.67	0.50	0.50
cycles	0.50	0.50	5.50	5.50	5.50	5.50	0.50	0.50	0.50	0.50	0.83	0.50	0.67	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.75-3.50

Cycles summary

Front-end	3.38
Overall L1	5.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.50 cycles. At this rate:

1% of peak load performance is reached (1.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.45 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 5194c4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADRP X5, <5504c4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X0, #64377	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X4, [X5, #768]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVK X0, #8163	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X1, #62237	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVK X0, #1455	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVK X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVK X0, #16807	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X7, #2835	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X3, XZR, #5738	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X6, #16807	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVK X3, #16863	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, #6016	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SMULH X8, X4, X0	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	3	0.50
FMOV D0, X3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
SBFM X9, X8, #15, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X10, X9, X4,ASR #63	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
MSUB X11, X10, X1, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X12, X10, X7, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X13, X11, X6, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ADD X14, X13, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X15, X14, X13, #13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF D1, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
STR X15, [X5, #768]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
FDIV D0, D1, D0	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0

Source file and lines	random.c:76-116
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/utilities/random.c:76-78,85,115-116.

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Conversion instructions

Detected expensive conversion instructions.

Details

SCVTF: 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: divide

The binary function is loading 8 bytes. The binary function is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.06 FP operations per loaded or stored byte.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	5.50	5.50	5.50	5.50	0.50	0.50	0.50	0.50	0.83	0.50	0.67	0.50	0.50
cycles	0.50	0.50	5.50	5.50	5.50	5.50	0.50	0.50	0.50	0.50	0.83	0.50	0.67	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.75-3.50

Cycles summary

Front-end	3.38
Overall L1	5.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.50 cycles. At this rate:

1% of peak load performance is reached (1.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.45 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 5194c4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADRP X5, <5504c4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X0, #64377	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X4, [X5, #768]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVK X0, #8163	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X1, #62237	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVK X0, #1455	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVK X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVK X0, #16807	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X7, #2835	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X3, XZR, #5738	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X6, #16807	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVK X3, #16863	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, #6016	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SMULH X8, X4, X0	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	3	0.50
FMOV D0, X3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
SBFM X9, X8, #15, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X10, X9, X4,ASR #63	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
MSUB X11, X10, X1, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X12, X10, X7, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X13, X11, X6, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ADD X14, X13, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X15, X14, X13, #13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SCVTF D1, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1
STR X15, [X5, #768]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
FDIV D0, D1, D0	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
○hypre_Rand	0.02	0.01

Report Configuration

Vectorization

Details

Workaround

Conversion instructions

Details

Workaround

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Conversion instructions

Details

Workaround

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code