OV - exec - Function main

	Function: main	Module: exec	Source: amg.c:58-599 [...]	Coverage: 0.01%

/usr/include/stdlib.h: 364 - 364

--------------------------------------------------------------------------------

364:   return (int) strtol (__nptr, (char **) NULL, 10);

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/test/amg.c: 58 - 599

--------------------------------------------------------------------------------

58: {

[...]

76:    HYPRE_Int 	       cum_num_its=0;

[...]

91:    HYPRE_Solver        pcg_precond=NULL, pcg_precond_gotten;

[...]

121:    HYPRE_Real   cum_nnz_AP = 0;

[...]

144:    hypre_MPI_Init(&argc, &argv);

145:

146:    hypre_MPI_Comm_rank(hypre_MPI_COMM_WORLD, &myid );

[...]

153:    build_rhs_arg_index = argc;

[...]

169:    arg_index = 1;

170:

171:    while ( (arg_index < argc) && (!print_usage) )

172:    {

173:       if ( strcmp(argv[arg_index], "-help") == 0 )

174:       {

175:          print_usage = 1;

176:       }

177:       else

178:       {

179:          arg_index++;

[...]

188:    while (arg_index < argc)

189:    {

190:       if ( strcmp(argv[arg_index], "-problem") == 0 )

191:       {

192:          arg_index++;

193:          problem_id = atoi(argv[arg_index++]);

194:          if (problem_id == 2)

195: 	 {

196: 	    solver_id = 3;

197: 	 }

198:

199:       }

200:       else if ( strcmp(argv[arg_index], "-printstats") == 0 )

201:       {

202:          arg_index++;

203:          ioutdat  = 1;

204:          poutdat  = 1;

205:          print_stats  = 1;

206:       }

207:       else if ( strcmp(argv[arg_index], "-printallstats") == 0 )

208:       {

209:          arg_index++;

210:          ioutdat  = 3;

211:          poutdat  = 1;

212:          print_stats  = 1;

213:       }

214:       else if ( strcmp(argv[arg_index], "-print") == 0 )

215:       {

216:          arg_index++;

217:          print_system = 1;

218:       }

219:       else if ( strcmp(argv[arg_index], "-keepT") == 0 )

220:       {

221:          arg_index++;

[...]

235:    if ( (print_usage) && (myid == 0) )

236:    {

237:       hypre_printf("\n");

238:       hypre_printf("Usage: %s [<options>]\n", argv[0]);

239:       hypre_printf("\n");

240:       hypre_printf("  -problem <ID>: problem ID\n");

241:       hypre_printf("       1 = solves 1 large problem with AMG-PCG (default) \n");

242:       hypre_printf("       2 = simulates a time-dependent loop with AMG-GMRES\n");

243:       hypre_printf("\n");

244:       hypre_printf("  -n <nx> <ny> <nz>: problem size per MPI process (default: nx=ny=nz=10)\n");

245:       hypre_printf("\n");

246:       hypre_printf("  -P <px> <py> <pz>: processor topology (default: px=py=pz=1)\n");

247:       hypre_printf("\n");

248:       hypre_printf("  -print       : prints the system\n");

249:       hypre_printf("  -printstats  : prints preconditioning and convergence stats\n");

250:       hypre_printf("  -printallstats  : prints preconditioning and convergence stats\n");

251:       hypre_printf("                    including residual norms for each iteration\n");

252:       hypre_printf("\n");

253:       exit(1);

[...]

260:    if (myid == 0)

261:    {

262:       hypre_printf("Running with these driver parameters:\n");

263:       hypre_printf("  solver ID    = %d\n\n", solver_id);

[...]

270:    time_index = hypre_InitializeTiming("Spatial Operator");

271:    hypre_BeginTiming(time_index);

272:

273:    BuildIJLaplacian27pt(argc, argv, &system_size, &ij_A);

274:    HYPRE_IJMatrixGetObject(ij_A, &object);

275:    parcsr_A = (HYPRE_ParCSRMatrix) object;

276:

277:

278:    hypre_EndTiming(time_index);

279:    hypre_PrintTiming("Generate Matrix", &wall_time, hypre_MPI_COMM_WORLD);

280:    hypre_FinalizeTiming(time_index);

281:    hypre_ClearTiming();

[...]

287:    time_index = hypre_InitializeTiming("RHS and Initial Guess");

288:    hypre_BeginTiming(time_index);

289:

290:    ierr = HYPRE_ParCSRMatrixGetLocalRange( parcsr_A,

291:                                               &first_local_row, &last_local_row ,

292:                                               &first_local_col, &last_local_col );

293:

294:    local_num_rows = last_local_row - first_local_row + 1;

295:    local_num_cols = last_local_col - first_local_col + 1;

296:

297:    if (myid == 0)

298:    {

299:       hypre_printf("  RHS vector has unit components\n");

300:       hypre_printf("  Initial guess is 0\n");

301:    }

302:

303:    /* RHS */

304:    HYPRE_IJVectorCreate(hypre_MPI_COMM_WORLD, first_local_row, last_local_row, &ij_b);

305:    HYPRE_IJVectorSetObjectType(ij_b, HYPRE_PARCSR);

306:    HYPRE_IJVectorInitialize(ij_b);

307:

308:    /* Initial guess */

309:    HYPRE_IJVectorCreate(hypre_MPI_COMM_WORLD, first_local_col, last_local_col, &ij_x);

310:    HYPRE_IJVectorSetObjectType(ij_x, HYPRE_PARCSR);

311:    HYPRE_IJVectorInitialize(ij_x);

312:

313:    values = hypre_CTAlloc(HYPRE_Real, local_num_rows);

314:

315:    HYPRE_IJVectorSetValues(ij_x, local_num_rows, NULL, values);

316:

317:    for (i = 0; i < local_num_rows; i++)

318:       values[i] = 1.0;

319:

320:    HYPRE_IJVectorSetValues(ij_b, local_num_rows, NULL, values);

321:    hypre_TFree(values);

322:

323:    ierr = HYPRE_IJVectorGetObject( ij_b, &object );

324:    b = (HYPRE_ParVector) object;

325:

326:    ierr = HYPRE_IJVectorGetObject( ij_x, &object );

327:    x = (HYPRE_ParVector) object;

328:

329:    hypre_EndTiming(time_index);

330:    hypre_PrintTiming("IJ Vector Setup", &wall_time, hypre_MPI_COMM_WORLD);

331:    hypre_FinalizeTiming(time_index);

332:    hypre_ClearTiming();

[...]

338:    if (print_system)

339:    {

340:       HYPRE_IJMatrixPrint(ij_A, "IJ.out.A");

341:       HYPRE_IJVectorPrint(ij_b, "IJ.out.b");

342:       HYPRE_IJVectorPrint(ij_x, "IJ.out.x0");

[...]

351:    if (problem_id == 1 )

352:    {

353:       time_index = hypre_InitializeTiming("PCG Setup");

354:       hypre_MPI_Barrier(hypre_MPI_COMM_WORLD);

355:       hypre_BeginTiming(time_index);

356:

357:       HYPRE_ParCSRPCGCreate(hypre_MPI_COMM_WORLD, &pcg_solver);

358:       HYPRE_PCGSetMaxIter(pcg_solver, max_iter);

359:       HYPRE_PCGSetTol(pcg_solver, tol);

360:       HYPRE_PCGSetTwoNorm(pcg_solver, 1);

361:       HYPRE_PCGSetRelChange(pcg_solver, rel_change);

362:       HYPRE_PCGSetPrintLevel(pcg_solver, ioutdat);

363:       HYPRE_PCGSetAbsoluteTol(pcg_solver, atol);

364:

365:       /* use BoomerAMG as preconditioner */

366:       if (myid == 0 && print_stats) hypre_printf("Solver: AMG-PCG\n");

367:       HYPRE_BoomerAMGCreate(&pcg_precond);

368:       HYPRE_BoomerAMGSetTol(pcg_precond, pc_tol);

369:       HYPRE_BoomerAMGSetCoarsenType(pcg_precond, coarsen_type);

370:       HYPRE_BoomerAMGSetPMaxElmts(pcg_precond, P_max_elmts);

371:       HYPRE_BoomerAMGSetPrintLevel(pcg_precond, poutdat);

372:       HYPRE_BoomerAMGSetMaxIter(pcg_precond, 1);

373:       HYPRE_BoomerAMGSetNumSweeps(pcg_precond, num_sweeps);

374:       if (relax_type > -1) HYPRE_BoomerAMGSetRelaxType(pcg_precond, relax_type);

375:       HYPRE_BoomerAMGSetDebugFlag(pcg_precond, debug_flag);

376:       HYPRE_BoomerAMGSetAggNumLevels(pcg_precond, agg_num_levels);

377:       HYPRE_BoomerAMGSetRAP2(pcg_precond, rap2);

378:       HYPRE_BoomerAMGSetKeepTranspose(pcg_precond, keepTranspose);

379:       HYPRE_PCGSetMaxIter(pcg_solver, mg_max_iter);

380:       HYPRE_PCGSetPrecond(pcg_solver,

381:                              (HYPRE_PtrToSolverFcn) HYPRE_BoomerAMGSolve,

382:                              (HYPRE_PtrToSolverFcn) HYPRE_BoomerAMGSetup,

383:                              pcg_precond);

384:

385:       HYPRE_PCGGetPrecond(pcg_solver, &pcg_precond_gotten);

386:       if (pcg_precond_gotten !=  pcg_precond)

387:       {

388:          hypre_printf("HYPRE_ParCSRPCGGetPrecond got bad precond\n");

389:          return(-1);

390:       }

391:       else

392:          if (myid == 0 && print_stats)

393:             hypre_printf("HYPRE_ParCSRPCGGetPrecond got good precond\n");

394:

395:       HYPRE_PCGSetup(pcg_solver, (HYPRE_Matrix)parcsr_A,

396:                      (HYPRE_Vector)b, (HYPRE_Vector)x);

397:

398:       hypre_MPI_Barrier(hypre_MPI_COMM_WORLD);

399:       hypre_EndTiming(time_index);

400:       hypre_PrintTiming("Problem 1: AMG Setup Time", &wall_time, hypre_MPI_COMM_WORLD);

401:       hypre_FinalizeTiming(time_index);

402:       hypre_ClearTiming();

403:       fflush(NULL);

404:

405:       HYPRE_BoomerAMGGetCumNnzAP(pcg_precond, &cum_nnz_AP);

406:

407:       FOM1 = cum_nnz_AP/ wall_time;

408:

409:       if (myid == 0)

410:             printf ("\nFOM_Setup: nnz_AP / Setup Phase Time: %e\n\n", FOM1);

411:

412:       time_index = hypre_InitializeTiming("PCG Solve");

413:       hypre_MPI_Barrier(hypre_MPI_COMM_WORLD);

414:       hypre_BeginTiming(time_index);

415:

416:       HYPRE_PCGSolve(pcg_solver, (HYPRE_Matrix)parcsr_A,

417:                      (HYPRE_Vector)b, (HYPRE_Vector)x);

418:

419:       hypre_MPI_Barrier(hypre_MPI_COMM_WORLD);

420:       hypre_EndTiming(time_index);

421:       hypre_PrintTiming("Problem 1: AMG-PCG Solve Time", &wall_time, hypre_MPI_COMM_WORLD);

422:       hypre_FinalizeTiming(time_index);

423:       hypre_ClearTiming();

424:       fflush(NULL);

425:

426:       HYPRE_PCGGetNumIterations(pcg_solver, &num_iterations);

427:       HYPRE_PCGGetFinalRelativeResidualNorm(pcg_solver, &final_res_norm);

428:

429:

430:       HYPRE_BoomerAMGDestroy(pcg_precond);

431:

432:       HYPRE_ParCSRPCGDestroy(pcg_solver);

433:

434:       FOM2 = cum_nnz_AP*(HYPRE_Real)num_iterations/ wall_time;

435:

436:       if (myid == 0)

437:       {

438:          hypre_printf("\n");

439:          hypre_printf("Iterations = %d\n", num_iterations);

440:          hypre_printf("Final Relative Residual Norm = %e\n", final_res_norm);

441:          hypre_printf("\n");

442:          printf ("\nFOM_Solve: nnz_AP * Iterations / Solve Phase Time: %e\n\n", FOM2);

443:          FOM1 += 3.0*FOM2;

444:          FOM1 /= 4.0;

[...]

454:    if (problem_id == 2)

455:    {

456:       HYPRE_Real eps;

457:       HYPRE_Real diagonal = 26.5;

458:       AddOrRestoreAIJ(ij_A, diagonal, 0);

459:       time_index = hypre_InitializeTiming("GMRES Solve");

460:       hypre_MPI_Barrier(hypre_MPI_COMM_WORLD);

461:       hypre_BeginTiming(time_index);

462:       for (j=0; j < time_steps; j++)

463:       {

464:

465:          HYPRE_ParCSRGMRESCreate(hypre_MPI_COMM_WORLD, &pcg_solver);

466:          HYPRE_GMRESSetKDim(pcg_solver, k_dim);

467:          HYPRE_GMRESSetMaxIter(pcg_solver, max_iter);

468:          HYPRE_GMRESSetTol(pcg_solver, tol);

469:          HYPRE_GMRESSetAbsoluteTol(pcg_solver, atol);

470:          HYPRE_GMRESSetLogging(pcg_solver, 1);

471:          HYPRE_GMRESSetPrintLevel(pcg_solver, ioutdat);

472:          HYPRE_GMRESSetRelChange(pcg_solver, rel_change);

473:

474:          /* use BoomerAMG as preconditioner */

475:          if (myid == 0 && print_stats) hypre_printf("Solver: AMG-GMRES\n");

476:

477:          HYPRE_BoomerAMGCreate(&pcg_precond);

478:          HYPRE_BoomerAMGSetTol(pcg_precond, pc_tol);

479:          HYPRE_BoomerAMGSetCoarsenType(pcg_precond, coarsen_type);

480:          HYPRE_BoomerAMGSetPMaxElmts(pcg_precond, P_max_elmts);

481:          HYPRE_BoomerAMGSetPrintLevel(pcg_precond, poutdat);

482:          HYPRE_BoomerAMGSetMaxIter(pcg_precond, 1);

483:          HYPRE_BoomerAMGSetNumSweeps(pcg_precond, num_sweeps);

484:          if (relax_type > -1) HYPRE_BoomerAMGSetRelaxType(pcg_precond, relax_type);

485:          HYPRE_BoomerAMGSetDebugFlag(pcg_precond, debug_flag);

486:          HYPRE_BoomerAMGSetAggNumLevels(pcg_precond, agg_num_levels);

487:          HYPRE_BoomerAMGSetRAP2(pcg_precond, rap2);

488:          HYPRE_BoomerAMGSetKeepTranspose(pcg_precond, keepTranspose);

489:          HYPRE_GMRESSetMaxIter(pcg_solver, mg_max_iter);

490:          HYPRE_GMRESSetPrecond(pcg_solver,

491:                                (HYPRE_PtrToSolverFcn) HYPRE_BoomerAMGSolve,

492:                                (HYPRE_PtrToSolverFcn) HYPRE_BoomerAMGSetup,

493:                                pcg_precond);

494:

495:          HYPRE_GMRESGetPrecond(pcg_solver, &pcg_precond_gotten);

496:          if (pcg_precond_gotten != pcg_precond)

497:          {

498:             hypre_printf("HYPRE_GMRESGetPrecond got bad precond\n");

499:             return(-1);

500:          }

501:          else

502:             if (myid == 0 && print_stats)

503:                hypre_printf("HYPRE_GMRESGetPrecond got good precond\n");

504:          HYPRE_GMRESSetup (pcg_solver, (HYPRE_Matrix)parcsr_A, (HYPRE_Vector)b, (HYPRE_Vector)x);

505:          HYPRE_BoomerAMGGetCumNnzAP(pcg_precond, &nnz_AP);

506:          cum_nnz_AP += nnz_AP;

507:

508:          HYPRE_GMRESSolve (pcg_solver, (HYPRE_Matrix)parcsr_A, (HYPRE_Vector)b, (HYPRE_Vector)x);

509:

510:          HYPRE_GMRESGetNumIterations(pcg_solver, &num_iterations);

511:          HYPRE_GMRESGetFinalRelativeResidualNorm(pcg_solver,&final_res_norm);

512:          if (myid == 0 && print_stats)

513:          {

514:             hypre_printf("\n");

515:             hypre_printf("GMRES Iterations = %d\n", num_iterations);

516:             hypre_printf("Final GMRES Relative Residual Norm = %e\n", final_res_norm);

517:             hypre_printf("\n");

518:          }

519:          cum_num_its += num_iterations;

520:

521:          for (i=0; i < 4; i++)

522:          {

523:             HYPRE_Int gmres_iter = 6-i;

524:             eps = 0.01;

525:             AddOrRestoreAIJ(ij_A, eps, 1);

526:             HYPRE_ParVectorAxpy(eps,x,b);

527:             HYPRE_GMRESSetMaxIter(pcg_solver, gmres_iter);

528:             HYPRE_GMRESSetTol(pcg_solver, 0.0);

529:             HYPRE_GMRESSolve(pcg_solver, (HYPRE_Matrix)parcsr_A, (HYPRE_Vector)b, (HYPRE_Vector)x);

530:             HYPRE_GMRESGetNumIterations(pcg_solver, &num_iterations);

531:             HYPRE_GMRESGetFinalRelativeResidualNorm(pcg_solver,&final_res_norm);

532:             if (myid == 0 && print_stats)

533:             {

534:                hypre_printf("\n");

535:                hypre_printf("GMRES Iterations = %d\n", num_iterations);

536:                hypre_printf("Final GMRES Relative Residual Norm = %e\n", final_res_norm);

537:                hypre_printf("\n");

538:             }

539:             cum_num_its += num_iterations;

540:          }

541:

542:          HYPRE_BoomerAMGDestroy(pcg_precond);

543:

544:          HYPRE_ParCSRGMRESDestroy(pcg_solver);

545:

546:          if (j < time_steps)

547:          {

548:             diagonal -= 0.1 ;

549:             AddOrRestoreAIJ(ij_A, diagonal, 0);

550:             HYPRE_ParVectorSetConstantValues(x,0.0);

551:             HYPRE_ParVectorSetConstantValues(b,1.0);

552:          }

553:       }

554:       hypre_MPI_Barrier(hypre_MPI_COMM_WORLD);

555:       hypre_EndTiming(time_index);

556:       hypre_PrintTiming("Problem 2: Cumulative AMG-GMRES Solve Time", &wall_time, hypre_MPI_COMM_WORLD);

557:       hypre_FinalizeTiming(time_index);

558:       hypre_ClearTiming();

559:       if (myid == 0)

560:       {

561:          hypre_printf("\n");

562:          hypre_printf("No. of Time Steps = %d\n", time_steps);

563:          hypre_printf("Cum. No. of Iterations = %d\n", cum_num_its);

564:          hypre_printf("Final Relative Residual Norm = %e\n", final_res_norm);

565:          hypre_printf("\n");

566:          cum_nnz_AP /= (HYPRE_Real)time_steps;

567:          printf ("\nnnz AP * (Iterations + time_steps) / Total Time: \n");

568:          printf ("\nFigure of Merit (FOM_2): %e\n\n", (cum_nnz_AP*(HYPRE_Real)(cum_num_its +time_steps)/ wall_time));

569:          hypre_printf("\n");

[...]

578:    if (print_system)

579:    {

580:       HYPRE_IJVectorPrint(ij_x, "IJ.out.x");

[...]

587:    HYPRE_IJMatrixDestroy(ij_A);

588:

589:    HYPRE_IJVectorDestroy(ij_b);

590:

591:    HYPRE_IJVectorDestroy(ij_x);

592:

593: /*

594:   hypre_FinalizeMemoryDebug();

595: */

596:    hypre_MPI_Finalize();

597:

598:    return (0);

599: }

/usr/include/aarch64-linux-gnu/bits/stdio2.h: 112 - 112

--------------------------------------------------------------------------------

112:   return __printf_chk (__USE_FORTIFY_LEVEL - 1, __fmt, __va_arg_pack ());

0x40f800 ADRP	X2,

0x40f804 STP	X29, X30, [SP, #624]!

0x40f808 ADD	X29, SP, #0

0x40f80c ORR	X3, XZR, X1

0x40f810 ADD	X1, SP, #224

0x40f814 LDR	X4, [X2, #3848]

0x40f818 STP	X19, X20, [SP, #16]

0x40f81c STP	X21, X22, [SP, #32]

0x40f820 STP	X23, X24, [SP, #48]

0x40f824 STP	X25, X26, [SP, #64]

0x40f828 STP	X27, X28, [SP, #80]

0x40f82c STR	X3, [SP, #224]

0x40f830 STR	W0, [SP, #236]

0x40f834 ADD	X0, SP, #236

0x40f838 LDR	X3, [X4]

0x40f83c STR	X3, [SP, #392]

0x40f840 MOVZ	X3, #0

0x40f844 STR	XZR, [SP, #304]

0x40f848 STR	XZR, [SP, #376]

0x40f84c BL	518628

0x40f850 ADRP	X0,

0x40f854 ADD	X1, SP, #320

0x40f858 LDR	X0, [X0, #3856]

0x40f85c BL	518744

0x40f860 LDRSW	X20, [SP, #236]

0x40f864 CMP	X20, #1

0x40f868 B.LE	40f9fc

0x40f86c MOVZ	X19, #1

0x40f870 ADRP	X6,

0x40f874 LDR	X28, [SP, #224]

0x40f878 SUB	X7, X20, X19

0x40f87c ADD	X23, X6, #464

0x40f880 ANDS	X8, X7, #4224

0x40f884 B.EQ	40f94c

0x40f888 CMP	X8, X19

0x40f88c B.EQ	40f930

0x40f890 CMP	X8, #2

0x40f894 B.EQ	40f91c

0x40f898 CMP	X8, #3

0x40f89c B.EQ	40f908

0x40f8a0 CMP	X8, #4

0x40f8a4 B.EQ	40f8f4

0x40f8a8 CMP	X8, #5

0x40f8ac B.EQ	40f8e0

0x40f8b0 CMP	X8, #6

0x40f8b4 B.EQ	40f8cc

0x40f8b8 ORR	X1, XZR, X23

0x40f8bc LDR	X0, [X28, #8]

0x40f8c0 BL	40f6b0

0x40f8c4 CBZ	W0, 40fe68

0x40f8c8 MOVZ	X19, #2

0x40f8cc ORR	X1, XZR, X23

0x40f8d0 LDR	X0, [X28, X19,LSL #3]

0x40f8d4 BL	40f6b0

0x40f8d8 CBZ	W0, 40fe68

0x40f8dc ADD	X19, X19, #1

0x40f8e0 ORR	X1, XZR, X23

0x40f8e4 LDR	X0, [X28, X19,LSL #3]

0x40f8e8 BL	40f6b0

0x40f8ec CBZ	W0, 40fe68

0x40f8f0 ADD	X19, X19, #1

0x40f8f4 ORR	X1, XZR, X23

0x40f8f8 LDR	X0, [X28, X19,LSL #3]

0x40f8fc BL	40f6b0

0x40f900 CBZ	W0, 40fe68

0x40f904 ADD	X19, X19, #1

0x40f908 ORR	X1, XZR, X23

0x40f90c LDR	X0, [X28, X19,LSL #3]

0x40f910 BL	40f6b0

0x40f914 CBZ	W0, 40fe68

0x40f918 ADD	X19, X19, #1

0x40f91c ORR	X1, XZR, X23

0x40f920 LDR	X0, [X28, X19,LSL #3]

0x40f924 BL	40f6b0

0x40f928 CBZ	W0, 40fe68

0x40f92c ADD	X19, X19, #1

0x40f930 ORR	X1, XZR, X23

0x40f934 LDR	X0, [X28, X19,LSL #3]

0x40f938 BL	40f6b0

0x40f93c CBZ	W0, 40fe68

0x40f940 ADD	X19, X19, #1

0x40f944 CMP	X20, X19

0x40f948 B.EQ	40f9f4

(8) 0x40f94c ORR	X1, XZR, X23

(8) 0x40f950 LDR	X0, [X28, X19,LSL #3]

(8) 0x40f954 BL	40f6b0

(8) 0x40f958 CBZ	W0, 40fe68

(8) 0x40f95c ADD	X22, X19, #1

(8) 0x40f960 ORR	X1, XZR, X23

(8) 0x40f964 LDR	X0, [X28, X22,LSL #3]

(8) 0x40f968 BL	40f6b0

(8) 0x40f96c CBZ	W0, 40fe68

(8) 0x40f970 ADD	X9, X22, #1

(8) 0x40f974 ORR	X1, XZR, X23

(8) 0x40f978 LDR	X0, [X28, X9,LSL #3]

(8) 0x40f97c BL	40f6b0

(8) 0x40f980 CBZ	W0, 40fe68

(8) 0x40f984 ADD	X10, X19, #3

(8) 0x40f988 ORR	X1, XZR, X23

(8) 0x40f98c LDR	X0, [X28, X10,LSL #3]

(8) 0x40f990 BL	40f6b0

(8) 0x40f994 CBZ	W0, 40fe68

(8) 0x40f998 ADD	X11, X19, #4

(8) 0x40f99c ORR	X1, XZR, X23

(8) 0x40f9a0 LDR	X0, [X28, X11,LSL #3]

(8) 0x40f9a4 BL	40f6b0

(8) 0x40f9a8 CBZ	W0, 40fe68

(8) 0x40f9ac ADD	X12, X19, #5

(8) 0x40f9b0 ORR	X1, XZR, X23

(8) 0x40f9b4 LDR	X0, [X28, X12,LSL #3]

(8) 0x40f9b8 BL	40f6b0

(8) 0x40f9bc CBZ	W0, 40fe68

(8) 0x40f9c0 ADD	X13, X19, #6

(8) 0x40f9c4 ORR	X1, XZR, X23

(8) 0x40f9c8 LDR	X0, [X28, X13,LSL #3]

(8) 0x40f9cc BL	40f6b0

(8) 0x40f9d0 CBZ	W0, 40fe68

(8) 0x40f9d4 ADD	X14, X19, #7

(8) 0x40f9d8 ORR	X1, XZR, X23

(8) 0x40f9dc LDR	X0, [X28, X14,LSL #3]

(8) 0x40f9e0 BL	40f6b0

(8) 0x40f9e4 CBZ	W0, 40fe68

(8) 0x40f9e8 ADD	X19, X19, #8

(8) 0x40f9ec CMP	X20, X19

(8) 0x40f9f0 B.NE	40f94c

0x40f9f4 STR	XZR, [SP, #168]

0x40f9f8 B	40fa08

0x40f9fc STR	XZR, [SP, #168]

0x40fa00 LDR	X28, [SP, #224]

0x40fa04 B.NE	40fe28

0x40fa08 MOVZ	X16, #1

0x40fa0c ADRP	X24,

0x40fa10 ADRP	X27,

0x40fa14 ADD	X24, X24, #472

0x40fa18 ADD	X27, X27, #488

0x40fa1c MOVZ	X21, #0

0x40fa20 STP	X16, XZR, [SP, #128]

0x40fa24 MOVZ	X25, #0

0x40fa28 MOVZ	X22, #0

0x40fa2c STP	XZR, X16, [SP, #144]

0x40fa30 STR	X16, [SP, #160]

0x40fa34 B	40fa9c

    (3) 0x40fa38 ADRP	X17,

    (3) 0x40fa3c ORR	X0, XZR, X19

    (3) 0x40fa40 ADD	X1, X17, #504

    (3) 0x40fa44 BL	40f6b0

    (3) 0x40fa48 CBZ	W0, 40fdf8

    (3) 0x40fa4c ADRP	X18,

    (3) 0x40fa50 ORR	X0, XZR, X19

    (3) 0x40fa54 ADD	X1, X18, #520

    (3) 0x40fa58 BL	40f6b0

    (3) 0x40fa5c CBZ	W0, 40fe18

    (3) 0x40fa60 ADRP	X30,

    (3) 0x40fa64 ORR	X0, XZR, X19

    (3) 0x40fa68 ADD	X1, X30, #528

    (3) 0x40fa6c ORR	X22, XZR, X23

    (3) 0x40fa70 BL	40f6b0

    (3) 0x40fa74 CMP	W0, #0

    (3) 0x40fa78 LDR	X2, [SP, #144]

    (3) 0x40fa7c CSINC	X3, X2, XZR, #1

    (3) 0x40fa80 STR	X3, [SP, #144]

    (3) 0x40fa84 LDR	X4, [SP, #152]

    (3) 0x40fa88 CSEL	X0, X4, XZR, #1

    (3) 0x40fa8c STR	X0, [SP, #152]

    (3) 0x40fa90 CMP	X20, X22

    (3) 0x40fa94 B.LE	40fadc

      (4) 0x40fa98 LDR	X28, [SP, #224]

      (4) 0x40fa9c ORR	X1, XZR, X24

      (4) 0x40faa0 UBFM	X26, X22, #61, #60

      (4) 0x40faa4 LDR	X19, [X28, X22,LSL #3]

      (4) 0x40faa8 ADD	X23, X22, #1

      (4) 0x40faac ORR	X0, XZR, X19

      (4) 0x40fab0 BL	40f6b0

      (4) 0x40fab4 CBZ	W0, 40fdc8

      (4) 0x40fab8 ORR	X1, XZR, X27

      (4) 0x40fabc ORR	X0, XZR, X19

      (4) 0x40fac0 BL	40f6b0

      (4) 0x40fac4 CBNZ	W0, 40fa38

      (4) 0x40fac8 MOVZ	X21, #1

      (4) 0x40facc ORR	X22, XZR, X23

      (4) 0x40fad0 ORR	X25, XZR, X21

      (4) 0x40fad4 CMP	X20, X22

      (4) 0x40fad8 B.GT	40fa98

  (1) 0x40fadc LDR	X7, [SP, #168]

  (1) 0x40fae0 LDR	X5, [SP, #320]

  (1) 0x40fae4 CBZ	X7, 40fe44

  (1) 0x40fae8 CBZ	X5, 41081c

  (1) 0x40faec ADRP	X9,

  (1) 0x40faf0 ADD	X27, SP, #360

  (1) 0x40faf4 ADD	X0, X9, #1176

  (1) 0x40faf8 ADD	X19, SP, #264

  (1) 0x40fafc STR	X27, [SP, #160]

  (1) 0x40fb00 BL	519680

  (1) 0x40fb04 ORR	X26, XZR, X0

  (1) 0x40fb08 BL	519e28

  (1) 0x40fb0c ADD	X3, SP, #272

  (1) 0x40fb10 ADD	X2, SP, #368

  (1) 0x40fb14 LDRSW	X0, [SP, #236]

  (1) 0x40fb18 LDR	X1, [SP, #224]

  (1) 0x40fb1c BL	41568c

  (1) 0x40fb20 LDR	X23, [SP, #272]

  (1) 0x40fb24 ORR	X1, XZR, X19

  (1) 0x40fb28 ORR	X0, XZR, X23

  (1) 0x40fb2c BL	4f2cc0

  (1) 0x40fb30 ORR	X0, XZR, X26

  (1) 0x40fb34 LDR	X24, [SP, #264]

  (1) 0x40fb38 BL	519f0c

  (1) 0x40fb3c ADRP	X10,

  (1) 0x40fb40 ADRP	X11,

  (1) 0x40fb44 LDR	X2, [X10, #3856]

  (1) 0x40fb48 ORR	X1, XZR, X27

  (1) 0x40fb4c ADD	X0, X11, #1200

  (1) 0x40fb50 BL	51a1e0

  (1) 0x40fb54 ORR	X0, XZR, X26

  (1) 0x40fb58 BL	519ccc

  (1) 0x40fb5c BL	519fe0

  (1) 0x40fb60 ADRP	X12,

  (1) 0x40fb64 ADD	X0, X12, #1216

  (1) 0x40fb68 BL	519680

  (1) 0x40fb6c ORR	X22, XZR, X0

  (1) 0x40fb70 BL	519e28

  (1) 0x40fb74 ADD	X2, SP, #336

  (1) 0x40fb78 ADD	X1, SP, #328

  (1) 0x40fb7c ORR	X0, XZR, X24

  (1) 0x40fb80 ADD	X4, SP, #352

  (1) 0x40fb84 ADD	X3, SP, #344

  (1) 0x40fb88 BL	4d55a4

  (1) 0x40fb8c LDP	X13, X1, [SP, #320]

  (1) 0x40fb90 LDR	X2, [SP, #336]

  (1) 0x40fb94 SUB	X18, X2, X1

  (1) 0x40fb98 ADD	X28, X18, #1

  (1) 0x40fb9c CBZ	X13, 40fe74

  (1) 0x40fba0 ADRP	X16,

  (1) 0x40fba4 ADD	X3, SP, #280

  (1) 0x40fba8 STR	X18, [SP, #168]

  (1) 0x40fbac LDR	X20, [X16, #3856]

  (1) 0x40fbb0 ORR	X0, XZR, X20

  (1) 0x40fbb4 BL	4f3500

  (1) 0x40fbb8 MOVZ	X1, #5555

  (1) 0x40fbbc LDR	X0, [SP, #280]

  (1) 0x40fbc0 BL	4f3c40

  (1) 0x40fbc4 LDR	X0, [SP, #280]

  (1) 0x40fbc8 BL	4f37c0

  (1) 0x40fbcc LDP	X1, X2, [SP, #344]

  (1) 0x40fbd0 ADD	X3, SP, #288

  (1) 0x40fbd4 ORR	X0, XZR, X20

  (1) 0x40fbd8 BL	4f3500

  (1) 0x40fbdc MOVZ	X1, #5555

  (1) 0x40fbe0 LDR	X0, [SP, #288]

  (1) 0x40fbe4 BL	4f3c40

  (1) 0x40fbe8 LDR	X0, [SP, #288]

  (1) 0x40fbec BL	4f37c0

  (1) 0x40fbf0 MOVZ	X1, #8

  (1) 0x40fbf4 ORR	X0, XZR, X28

  (1) 0x40fbf8 BL	51674c

  (1) 0x40fbfc ORR	X3, XZR, X0

  (1) 0x40fc00 ORR	X27, XZR, X0

  (1) 0x40fc04 LDR	X0, [SP, #288]

  (1) 0x40fc08 MOVZ	X2, #0

  (1) 0x40fc0c ORR	X1, XZR, X28

  (1) 0x40fc10 BL	4f38b0

  (1) 0x40fc14 MOVZ	X4, #0

  (1) 0x40fc18 CMP	X28, #0

  (1) 0x40fc1c B.LE	40fce4

  (1) 0x40fc20 LDR	X17, [SP, #168]

  (1) 0x40fc24 FMOV	D0, #1.0000000

  (1) 0x40fc28 ADD	X30, X17, #1

  (1) 0x40fc2c ANDS	X2, X30, #4224

  (1) 0x40fc30 B.EQ	40fc9c

  (1) 0x40fc34 CMP	X2, #1

  (1) 0x40fc38 B.EQ	40fc8c

  (1) 0x40fc3c CMP	X2, #2

  (1) 0x40fc40 B.EQ	40fc84

  (1) 0x40fc44 CMP	X2, #3

  (1) 0x40fc48 B.EQ	40fc7c

  (1) 0x40fc4c CMP	X2, #4

  (1) 0x40fc50 B.EQ	40fc74

  (1) 0x40fc54 CMP	X2, #5

  (1) 0x40fc58 B.EQ	40fc6c

  (1) 0x40fc5c CMP	X2, #6

  (1) 0x40fc60 B.NE	410600

  (1) 0x40fc64 STR	D0, [X27, X4,LSL #3]

  (1) 0x40fc68 ADD	X4, X4, #1

  (1) 0x40fc6c STR	D0, [X27, X4,LSL #3]

  (1) 0x40fc70 ADD	X4, X4, #1

  (1) 0x40fc74 STR	D0, [X27, X4,LSL #3]

  (1) 0x40fc78 ADD	X4, X4, #1

  (1) 0x40fc7c STR	D0, [X27, X4,LSL #3]

  (1) 0x40fc80 ADD	X4, X4, #1

  (1) 0x40fc84 STR	D0, [X27, X4,LSL #3]

  (1) 0x40fc88 ADD	X4, X4, #1

  (1) 0x40fc8c CMP	X17, X4

  (1) 0x40fc90 STR	D0, [X27, X4,LSL #3]

  (1) 0x40fc94 ADD	X4, X4, #1

  (1) 0x40fc98 B.EQ	40fce4

    (7) 0x40fc9c ADD	X0, X4, #1

    (7) 0x40fca0 ADD	X6, X4, #2

    (7) 0x40fca4 STR	D0, [X27, X4,LSL #3]

    (7) 0x40fca8 ADD	X1, X4, #3

    (7) 0x40fcac ADD	X5, X4, #4

    (7) 0x40fcb0 STR	D0, [X27, X0,LSL #3]

    (7) 0x40fcb4 ADD	X7, X4, #5

    (7) 0x40fcb8 ADD	X8, X4, #6

    (7) 0x40fcbc STR	D0, [X27, X6,LSL #3]

    (7) 0x40fcc0 ADD	X9, X4, #7

    (7) 0x40fcc4 ADD	X4, X4, #8

    (7) 0x40fcc8 STR	D0, [X27, X1,LSL #3]

    (7) 0x40fccc STR	D0, [X27, X5,LSL #3]

    (7) 0x40fcd0 STR	D0, [X27, X7,LSL #3]

    (7) 0x40fcd4 STR	D0, [X27, X8,LSL #3]

    (7) 0x40fcd8 STR	D0, [X27, X9,LSL #3]

    (7) 0x40fcdc CMP	X17, X9

    (7) 0x40fce0 B.NE	40fc9c

  (1) 0x40fce4 ORR	X3, XZR, X27

  (1) 0x40fce8 MOVZ	X2, #0

  (1) 0x40fcec LDR	X0, [SP, #280]

  (1) 0x40fcf0 ORR	X1, XZR, X28

  (1) 0x40fcf4 ADRP	X26,

  (1) 0x40fcf8 BL	4f38b0

  (1) 0x40fcfc ORR	X0, XZR, X27

  (1) 0x40fd00 BL	516820

  (1) 0x40fd04 ORR	X1, XZR, X19

  (1) 0x40fd08 LDR	X0, [SP, #280]

  (1) 0x40fd0c BL	4f3da0

  (1) 0x40fd10 ORR	X1, XZR, X19

  (1) 0x40fd14 LDR	X0, [SP, #288]

  (1) 0x40fd18 LDR	X19, [SP, #264]

  (1) 0x40fd1c BL	4f3da0

  (1) 0x40fd20 ORR	X0, XZR, X22

  (1) 0x40fd24 LDR	X20, [SP, #264]

  (1) 0x40fd28 BL	519f0c

  (1) 0x40fd2c ADRP	X10,

  (1) 0x40fd30 LDR	X2, [X26, #3856]

  (1) 0x40fd34 ADD	X0, X10, #1304

  (1) 0x40fd38 LDR	X1, [SP, #160]

  (1) 0x40fd3c BL	51a1e0

  (1) 0x40fd40 ORR	X0, XZR, X22

  (1) 0x40fd44 BL	519ccc

  (1) 0x40fd48 BL	519fe0

  (1) 0x40fd4c LDR	X11, [SP, #136]

  (1) 0x40fd50 CBNZ	X11, 40fe9c

  (1) 0x40fd54 LDR	X28, [SP, #128]

  (1) 0x40fd58 CMP	X28, #1

  (1) 0x40fd5c B.EQ	40fee4

  (1) 0x40fd60 CMP	X28, #2

  (1) 0x40fd64 B.EQ	410184

  (1) 0x40fd68 LDR	X2, [SP, #136]

  (1) 0x40fd6c CBNZ	X2, 40fed0

  (1) 0x40fd70 ORR	X0, XZR, X23

  (1) 0x40fd74 BL	4f23a0

  (1) 0x40fd78 LDR	X0, [SP, #280]

  (1) 0x40fd7c BL	4f36e8

  (1) 0x40fd80 LDR	X0, [SP, #288]

  (1) 0x40fd84 BL	4f36e8

  (1) 0x40fd88 BL	518640

  (1) 0x40fd8c MOVZ	W0, #0

  (1) 0x40fd90 ADRP	X4,

  (1) 0x40fd94 LDR	X1, [X4, #3848]

  (1) 0x40fd98 LDR	X3, [SP, #392]

  (1) 0x40fd9c LDR	X2, [X1]

  (1) 0x40fda0 SUBS	X3, X3, X2

  (1) 0x40fda4 MOVZ	X2, #0

  (1) 0x40fda8 B.NE	4108e4

  (1) 0x40fdac LDP	X19, X20, [SP, #16]

  (1) 0x40fdb0 LDP	X21, X22, [SP, #32]

  (1) 0x40fdb4 LDP	X23, X24, [SP, #48]

  (1) 0x40fdb8 LDP	X25, X26, [SP, #64]

  (1) 0x40fdbc LDP	X27, X28, [SP, #80]

  (1) 0x40fdc0 LDP	X29, X30, [SP], #400

  (1) 0x40fdc4 RET

    (2) 0x40fdc8 ADD	X20, X28, X26

    (2) 0x40fdcc MOVZ	W2, #10

    (2) 0x40fdd0 MOVZ	X1, #0

    (2) 0x40fdd4 LDR	X0, [X20, #8]

    (2) 0x40fdd8 ADD	X22, X22, #2

    (2) 0x40fddc BL	40f330

  (1) 0x40fde0 SBFM	X5, X0, #0, #31

  (1) 0x40fde4 STR	X5, [SP, #128]

  (1) 0x40fde8 CMP	W0, #2

  (1) 0x40fdec B.EQ	40fe08

  (1) 0x40fdf0 LDRSW	X20, [SP, #236]

  (1) 0x40fdf4 B	40fa90

    (3) 0x40fdf8 ORR	X22, XZR, X23

    (3) 0x40fdfc MOVZ	X21, #1

    (3) 0x40fe00 MOVZ	X25, #3

    (3) 0x40fe04 B	40fa90

  (1) 0x40fe08 MOVZ	X6, #3

  (1) 0x40fe0c LDRSW	X20, [SP, #236]

  (1) 0x40fe10 STR	X6, [SP, #160]

  (1) 0x40fe14 B	40fa90

    (3) 0x40fe18 MOVZ	X1, #1

    (3) 0x40fe1c ORR	X22, XZR, X23

    (3) 0x40fe20 STR	X1, [SP, #136]

    (3) 0x40fe24 B	40fa90

0x40fe28 LDR	X5, [SP, #320]

0x40fe2c MOVZ	X1, #1

0x40fe30 MOVZ	X25, #0

0x40fe34 MOVZ	X21, #0

0x40fe38 STP	X1, XZR, [SP, #128]

0x40fe3c STP	XZR, X1, [SP, #144]

0x40fe40 STR	X1, [SP, #160]

(0) 0x40fe44 CBNZ	X5, 40faec

(0) 0x40fe48 ADRP	X8,

(0) 0x40fe4c ADRP	X28,

(0) 0x40fe50 ADD	X0, X8, #1112

(0) 0x40fe54 BL	5169a0

(0) 0x40fe58 ADD	X0, X28, #1152

(0) 0x40fe5c LDR	X1, [SP, #160]

(0) 0x40fe60 BL	5169a0

(0) 0x40fe64 B	40faec

0x40fe68 MOVZ	X15, #1

0x40fe6c STR	X15, [SP, #168]

0x40fe70 B	40fa08

  (1) 0x40fe74 ADRP	X14,

  (1) 0x40fe78 STR	X18, [SP, #168]

  (1) 0x40fe7c ADD	X0, X14, #1240

  (1) 0x40fe80 BL	5169a0

  (1) 0x40fe84 ADRP	X15,

  (1) 0x40fe88 ADD	X0, X15, #1280

  (1) 0x40fe8c BL	5169a0

  (1) 0x40fe90 LDR	X18, [SP, #168]

  (1) 0x40fe94 LDP	X1, X2, [SP, #328]

  (1) 0x40fe98 B	40fba0

  (1) 0x40fe9c ADRP	X12,

  (1) 0x40fea0 ORR	X0, XZR, X23

  (1) 0x40fea4 ADD	X1, X12, #1320

  (1) 0x40fea8 ADRP	X22,

  (1) 0x40feac BL	4f31c8

  (1) 0x40feb0 ADD	X1, X22, #1336

  (1) 0x40feb4 LDR	X0, [SP, #280]

  (1) 0x40feb8 BL	4f4140

  (1) 0x40febc ADRP	X13,

  (1) 0x40fec0 LDR	X0, [SP, #288]

  (1) 0x40fec4 ADD	X1, X13, #1352

  (1) 0x40fec8 BL	4f4140

  (1) 0x40fecc B	40fd54

  (1) 0x40fed0 ADRP	X3,

  (1) 0x40fed4 LDR	X0, [SP, #288]

  (1) 0x40fed8 ADD	X1, X3, #2176

  (1) 0x40fedc BL	4f4140

  (1) 0x40fee0 B	40fd70

  (1) 0x40fee4 ADRP	X18,

  (1) 0x40fee8 ORR	W28, WZR, W21

  (1) 0x40feec ADD	X0, X18, #1368

  (1) 0x40fef0 BL	519680

  (1) 0x40fef4 ADRP	X2,

  (1) 0x40fef8 ORR	X22, XZR, X0

  (1) 0x40fefc LDR	X3, [X2, #3856]

  (1) 0x40ff00 ORR	X0, XZR, X3

  (1) 0x40ff04 STR	X3, [SP, #168]

  (1) 0x40ff08 BL	518688

  (1) 0x40ff0c ORR	X0, XZR, X22

  (1) 0x40ff10 BL	519e28

  (1) 0x40ff14 ADD	X1, SP, #296

  (1) 0x40ff18 LDR	X0, [SP, #168]

  (1) 0x40ff1c BL	416440

  (1) 0x40ff20 MOVZ	X1, #1000

  (1) 0x40ff24 LDR	X0, [SP, #296]

  (1) 0x40ff28 BL	513748

  (1) 0x40ff2c ADRP	X4,

  (1) 0x40ff30 LDR	X0, [SP, #296]

  (1) 0x40ff34 LDR	D0, [X4, #2192]

  (1) 0x40ff38 BL	513708

  (1) 0x40ff3c LDR	X1, [SP, #128]

  (1) 0x40ff40 LDR	X0, [SP, #296]

  (1) 0x40ff44 BL	513764

  (1) 0x40ff48 MOVZ	X1, #0

  (1) 0x40ff4c LDR	X0, [SP, #296]

  (1) 0x40ff50 BL	51376c

  (1) 0x40ff54 ORR	X1, XZR, X25

  (1) 0x40ff58 LDR	X0, [SP, #296]

  (1) 0x40ff5c BL	5137ac

  (1) 0x40ff60 MOVI	D0, #0

  (1) 0x40ff64 LDR	X0, [SP, #296]

  (1) 0x40ff68 BL	513710

  (1) 0x40ff6c LDR	X1, [SP, #320]

  (1) 0x40ff70 CMP	X1, #0

  (1) 0x40ff74 CCMP	W21, #0, #4, #0

  (1) 0x40ff78 B.NE	4107e8

  (1) 0x40ff7c ADD	X0, SP, #304

  (1) 0x40ff80 BL	415d20

  (1) 0x40ff84 MOVI	D0, #0

  (1) 0x40ff88 LDR	X0, [SP, #304]

  (1) 0x40ff8c BL	415ec4

  (1) 0x40ff90 MOVZ	X1, #8

  (1) 0x40ff94 LDR	X0, [SP, #304]

  (1) 0x40ff98 BL	415e48

  (1) 0x40ff9c MOVZ	X1, #8

  (1) 0x40ffa0 LDR	X0, [SP, #304]

  (1) 0x40ffa4 BL	415e00

  (1) 0x40ffa8 ORR	X1, XZR, X21

  (1) 0x40ffac LDR	X0, [SP, #304]

  (1) 0x40ffb0 ADRP	X21,

  (1) 0x40ffb4 BL	4161b0

  (1) 0x40ffb8 MOVZ	X1, #1

  (1) 0x40ffbc LDR	X0, [SP, #304]

  (1) 0x40ffc0 BL	415e40

  (1) 0x40ffc4 MOVZ	X1, #2

  (1) 0x40ffc8 LDR	X0, [SP, #304]

  (1) 0x40ffcc BL	415ed0

  (1) 0x40ffd0 MOVZ	X1, #18

  (1) 0x40ffd4 LDR	X0, [SP, #304]

  (1) 0x40ffd8 BL	416164

  (1) 0x40ffdc MOVZ	X1, #0

  (1) 0x40ffe0 LDR	X0, [SP, #304]

  (1) 0x40ffe4 BL	4161c8

  (1) 0x40ffe8 MOVZ	X1, #1

  (1) 0x40ffec LDR	X0, [SP, #304]

  (1) 0x40fff0 BL	416224

  (1) 0x40fff4 LDR	X1, [SP, #152]

  (1) 0x40fff8 LDR	X0, [SP, #304]

  (1) 0x40fffc BL	4162cc

  (1) 0x410000 LDR	X1, [SP, #144]

  (1) 0x410004 LDR	X0, [SP, #304]

  (1) 0x410008 BL	4162d0

  (1) 0x41000c MOVZ	X1, #100

  (1) 0x410010 LDR	X0, [SP, #296]

  (1) 0x410014 BL	513748

  (1) 0x410018 ADRP	X6,

  (1) 0x41001c LDR	X2, [X21, #3928]

  (1) 0x410020 LDP	X0, X3, [SP, #296]

  (1) 0x410024 LDR	X1, [X6, #4016]

  (1) 0x410028 BL	513790

  (1) 0x41002c LDR	X0, [SP, #296]

  (1) 0x410030 ADD	X1, SP, #312

  (1) 0x410034 BL	5137a0

  (1) 0x410038 LDP	X5, X7, [SP, #304]

  (1) 0x41003c CMP	X7, X5

  (1) 0x410040 B.NE	4107f8

  (1) 0x410044 LDR	X17, [SP, #320]

  (1) 0x410048 STP	D8, D9, [SP, #96]

  (1) 0x41004c CMP	X17, #0

  (1) 0x410050 CCMP	W28, #0, #4, #0

  (1) 0x410054 B.NE	41080c

  (1) 0x410058 ORR	X3, XZR, X20

  (1) 0x41005c ORR	X2, XZR, X19

  (1) 0x410060 LDR	X0, [SP, #296]

  (1) 0x410064 ORR	X1, XZR, X24

  (1) 0x410068 BL	513700

  (1) 0x41006c ADRP	X8,

  (1) 0x410070 LDR	X27, [X8, #3856]

  (1) 0x410074 ORR	X0, XZR, X27

  (1) 0x410078 BL	518688

  (1) 0x41007c ORR	X0, XZR, X22

  (1) 0x410080 BL	519f0c

  (1) 0x410084 ADRP	X9, 51d084

  (1) 0x410088 LDR	X1, [SP, #160]

  (1) 0x41008c ORR	X2, XZR, X27

  (1) 0x410090 ADD	X0, X9, #1504

  (1) 0x410094 BL	51a1e0

  (1) 0x410098 ORR	X0, XZR, X22

  (1) 0x41009c BL	519ccc

  (1) 0x4100a0 BL	519fe0

  (1) 0x4100a4 MOVZ	X0, #0

  (1) 0x4100a8 BL	40f560

  (1) 0x4100ac ADD	X1, SP, #376

  (1) 0x4100b0 LDR	X0, [SP, #304]

  (1) 0x4100b4 BL	4161e4

  (1) 0x4100b8 LDR	D25, [SP, #360]

  (1) 0x4100bc LDR	D26, [SP, #376]

  (1) 0x4100c0 LDR	X10, [SP, #320]

  (1) 0x4100c4 FDIV	D9, D26, D25

  (1) 0x4100c8 CBZ	X10, 410714

  (1) 0x4100cc ADRP	X11, 51d0cc

  (1) 0x4100d0 ADD	X0, X11, #1584

  (1) 0x4100d4 BL	519680

  (1) 0x4100d8 ADRP	X12,

  (1) 0x4100dc ORR	X28, XZR, X0

  (1) 0x4100e0 LDR	X25, [X12, #3856]

  (1) 0x4100e4 ORR	X0, XZR, X25

  (1) 0x4100e8 BL	518688

  (1) 0x4100ec ORR	X0, XZR, X28

  (1) 0x4100f0 BL	519e28

  (1) 0x4100f4 ORR	X3, XZR, X20

  (1) 0x4100f8 ORR	X2, XZR, X19

  (1) 0x4100fc LDR	X0, [SP, #296]

  (1) 0x410100 ORR	X1, XZR, X24

  (1) 0x410104 ADRP	X24, 51d104

  (1) 0x410108 BL	513704

  (1) 0x41010c ORR	X0, XZR, X25

  (1) 0x410110 BL	518688

  (1) 0x410114 ORR	X0, XZR, X28

  (1) 0x410118 BL	519f0c

  (1) 0x41011c LDR	X1, [SP, #160]

  (1) 0x410120 ORR	X2, XZR, X25

  (1) 0x410124 ADD	X0, X24, #1600

  (1) 0x410128 BL	51a1e0

  (1) 0x41012c ORR	X0, XZR, X28

  (1) 0x410130 BL	519ccc

  (1) 0x410134 BL	519fe0

  (1) 0x410138 MOVZ	X0, #0

  (1) 0x41013c BL	40f560

  (1) 0x410140 ADD	X1, SP, #248

  (1) 0x410144 LDR	X0, [SP, #296]

  (1) 0x410148 BL	5137c0

  (1) 0x41014c ADD	X1, SP, #256

  (1) 0x410150 LDR	X0, [SP, #296]

  (1) 0x410154 BL	5137c8

  (1) 0x410158 LDR	X0, [SP, #304]

  (1) 0x41015c BL	415d80

  (1) 0x410160 LDR	X0, [SP, #296]

  (1) 0x410164 BL	416540

  (1) 0x410168 LDR	X19, [SP, #320]

  (1) 0x41016c LDR	D27, [SP, #248]

  (1) 0x410170 LDR	D28, [SP, #360]

  (1) 0x410174 LDR	D29, [SP, #376]

  (1) 0x410178 CBZ	X19, 410694

  (1) 0x41017c LDP	D8, D9, [SP, #96]

  (1) 0x410180 B	40fd68

  (1) 0x410184 MOVZ	X14, #32768

  (1) 0x410188 ADRP	X15,

  (1) 0x41018c STP	D8, D9, [SP, #96]

  (1) 0x410190 MOVK	X14, #16442

  (1) 0x410194 ADRP	X18,

  (1) 0x410198 STP	D10, D11, [SP, #112]

  (1) 0x41019c ADRP	X17,

  (1) 0x4101a0 LDR	D10, [X15, #2192]

  (1) 0x4101a4 MOVZ	X16, #6

  (1) 0x4101a8 FMOV	D0, X14

  (1) 0x4101ac ADD	X30, SP, #296

  (1) 0x4101b0 ADD	X2, SP, #304

  (1) 0x4101b4 LDR	D8, [X18, #2200]

  (1) 0x4101b8 MOVZ	X1, #0

  (1) 0x4101bc ORR	X0, XZR, X23

  (1) 0x4101c0 STR	X16, [SP, #128]

  (1) 0x4101c4 ORR	W27, WZR, W21

  (1) 0x4101c8 MOVZ	X22, #0

  (1) 0x4101cc LDR	D11, [X17, #2208]

  (1) 0x4101d0 STR	X30, [SP, #184]

  (1) 0x4101d4 STR	X2, [SP, #192]

  (1) 0x4101d8 BL	415bb0

  (1) 0x4101dc ADRP	X3,

  (1) 0x4101e0 ADD	X4, SP, #312

  (1) 0x4101e4 ADD	X0, X3, #1792

  (1) 0x4101e8 STR	X4, [SP, #200]

  (1) 0x4101ec BL	519680

  (1) 0x4101f0 ORR	X26, XZR, X0

  (1) 0x4101f4 ADRP	X0,

  (1) 0x4101f8 LDR	X0, [X0, #3856]

  (1) 0x4101fc STR	X26, [SP, #216]

  (1) 0x410200 BL	518688

  (1) 0x410204 ORR	X0, XZR, X26

  (1) 0x410208 BL	519e28

  (1) 0x41020c MOVZ	X1, #32768

  (1) 0x410210 STR	X21, [SP, #168]

  (1) 0x410214 MOVK	X1, #16442

  (1) 0x410218 STR	X25, [SP, #208]

  (1) 0x41021c FMOV	D9, X1

    (6) 0x410220 ADRP	X25,

    (6) 0x410224 LDR	X1, [SP, #184]

    (6) 0x410228 LDR	X0, [X25, #3856]

    (6) 0x41022c BL	4162e0

    (6) 0x410230 MOVZ	X1, #20

    (6) 0x410234 LDR	X0, [SP, #296]

    (6) 0x410238 BL	513648

    (6) 0x41023c MOVZ	X1, #1000

    (6) 0x410240 LDR	X0, [SP, #296]

    (6) 0x410244 BL	513688

    (6) 0x410248 FMOV	D0, D10

    (6) 0x41024c LDR	X0, [SP, #296]

    (6) 0x410250 BL	513650

    (6) 0x410254 MOVI	D0, #0

    (6) 0x410258 LDR	X0, [SP, #296]

    (6) 0x41025c BL	513664

    (6) 0x410260 MOVZ	X1, #1

    (6) 0x410264 LDR	X0, [SP, #296]

    (6) 0x410268 BL	5136d0

    (6) 0x41026c LDR	X1, [SP, #208]

    (6) 0x410270 LDR	X0, [SP, #296]

    (6) 0x410274 BL	5136c8

    (6) 0x410278 MOVZ	X1, #0

    (6) 0x41027c LDR	X0, [SP, #296]

    (6) 0x410280 BL	5136a4

    (6) 0x410284 LDR	X21, [SP, #320]

    (6) 0x410288 CMP	X21, #0

    (6) 0x41028c CCMP	W27, #0, #4, #0

    (6) 0x410290 B.NE	41060c

    (6) 0x410294 LDR	X0, [SP, #192]

    (6) 0x410298 BL	415d20

    (6) 0x41029c MOVI	D0, #0

    (6) 0x4102a0 LDR	X0, [SP, #304]

    (6) 0x4102a4 BL	415ec4

    (6) 0x4102a8 MOVZ	X1, #8

    (6) 0x4102ac LDR	X0, [SP, #304]

    (6) 0x4102b0 BL	415e48

    (6) 0x4102b4 MOVZ	X1, #8

    (6) 0x4102b8 LDR	X0, [SP, #304]

    (6) 0x4102bc BL	415e00

    (6) 0x4102c0 LDR	X1, [SP, #168]

    (6) 0x4102c4 LDR	X0, [SP, #304]

    (6) 0x4102c8 BL	4161b0

    (6) 0x4102cc MOVZ	X1, #1

    (6) 0x4102d0 LDR	X0, [SP, #304]

    (6) 0x4102d4 BL	415e40

    (6) 0x4102d8 MOVZ	X1, #2

    (6) 0x4102dc LDR	X0, [SP, #304]

    (6) 0x4102e0 BL	415ed0

    (6) 0x4102e4 MOVZ	X1, #18

    (6) 0x4102e8 LDR	X0, [SP, #304]

    (6) 0x4102ec BL	416164

    (6) 0x4102f0 MOVZ	X1, #0

    (6) 0x4102f4 LDR	X0, [SP, #304]

    (6) 0x4102f8 BL	4161c8

    (6) 0x4102fc MOVZ	X1, #1

    (6) 0x410300 LDR	X0, [SP, #304]

    (6) 0x410304 BL	416224

    (6) 0x410308 LDR	X1, [SP, #152]

    (6) 0x41030c LDR	X0, [SP, #304]

    (6) 0x410310 BL	4162cc

    (6) 0x410314 LDR	X1, [SP, #144]

    (6) 0x410318 LDR	X0, [SP, #304]

    (6) 0x41031c BL	4162d0

    (6) 0x410320 MOVZ	X1, #100

    (6) 0x410324 LDR	X0, [SP, #296]

    (6) 0x410328 BL	513688

    (6) 0x41032c ADRP	X5,

    (6) 0x410330 ADRP	X7,

    (6) 0x410334 LDP	X0, X3, [SP, #296]

    (6) 0x410338 LDR	X2, [X5, #3928]

    (6) 0x41033c LDR	X1, [X7, #4016]

    (6) 0x410340 BL	5136c0

    (6) 0x410344 LDR	X1, [SP, #200]

    (6) 0x410348 LDR	X0, [SP, #296]

    (6) 0x41034c BL	5136c4

    (6) 0x410350 LDP	X8, X9, [SP, #304]

    (6) 0x410354 CMP	X9, X8

    (6) 0x410358 B.NE	4107cc

    (6) 0x41035c LDR	X10, [SP, #320]

    (6) 0x410360 CBNZ	X10, 410554

    (6) 0x410364 LDR	X13, [SP, #168]

    (6) 0x410368 CBNZ	X13, 41061c

    (6) 0x41036c ORR	X3, XZR, X20

    (6) 0x410370 ORR	X2, XZR, X19

    (6) 0x410374 LDR	X0, [SP, #296]

    (6) 0x410378 ORR	X1, XZR, X24

    (6) 0x41037c ADD	X26, SP, #248

    (6) 0x410380 BL	513640

    (6) 0x410384 ADD	X1, SP, #384

    (6) 0x410388 LDR	X0, [SP, #304]

    (6) 0x41038c ADD	X25, SP, #256

    (6) 0x410390 BL	4161e4

    (6) 0x410394 LDP	D4, D5, [SP, #376]

    (6) 0x410398 ORR	X3, XZR, X20

    (6) 0x41039c ORR	X2, XZR, X19

    (6) 0x4103a0 ORR	X1, XZR, X24

    (6) 0x4103a4 LDR	X0, [SP, #296]

    (6) 0x4103a8 FADD	D6, D4, D5

    (6) 0x4103ac STR	D6, [SP, #376]

    (6) 0x4103b0 BL	513644

    (6) 0x4103b4 ORR	X1, XZR, X26

    (6) 0x4103b8 LDR	X0, [SP, #296]

    (6) 0x4103bc BL	5136e4

    (6) 0x4103c0 ORR	X1, XZR, X25

    (6) 0x4103c4 LDR	X0, [SP, #296]

    (6) 0x4103c8 BL	5136ec

    (6) 0x4103cc LDR	X4, [SP, #248]

    (6) 0x4103d0 ADRP	X16,

    (6) 0x4103d4 ADRP	X17,

    (6) 0x4103d8 ADD	X30, X17, #1912

    (6) 0x4103dc ADD	X28, X16, #3896

    (6) 0x4103e0 MOVZ	X21, #6

    (6) 0x4103e4 STR	X30, [SP, #176]

    (6) 0x4103e8 ADD	X22, X22, X4

      (5) 0x4103ec FMOV	D0, D8

      (5) 0x4103f0 MOVZ	X1, #1

      (5) 0x4103f4 ORR	X0, XZR, X23

      (5) 0x4103f8 BL	415bb0

      (5) 0x4103fc FMOV	D0, D8

      (5) 0x410400 ORR	X1, XZR, X19

      (5) 0x410404 ORR	X0, XZR, X20

      (5) 0x410408 BL	4d58cc

      (5) 0x41040c ORR	X1, XZR, X21

      (5) 0x410410 LDR	X0, [SP, #296]

      (5) 0x410414 BL	513688

      (5) 0x410418 MOVI	D0, #0

      (5) 0x41041c LDR	X0, [SP, #296]

      (5) 0x410420 BL	513650

      (5) 0x410424 ORR	X3, XZR, X20

      (5) 0x410428 ORR	X2, XZR, X19

      (5) 0x41042c LDR	X0, [SP, #296]

      (5) 0x410430 ORR	X1, XZR, X24

      (5) 0x410434 BL	513644

      (5) 0x410438 ORR	X1, XZR, X26

      (5) 0x41043c LDR	X0, [SP, #296]

      (5) 0x410440 BL	5136e4

      (5) 0x410444 ORR	X1, XZR, X25

      (5) 0x410448 LDR	X0, [SP, #296]

      (5) 0x41044c BL	5136ec

      (5) 0x410450 LDR	X0, [SP, #320]

      (5) 0x410454 CMP	X0, #0

      (5) 0x410458 CCMP	W27, #0, #4, #0

      (5) 0x41045c B.NE	410510

      (5) 0x410460 LDR	X1, [SP, #248]

      (5) 0x410464 SUB	X21, X21, #1

      (5) 0x410468 ADD	X22, X22, X1

      (5) 0x41046c CMP	X21, #2

      (5) 0x410470 B.NE	4103ec

    (6) 0x410474 LDR	X0, [SP, #304]

    (6) 0x410478 BL	415d80

    (6) 0x41047c LDR	X0, [SP, #296]

    (6) 0x410480 BL	4163e0

    (6) 0x410484 FSUB	D9, D9, S11

    (6) 0x410488 MOVZ	X1, #0

    (6) 0x41048c ORR	X0, XZR, X23

    (6) 0x410490 FMOV	D0, D9

    (6) 0x410494 BL	415bb0

    (6) 0x410498 MOVI	D0, #0

    (6) 0x41049c ORR	X0, XZR, X20

    (6) 0x4104a0 BL	4d58ac

    (6) 0x4104a4 FMOV	D0, #1.0000000

    (6) 0x4104a8 ORR	X0, XZR, X19

    (6) 0x4104ac BL	4d58ac

    (6) 0x4104b0 LDR	X7, [SP, #128]

    (6) 0x4104b4 SUBS	X8, X7, #1

    (6) 0x4104b8 STR	X8, [SP, #128]

    (6) 0x4104bc B.NE	410220

  (1) 0x4104c0 ADRP	X24,

  (1) 0x4104c4 ADRP	X27,

  (1) 0x4104c8 LDR	X19, [X24, #3856]

  (1) 0x4104cc ORR	X0, XZR, X19

  (1) 0x4104d0 BL	518688

  (1) 0x4104d4 LDR	X20, [SP, #216]

  (1) 0x4104d8 ORR	X0, XZR, X20

  (1) 0x4104dc BL	519f0c

  (1) 0x4104e0 LDR	X1, [SP, #160]

  (1) 0x4104e4 ORR	X2, XZR, X19

  (1) 0x4104e8 ADD	X0, X27, #1984

  (1) 0x4104ec BL	51a1e0

  (1) 0x4104f0 ORR	X0, XZR, X20

  (1) 0x4104f4 BL	519ccc

  (1) 0x4104f8 BL	519fe0

  (1) 0x4104fc LDR	X9, [SP, #320]

  (1) 0x410500 CBZ	X9, 41072c

  (1) 0x410504 LDP	D8, D9, [SP, #96]

  (1) 0x410508 LDP	D10, D11, [SP, #112]

  (1) 0x41050c B	40fd68

      (5) 0x410510 ORR	X0, XZR, X28

      (5) 0x410514 SUB	X21, X21, #1

      (5) 0x410518 BL	5169a0

      (5) 0x41051c LDR	X0, [SP, #176]

      (5) 0x410520 LDR	X1, [SP, #248]

      (5) 0x410524 BL	5169a0

      (5) 0x410528 LDR	D0, [SP, #256]

      (5) 0x41052c ADRP	X6,

      (5) 0x410530 ADD	X0, X6, #1936

      (5) 0x410534 BL	5169a0

      (5) 0x410538 ORR	X0, XZR, X28

      (5) 0x41053c BL	5169a0

      (5) 0x410540 LDR	X5, [SP, #248]

      (5) 0x410544 ADD	X22, X22, X5

      (5) 0x410548 CMP	X21, #2

      (5) 0x41054c B.NE	4103ec

    (6) 0x410550 B	410474

    (6) 0x410554 ORR	X3, XZR, X20

    (6) 0x410558 ORR	X2, XZR, X19

    (6) 0x41055c LDR	X0, [SP, #296]

    (6) 0x410560 ORR	X1, XZR, X24

    (6) 0x410564 ADD	X26, SP, #248

    (6) 0x410568 BL	513640

    (6) 0x41056c ADD	X1, SP, #384

    (6) 0x410570 LDR	X0, [SP, #304]

    (6) 0x410574 ADD	X25, SP, #256

    (6) 0x410578 BL	4161e4

    (6) 0x41057c LDP	D2, D1, [SP, #376]

    (6) 0x410580 ORR	X3, XZR, X20

    (6) 0x410584 ORR	X2, XZR, X19

    (6) 0x410588 ORR	X1, XZR, X24

    (6) 0x41058c LDR	X0, [SP, #296]

    (6) 0x410590 FADD	D3, D2, D1

    (6) 0x410594 STR	D3, [SP, #376]

    (6) 0x410598 BL	513644

    (6) 0x41059c ORR	X1, XZR, X26

    (6) 0x4105a0 LDR	X0, [SP, #296]

    (6) 0x4105a4 BL	5136e4

    (6) 0x4105a8 ORR	X1, XZR, X25

    (6) 0x4105ac LDR	X0, [SP, #296]

    (6) 0x4105b0 BL	5136ec

    (6) 0x4105b4 LDR	X11, [SP, #320]

    (6) 0x4105b8 CBNZ	X11, 4103cc

    (6) 0x4105bc LDR	X12, [SP, #168]

    (6) 0x4105c0 CBZ	X12, 4103cc

    (6) 0x4105c4 ADRP	X18,

    (6) 0x4105c8 ADD	X28, X18, #3896

    (6) 0x4105cc ORR	X0, XZR, X28

    (6) 0x4105d0 BL	5169a0

    (6) 0x4105d4 ADRP	X2,

    (6) 0x4105d8 LDR	X1, [SP, #248]

    (6) 0x4105dc ADD	X0, X2, #1912

    (6) 0x4105e0 BL	5169a0

    (6) 0x4105e4 LDR	D0, [SP, #256]

    (6) 0x4105e8 ADRP	X3,

    (6) 0x4105ec ADD	X0, X3, #1936

    (6) 0x4105f0 BL	5169a0

    (6) 0x4105f4 ORR	X0, XZR, X28

    (6) 0x4105f8 BL	5169a0

    (6) 0x4105fc B	4103cc

  (1) 0x410600 MOVZ	X4, #1

  (1) 0x410604 STR	D0, [X27]

  (1) 0x410608 B	40fc64

    (6) 0x41060c ADRP	X6,

    (6) 0x410610 ADD	X0, X6, #1808

    (6) 0x410614 BL	5169a0

    (6) 0x410618 B	410294

    (6) 0x41061c ADRP	X14,

    (6) 0x410620 ADD	X26, SP, #248

    (6) 0x410624 ADD	X0, X14, #1872

    (6) 0x410628 ADD	X25, SP, #256

    (6) 0x41062c BL	5169a0

    (6) 0x410630 ORR	X3, XZR, X20

    (6) 0x410634 ORR	X2, XZR, X19

    (6) 0x410638 LDR	X0, [SP, #296]

    (6) 0x41063c ORR	X1, XZR, X24

    (6) 0x410640 BL	513640

    (6) 0x410644 ADD	X1, SP, #384

    (6) 0x410648 LDR	X0, [SP, #304]

    (6) 0x41064c BL	4161e4

    (6) 0x410650 LDP	D7, D16, [SP, #376]

    (6) 0x410654 ORR	X3, XZR, X20

    (6) 0x410658 ORR	X2, XZR, X19

    (6) 0x41065c ORR	X1, XZR, X24

    (6) 0x410660 LDR	X0, [SP, #296]

    (6) 0x410664 FADD	D17, D7, D16

    (6) 0x410668 STR	D17, [SP, #376]

    (6) 0x41066c BL	513644

    (6) 0x410670 ORR	X1, XZR, X26

    (6) 0x410674 LDR	X0, [SP, #296]

    (6) 0x410678 BL	5136e4

    (6) 0x41067c ORR	X1, XZR, X25

    (6) 0x410680 LDR	X0, [SP, #296]

    (6) 0x410684 BL	5136ec

    (6) 0x410688 LDR	X15, [SP, #320]

    (6) 0x41068c CBZ	X15, 4105c4

    (6) 0x410690 B	4103cc

  (1) 0x410694 SCVTF	D30, D27

  (1) 0x410698 ADRP	X20,

  (1) 0x41069c ADD	X22, X20, #3896

  (1) 0x4106a0 ORR	X0, XZR, X22

  (1) 0x4106a4 FMUL	D31, D30, D29

  (1) 0x4106a8 FDIV	D8, D31, D28

  (1) 0x4106ac BL	5169a0

  (1) 0x4106b0 ADRP	X13,

  (1) 0x4106b4 LDR	X1, [SP, #248]

  (1) 0x4106b8 ADD	X0, X13, #1632

  (1) 0x4106bc BL	5169a0

  (1) 0x4106c0 LDR	D0, [SP, #256]

  (1) 0x4106c4 ADRP	X14,

  (1) 0x4106c8 ADD	X0, X14, #1656

  (1) 0x4106cc BL	5169a0

  (1) 0x4106d0 ORR	X0, XZR, X22

  (1) 0x4106d4 BL	5169a0

  (1) 0x4106d8 ADRP	X15,

  (1) 0x4106dc FMOV	D0, D8

  (1) 0x4106e0 MOVZ	W0, #1

  (1) 0x4106e4 ADD	X1, X15, #1696

  (1) 0x4106e8 BL	40f7c0

  (1) 0x4106ec FMOV	D0, #3.0000000

  (1) 0x4106f0 FMOV	D2, #0.2500000

  (1) 0x4106f4 ADRP	X18,

  (1) 0x4106f8 ADD	X1, X18, #1760

  (1) 0x4106fc MOVZ	W0, #1

  (1) 0x410700 FMADD	D1, D8, D0, D9

  (1) 0x410704 FMUL	D0, D1, D2

  (1) 0x410708 BL	40f7c0

  (1) 0x41070c LDP	D8, D9, [SP, #96]

  (1) 0x410710 B	40fd68

  (1) 0x410714 ADRP	X26,

  (1) 0x410718 FMOV	D0, D9

  (1) 0x41071c MOVZ	W0, #1

  (1) 0x410720 ADD	X1, X26, #1536

  (1) 0x410724 BL	40f7c0

  (1) 0x410728 B	4100cc

  (1) 0x41072c ADRP	X10,

  (1) 0x410730 ADD	X25, X22, #6

  (1) 0x410734 ADD	X26, X10, #3896

  (1) 0x410738 ORR	X0, XZR, X26

  (1) 0x41073c BL	5169a0

  (1) 0x410740 ADRP	X11,

  (1) 0x410744 MOVZ	X1, #6

  (1) 0x410748 ADD	X0, X11, #2032

  (1) 0x41074c BL	5169a0

  (1) 0x410750 ADRP	X12,

  (1) 0x410754 ORR	X1, XZR, X22

  (1) 0x410758 ADD	X0, X12, #2056

  (1) 0x41075c BL	5169a0

  (1) 0x410760 LDR	D0, [SP, #256]

  (1) 0x410764 ADRP	X13,

  (1) 0x410768 ADD	X0, X13, #1656

  (1) 0x41076c BL	5169a0

  (1) 0x410770 ORR	X0, XZR, X26

  (1) 0x410774 BL	5169a0

  (1) 0x410778 LDR	D19, [SP, #376]

  (1) 0x41077c FMOV	D18, #6.0000000

  (1) 0x410780 ADRP	X14,

  (1) 0x410784 ADD	X0, X14, #2088

  (1) 0x410788 FDIV	D20, D19, D18

  (1) 0x41078c STR	D20, [SP, #376]

  (1) 0x410790 BL	40f280

  (1) 0x410794 SCVTF	D21, X25

  (1) 0x410798 LDR	D23, [SP, #376]

  (1) 0x41079c ADRP	X15,

  (1) 0x4107a0 ADD	X1, X15, #2144

  (1) 0x4107a4 MOVZ	W0, #1

  (1) 0x4107a8 LDR	D22, [SP, #360]

  (1) 0x4107ac FMUL	D24, D21, D23

  (1) 0x4107b0 FDIV	D0, D24, D22

  (1) 0x4107b4 BL	40f7c0

  (1) 0x4107b8 ORR	X0, XZR, X26

  (1) 0x4107bc BL	5169a0

  (1) 0x4107c0 LDP	D8, D9, [SP, #96]

  (1) 0x4107c4 LDP	D10, D11, [SP, #112]

  (1) 0x4107c8 B	40fd68

  (1) 0x4107cc ADRP	X23,

  (1) 0x4107d0 ADD	X0, X23, #1832

  (1) 0x4107d4 BL	5169a0

  (1) 0x4107d8 MOVN	W0, #0

  (1) 0x4107dc LDP	D8, D9, [SP, #96]

  (1) 0x4107e0 LDP	D10, D11, [SP, #112]

  (1) 0x4107e4 B	40fd90

  (1) 0x4107e8 ADRP	X16,

  (1) 0x4107ec ADD	X0, X16, #1384

  (1) 0x4107f0 BL	5169a0

  (1) 0x4107f4 B	40ff7c

  (1) 0x4107f8 ADRP	X23,

  (1) 0x4107fc ADD	X0, X23, #1408

  (1) 0x410800 BL	5169a0

  (1) 0x410804 MOVN	W0, #0

  (1) 0x410808 B	40fd90

  (1) 0x41080c ADRP	X30,

  (1) 0x410810 ADD	X0, X30, #1456

  (1) 0x410814 BL	5169a0

  (1) 0x410818 B	410058

0x41081c ADRP	X0,

0x410820 STP	D8, D9, [SP, #96]

0x410824 ADRP	X27,

0x410828 ADD	X21, X0, #3896

0x41082c STP	D10, D11, [SP, #112]

0x410830 ADRP	X26,

0x410834 ORR	X0, XZR, X21

0x410838 ADRP	X25,

0x41083c BL	5169a0

0x410840 LDR	X5, [SP, #224]

0x410844 ADRP	X6,

0x410848 ADD	X0, X6, #536

0x41084c LDR	X1, [X5]

0x410850 BL	5169a0

0x410854 ORR	X0, XZR, X21

0x410858 BL	5169a0

0x41085c ADRP	X7,

0x410860 ADD	X0, X7, #560

0x410864 BL	5169a0

0x410868 ADRP	X8,

0x41086c ADD	X0, X8, #592

0x410870 BL	5169a0

0x410874 ADD	X0, X27, #656

0x410878 BL	5169a0

0x41087c ORR	X0, XZR, X21

0x410880 BL	5169a0

0x410884 ADRP	X9,

0x410888 ADD	X0, X9, #720

0x41088c BL	5169a0

0x410890 ORR	X0, XZR, X21

0x410894 BL	5169a0

0x410898 ADRP	X10,

0x41089c ADD	X0, X10, #800

0x4108a0 BL	5169a0

0x4108a4 ORR	X0, XZR, X21

0x4108a8 BL	5169a0

0x4108ac ADD	X0, X26, #864

0x4108b0 BL	5169a0

0x4108b4 ADRP	X11,

0x4108b8 ADD	X0, X11, #904

0x4108bc BL	5169a0

0x4108c0 ADRP	X12,

0x4108c4 ADD	X0, X12, #968

0x4108c8 BL	5169a0

0x4108cc ADD	X0, X25, #1040

0x4108d0 BL	5169a0

0x4108d4 ORR	X0, XZR, X21

0x4108d8 BL	5169a0

0x4108dc MOVZ	W0, #1

0x4108e0 BL	40f740

0x4108e4 STP	D8, D9, [SP, #96]

0x4108e8 STP	D10, D11, [SP, #112]

0x4108ec BL	40f2e0

0x4108f0 HINT	#0

0x4108f4 HINT	#0

0x4108f8 HINT	#0

0x4108fc HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	amg.c:58-599
Module	exec

The function is defined in:

/usr/include/stdlib.h:364
/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/test/amg.c:58,76,91,121,144-146,153,169-179,188-221,235-253,260-263,270-281,287-332,338-342,351-444,454-569,578-580,587-599
/usr/include/aarch64-linux-gnu/bits/stdio2.h:112

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 26.00 to 5.50 cycles (4.73x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 27% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 26.00 to 6.50 cycles (4.00x speedup).

Details

8% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 26.00 to 13.50 cycles (1.93x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 124 bytes. The binary function is storing 300 bytes.

General properties

nb instructions	167
loop length	668
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

20.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	23.50	23.50	26.00	26.00	26.00	26.00	2.00	2.00	0.00	0.00	13.33	13.33	13.33	10.00	10.00
cycles	23.50	23.50	26.00	26.00	26.00	26.00	2.00	2.00	0.00	0.00	13.33	13.33	13.33	10.00	10.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	20.38
Overall L1	26.00

Vectorization ratios

all	8%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 26.00 cycles. At this rate:

4% of peak load performance is reached (4.77 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
24% of peak store performance is reached (11.54 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40f800

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADRP X2, <54f800>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #624]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X3, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, SP, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X4, [X2, #3848]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X3, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W0, [SP, #236]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X0, SP, #236	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X3, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X3, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR XZR, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 518628 <hypre_MPI_Init>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X0, <54f850>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, SP, #320	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #3856]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 518744 <hypre_MPI_Comm_rank>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X20, [SP, #236]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 40f9fc <main+0x1fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X6, <51d870>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X28, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X7, X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X23, X6, #464	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X8, X7, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 40f94c <main+0x14c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X8, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 40f930 <main+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 40f91c <main+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 40f908 <main+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 40f8f4 <main+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X8, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 40f8e0 <main+0xe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X8, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 40f8cc <main+0xcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X1, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X28, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 40f6b0 <@plt_start@+0x4c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W0, 40fe68 <main+0x668>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X19, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X28, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 40f6b0 <@plt_start@+0x4c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W0, 40fe68 <main+0x668>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X19, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X28, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 40f6b0 <@plt_start@+0x4c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W0, 40fe68 <main+0x668>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X19, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X28, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 40f6b0 <@plt_start@+0x4c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W0, 40fe68 <main+0x668>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X19, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X28, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 40f6b0 <@plt_start@+0x4c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W0, 40fe68 <main+0x668>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X19, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X28, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 40f6b0 <@plt_start@+0x4c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W0, 40fe68 <main+0x668>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X19, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X28, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 40f6b0 <@plt_start@+0x4c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W0, 40fe68 <main+0x668>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X19, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 40f9f4 <main+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR XZR, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 40fa08 <main+0x208>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR XZR, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X28, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.NE 40fe28 <main+0x628>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X24, <51da0c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X27, <51da10>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X24, X24, #472	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X27, #488	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X21, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X16, XZR, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ X25, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP XZR, X16, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X16, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 40fa9c <main+0x29c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X5, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X25, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X21, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X1, XZR, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP XZR, X1, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X1, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X15, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 40fa08 <main+0x208>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X0, <51d81c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADRP X27, <51d824>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X21, X0, #3896	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADRP X26, <51d830>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X25, <51d838>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 5169a0 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X5, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X6, <51d844>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X6, #536	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 5169a0 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 5169a0 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X7, <51d85c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X7, #560	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 5169a0 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X8, <51d868>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X8, #592	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 5169a0 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X27, #656	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 5169a0 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 5169a0 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X9, <51d884>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X9, #720	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 5169a0 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 5169a0 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X10, <51d898>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X10, #800	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 5169a0 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 5169a0 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X26, #864	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 5169a0 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X11, <51d8b4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X11, #904	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 5169a0 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X12, <51d8c0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X12, #968	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 5169a0 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X25, #1040	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 5169a0 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 5169a0 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f740 <@plt_start@+0x550>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
BL 40f2e0 <@plt_start@+0xf0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0

Source file and lines	amg.c:58-599
Module	exec

The function is defined in:

/usr/include/stdlib.h:364
/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/test/amg.c:58,76,91,121,144-146,153,169-179,188-221,235-253,260-263,270-281,287-332,338-342,351-444,454-569,578-580,587-599
/usr/include/aarch64-linux-gnu/bits/stdio2.h:112

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 26.00 to 5.50 cycles (4.73x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

8% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 26.00 to 13.50 cycles (1.93x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 124 bytes. The binary function is storing 300 bytes.

General properties

nb instructions	167
loop length	668
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

20.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	23.50	23.50	26.00	26.00	26.00	26.00	2.00	2.00	0.00	0.00	13.33	13.33	13.33	10.00	10.00
cycles	23.50	23.50	26.00	26.00	26.00	26.00	2.00	2.00	0.00	0.00	13.33	13.33	13.33	10.00	10.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	20.38
Overall L1	26.00

Vectorization ratios

all	8%
load	NA (no load vectorizable/vectorized instructions)
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 26.00 cycles. At this rate:

4% of peak load performance is reached (4.77 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
24% of peak store performance is reached (11.54 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 40f800

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADRP X2, <54f800>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #624]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X3, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, SP, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X4, [X2, #3848]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X3, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W0, [SP, #236]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X0, SP, #236	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X3, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X3, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR XZR, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [SP, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 518628 <hypre_MPI_Init>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X0, <54f850>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, SP, #320	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #3856]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 518744 <hypre_MPI_Comm_rank>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDRSW X20, [SP, #236]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 40f9fc <main+0x1fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X6, <51d870>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X28, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X7, X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X23, X6, #464	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X8, X7, #4224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 40f94c <main+0x14c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X8, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 40f930 <main+0x130>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 40f91c <main+0x11c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 40f908 <main+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 40f8f4 <main+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X8, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 40f8e0 <main+0xe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X8, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 40f8cc <main+0xcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X1, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X28, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 40f6b0 <@plt_start@+0x4c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W0, 40fe68 <main+0x668>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X19, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X28, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 40f6b0 <@plt_start@+0x4c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W0, 40fe68 <main+0x668>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X19, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X28, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 40f6b0 <@plt_start@+0x4c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W0, 40fe68 <main+0x668>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X19, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X28, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 40f6b0 <@plt_start@+0x4c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W0, 40fe68 <main+0x668>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X19, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X28, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 40f6b0 <@plt_start@+0x4c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W0, 40fe68 <main+0x668>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X19, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X28, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 40f6b0 <@plt_start@+0x4c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W0, 40fe68 <main+0x668>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X19, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X28, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 40f6b0 <@plt_start@+0x4c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W0, 40fe68 <main+0x668>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X19, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 40f9f4 <main+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR XZR, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 40fa08 <main+0x208>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR XZR, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X28, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.NE 40fe28 <main+0x628>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X24, <51da0c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X27, <51da10>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X24, X24, #472	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X27, #488	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X21, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X16, XZR, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ X25, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP XZR, X16, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X16, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 40fa9c <main+0x29c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X5, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X25, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X21, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X1, XZR, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP XZR, X1, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X1, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X15, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 40fa08 <main+0x208>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X0, <51d81c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADRP X27, <51d824>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X21, X0, #3896	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADRP X26, <51d830>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X25, <51d838>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 5169a0 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X5, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X6, <51d844>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X6, #536	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 5169a0 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 5169a0 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X7, <51d85c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X7, #560	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 5169a0 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X8, <51d868>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X8, #592	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 5169a0 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X27, #656	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 5169a0 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 5169a0 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X9, <51d884>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X9, #720	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 5169a0 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 5169a0 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X10, <51d898>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X10, #800	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 5169a0 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 5169a0 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X26, #864	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 5169a0 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X11, <51d8b4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X11, #904	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 5169a0 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X12, <51d8c0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X12, #968	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 5169a0 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X25, #1040	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 5169a0 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 5169a0 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f740 <@plt_start@+0x550>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
BL 40f2e0 <@plt_start@+0xf0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼main–	0.01	0
▼Loop 0 - amg.c:76-599 - exec–	0	0
▼Loop 1 - amg.c:76-599 - exec–	0	0
○Loop 7 - amg.c:317-318 - exec	0.01	0.2
○Loop 3 - amg.c:188-221 - exec	0	0
▼Loop 2 - amg.c:188-204 - exec–	0	0
○Loop 4 - amg.c:188-204 - exec	0	0
▼Loop 6 - amg.c:462-551 - exec–	0	0
○Loop 5 - amg.c:521-539 - exec	0	0
○Loop 8 - amg.c:171-179 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code