OV - exec - Loop 710

0x433d2c LDR	X10, [X11, X17,LSL #3]

0x433d30 ADD	X0, X0, #1

0x433d34 CMP	X0, X10

0x433d38 B.GE	433e20

0x433d3c LDR	X10, [X12, X0,LSL #3]

0x433d40 LDR	X20, [X21]

0x433d44 LDR	X19, [X13, X10,LSL #3]

0x433d48 SUB	X20, X20, #1

0x433d4c CMP	X19, X20

0x433d50 B.NE	433d2c

0x433d54 ADD	X25, X10, #1

0x433d58 LDR	X19, [X2, X25,LSL #3]

0x433d5c CMP	X19, #1

0x433d60 B.LT	433dc0

0x433d64 LDR	X28, [X1, X10,LSL #3]

0x433d68 ADD	X20, X19, X28

0x433d6c B	433d8c

  (712) 0x433d80 ADD	X28, X28, #1

  (712) 0x433d84 CMP	X28, X20

  (712) 0x433d88 B.GE	433dc0

  (712) 0x433d8c LDR	X19, [X21]

  (712) 0x433d90 LDR	X24, [X26, X19,LSL #3]

  (712) 0x433d94 LDR	X24, [X24, X28,LSL #3]

  (712) 0x433d98 LDR	X27, [X22, X24,LSL #3]

  (712) 0x433d9c CMP	X27, X4

  (712) 0x433da0 B.EQ	433d80

  (712) 0x433da4 LDR	X19, [X3, X19,LSL #3]

  (712) 0x433da8 STR	X24, [X19, X8,LSL #3]

  (712) 0x433dac ADD	X8, X8, #1

  (712) 0x433db0 STR	X4, [X22, X24,LSL #3]

  (712) 0x433db4 B	433d80

0x433dc0 LDR	X19, [X6, X25,LSL #3]

0x433dc4 CMP	X19, #1

0x433dc8 B.LT	433d2c

0x433dcc LDR	X10, [X5, X10,LSL #3]

0x433dd0 ADD	X20, X19, X10

0x433dd4 B	433dec

  (711) 0x433de0 ADD	X10, X10, #1

  (711) 0x433de4 CMP	X10, X20

  (711) 0x433de8 B.GE	433d2c

  (711) 0x433dec LDR	X19, [X21]

  (711) 0x433df0 LDR	X24, [X30, X19,LSL #3]

  (711) 0x433df4 LDR	X24, [X24, X10,LSL #3]

  (711) 0x433df8 LDR	X25, [X23, X24,LSL #3]

  (711) 0x433dfc CMP	X25, X4

  (711) 0x433e00 B.EQ	433de0

  (711) 0x433e04 LDR	X19, [X7, X19,LSL #3]

  (711) 0x433e08 STR	X24, [X19, X9,LSL #3]

  (711) 0x433e0c ADD	X9, X9, #1

  (711) 0x433e10 STR	X4, [X23, X24,LSL #3]

  (711) 0x433e14 B	433de0

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1075 - 1099

--------------------------------------------------------------------------------

1075:              for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1076:              {

1077:                 j1 = S_diag_j[j];

1078:                 if (assigned[j1] == pass-1)

1079:                 {

1080:                    j_start = P_diag_start[j1];

1081:                    j_end = j_start+P_diag_i[j1+1];

1082:                    for (k=j_start; k < j_end; k++)

1083:                    {

1084:                       k1 = P_diag_pass[pass-1][k];

1085:                       if (P_marker[k1] != -i1-1)

1086:                       {

1087:                           P_diag_pass[pass][cnt_nz++] = k1;

1088:                           P_marker[k1] = -i1-1;

1089:                       }

1090:                    }

1091:                    j_start = P_offd_start[j1];

1092:                    j_end = j_start+P_offd_i[j1+1];

1093:                    for (k=j_start; k < j_end; k++)

1094:                    {

1095:                       k1 = P_offd_pass[pass-1][k];

1096:                       if (P_marker_offd[k1] != -i1-1)

1097:                       {

1098:                          P_offd_pass[pass][cnt_nz_offd++] = k1;

1099:                          P_marker_offd[k1] = -i1-1;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	P0, P1,
Function	.omp_outlined..12#0x433590
Source	par_multi_interp.c:1075-1078,par_multi_interp.c:1081-1082,par_multi_interp.c:1092-1093
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	0.75
Front-end cycles	2.88
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	2.25
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.67
P10 cycles	2.67
P11 cycles	2.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	23.00
Nb uops	23.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.33
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	P0, P1,
Function	.omp_outlined..12#0x433590
Source	par_multi_interp.c:1075-1078,par_multi_interp.c:1081-1082,par_multi_interp.c:1092-1093
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	0.75
Front-end cycles	2.88
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	2.25
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.67
P10 cycles	2.67
P11 cycles	2.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	23.00
Nb uops	23.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.33
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..12#0x433590
Source file and lines	par_multi_interp.c:1075-1099
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1075-1099.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1075-1078,1081-1082,1092-1093.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.75 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes.

General properties

nb instructions	23
loop length	92
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	2.67	2.67	2.67	0.00	0.00
cycles	3.00	3.00	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	2.67	2.67	2.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.88
Overall L1	3.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

22% of peak load performance is reached (21.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 433d3c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDR X10, [X11, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X0, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GE 433e20 <.omp_outlined..12+0x890>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X10, [X12, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X20, [X21]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X19, [X13, X10,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUB X20, X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X19, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.NE 433d2c <.omp_outlined..12+0x79c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X25, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X19, [X2, X25,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LT 433dc0 <.omp_outlined..12+0x830>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X28, [X1, X10,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X20, X19, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
B 433d8c <.omp_outlined..12+0x7fc>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X19, [X6, X25,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LT 433d2c <.omp_outlined..12+0x79c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X10, [X5, X10,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X20, X19, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
B 433dec <.omp_outlined..12+0x85c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..12#0x433590
Source file and lines	par_multi_interp.c:1075-1099
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1075-1099.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1075-1078,1081-1082,1092-1093.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.75 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes.

General properties

nb instructions	23
loop length	92
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	2.67	2.67	2.67	0.00	0.00
cycles	3.00	3.00	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	2.67	2.67	2.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.88
Overall L1	3.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

22% of peak load performance is reached (21.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 433d3c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDR X10, [X11, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X0, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GE 433e20 <.omp_outlined..12+0x890>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X10, [X12, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X20, [X21]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X19, [X13, X10,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUB X20, X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X19, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.NE 433d2c <.omp_outlined..12+0x79c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ADD X25, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X19, [X2, X25,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LT 433dc0 <.omp_outlined..12+0x830>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X28, [X1, X10,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X20, X19, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
B 433d8c <.omp_outlined..12+0x7fc>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X19, [X6, X25,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LT 433d2c <.omp_outlined..12+0x79c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X10, [X5, X10,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X20, X19, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
B 433dec <.omp_outlined..12+0x85c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code