OV - exec - Loop 60

	Loop Id: 60	Module: exec	Source: ams.c:3365-3540 [...]	Coverage: 0.04%

  (61) 0x473cc0 ORR	X3, XZR, XZR

  (61) 0x473cc4 ADRP	X0,

  (61) 0x473cc8 ADD	X0, X0, #4024

  (61) 0x473ccc MOVZ	W1, #3540

  (61) 0x473cd0 MOVZ	W2, #12

  (61) 0x473cd4 BL	4a5070

    (58) 0x473cd8 CMP	X28, X27

    (58) 0x473cdc ORR	X28, XZR, X19

    (58) 0x473ce0 B.EQ	474b8c

    (58) 0x473ce4 LDR	X8, [X23]

    (58) 0x473ce8 LDR	X9, [X24]

    (58) 0x473cec ADD	X19, X28, #1

    (58) 0x473cf0 SDIV	X10, X8, X9

    (58) 0x473cf4 MSUB	X8, X10, X9, X8

    (58) 0x473cf8 CMP	X28, X8

    (58) 0x473cfc MADD	X9, X10, X28, X8

    (58) 0x473d00 MADD	X11, X10, X19, X8

    (58) 0x473d04 ADD	X8, X10, #1

    (58) 0x473d08 MADD	X10, X8, X28, XZR

    (58) 0x473d0c MADD	X12, X8, X19, XZR

    (58) 0x473d10 CSEL	X8, X9, X10, #10

    (58) 0x473d14 LDR	X10, [X22]

    (58) 0x473d18 CSEL	X9, X11, X12, #10

    (58) 0x473d1c CMP	X10, #1

    (58) 0x473d20 B.EQ	4740e0

    (58) 0x473d24 CMP	X10, #2

    (58) 0x473d28 B.EQ	473f00

    (58) 0x473d2c CMP	X10, #3

    (58) 0x473d30 B.NE	474340

    (58) 0x473d34 CMP	X9, X8

    (58) 0x473d38 B.LE	474a80

    (58) 0x473d3c LDUR	X11, [X29, #456]

    (58) 0x473d40 LDP	X14, X10, [SP, #56]

    (58) 0x473d44 LDR	X13, [SP, #48]

    (58) 0x473d48 ORR	X0, XZR, X8

    (58) 0x473d4c LDR	X12, [X26]

    (58) 0x473d50 ADD	X16, X12, #16

    (58) 0x473d54 LDR	X11, [X11]

    (58) 0x473d58 LDR	X15, [X25]

    (58) 0x473d5c LDR	X10, [X10]

    (58) 0x473d60 LDR	X13, [X13]

    (58) 0x473d64 LDR	X14, [X14]

    (58) 0x473d68 ADD	X17, X15, #16

    (58) 0x473d6c LDR	X18, [X11, X8,LSL #3]

    (58) 0x473d70 B	473d88

      (83) 0x473d80 CMP	X0, X9

      (83) 0x473d84 B.EQ	474a80

      (83) 0x473d88 ORR	X1, XZR, X0

      (83) 0x473d8c STR	XZR, [X10, X0,LSL #3]

      (83) 0x473d90 ADD	X0, X0, #1

      (83) 0x473d94 ORR	X2, XZR, X18

      (83) 0x473d98 MOVI	D0, #0

      (83) 0x473d9c LDR	X18, [X11, X0,LSL #3]

      (83) 0x473da0 CMP	X18, X2

      (83) 0x473da4 B.LE	473e44

      (83) 0x473da8 SUB	W3, W18, W2

      (83) 0x473dac MOVI	D0, #0

      (83) 0x473db0 ANDS	X4, X3, #4160

      (83) 0x473db4 B.EQ	473dec

      (83) 0x473db8 ORR	X3, XZR, X2

      (83) 0x473dbc HINT	#0

        (87) 0x473dc0 LDR	D1, [X12, X3,LSL #3]

        (87) 0x473dc4 ADD	X3, X3, #1

        (87) 0x473dc8 SUBS	X4, X4, #1

        (87) 0x473dcc FMADD	D0, D1, D1, D0

        (87) 0x473dd0 STR	D0, [X10, X1,LSL #3]

        (87) 0x473dd4 B.NE	473dc0

      (83) 0x473dd8 ORN	X2, XZR, X2

      (83) 0x473ddc ADD	X2, X18, X2

      (83) 0x473de0 CMP	X2, #3

      (83) 0x473de4 B.CS	473e00

      (83) 0x473de8 B	473e44

      (83) 0x473dec ORR	X3, XZR, X2

      (83) 0x473df0 ORN	X2, XZR, X2

      (83) 0x473df4 ADD	X2, X18, X2

      (83) 0x473df8 CMP	X2, #3

      (83) 0x473dfc B.CC	473e44

      (83) 0x473e00 SUB	X2, X18, X3

      (83) 0x473e04 ADD	X3, X16, X3,LSL #3

        (86) 0x473e08 LDUR	D1, [X3, #496]

        (86) 0x473e0c SUBS	X2, X2, #4

        (86) 0x473e10 FMADD	D0, D1, D1, D0

        (86) 0x473e14 STR	D0, [X10, X1,LSL #3]

        (86) 0x473e18 LDUR	D1, [X3, #504]

        (86) 0x473e1c FMADD	D0, D1, D1, D0

        (86) 0x473e20 STR	D0, [X10, X1,LSL #3]

        (86) 0x473e24 LDR	D1, [X3]

        (86) 0x473e28 FMADD	D0, D1, D1, D0

        (86) 0x473e2c STR	D0, [X10, X1,LSL #3]

        (86) 0x473e30 LDR	D1, [X3, #8]

        (86) 0x473e34 ADD	X3, X3, #32

        (86) 0x473e38 FMADD	D0, D1, D1, D0

        (86) 0x473e3c STR	D0, [X10, X1,LSL #3]

        (86) 0x473e40 B.NE	473e08

      (83) 0x473e44 CBZ	X13, 473d80

      (83) 0x473e48 LDR	X3, [X14, X1,LSL #3]

      (83) 0x473e4c LDR	X2, [X14, X0,LSL #3]

      (83) 0x473e50 CMP	X2, X3

      (83) 0x473e54 B.LE	473d80

      (83) 0x473e58 SUB	W4, W2, W3

      (83) 0x473e5c ANDS	X5, X4, #4160

      (83) 0x473e60 B.EQ	473e94

      (83) 0x473e64 ORR	X4, XZR, X3

        (85) 0x473e68 LDR	D1, [X15, X4,LSL #3]

        (85) 0x473e6c ADD	X4, X4, #1

        (85) 0x473e70 SUBS	X5, X5, #1

        (85) 0x473e74 FMADD	D0, D1, D1, D0

        (85) 0x473e78 STR	D0, [X10, X1,LSL #3]

        (85) 0x473e7c B.NE	473e68

      (83) 0x473e80 ORN	X3, XZR, X3

      (83) 0x473e84 ADD	X3, X2, X3

      (83) 0x473e88 CMP	X3, #3

      (83) 0x473e8c B.CC	473d80

      (83) 0x473e90 B	473ea8

      (83) 0x473e94 ORR	X4, XZR, X3

      (83) 0x473e98 ORN	X3, XZR, X3

      (83) 0x473e9c ADD	X3, X2, X3

      (83) 0x473ea0 CMP	X3, #3

      (83) 0x473ea4 B.CC	473d80

      (83) 0x473ea8 SUB	X2, X2, X4

      (83) 0x473eac ADD	X3, X17, X4,LSL #3

      (83) 0x473eb0 HINT	#0

      (83) 0x473eb4 HINT	#0

      (83) 0x473eb8 HINT	#0

      (83) 0x473ebc HINT	#0

        (84) 0x473ec0 LDUR	D1, [X3, #496]

        (84) 0x473ec4 SUBS	X2, X2, #4

        (84) 0x473ec8 FMADD	D0, D1, D1, D0

        (84) 0x473ecc STR	D0, [X10, X1,LSL #3]

        (84) 0x473ed0 LDUR	D1, [X3, #504]

        (84) 0x473ed4 FMADD	D0, D1, D1, D0

        (84) 0x473ed8 STR	D0, [X10, X1,LSL #3]

        (84) 0x473edc LDR	D1, [X3]

        (84) 0x473ee0 FMADD	D0, D1, D1, D0

        (84) 0x473ee4 STR	D0, [X10, X1,LSL #3]

        (84) 0x473ee8 LDR	D1, [X3, #8]

        (84) 0x473eec ADD	X3, X3, #32

        (84) 0x473ef0 FMADD	D0, D1, D1, D0

        (84) 0x473ef4 STR	D0, [X10, X1,LSL #3]

        (84) 0x473ef8 B.NE	473ec0

      (83) 0x473efc B	473d80

    (58) 0x473f00 CMP	X9, X8

    (58) 0x473f04 B.LE	474a80

    (58) 0x473f08 LDP	X12, X11, [SP, #32]

    (58) 0x473f0c LDP	X14, X10, [SP, #56]

    (58) 0x473f10 LDR	X13, [SP, #48]

    (58) 0x473f14 LDR	X16, [X11]

    (58) 0x473f18 LDUR	X11, [X29, #456]

    (58) 0x473f1c LDR	X10, [X10]

    (58) 0x473f20 LDR	X12, [X12]

    (58) 0x473f24 LDR	X13, [X13]

    (58) 0x473f28 LDR	X14, [X14]

    (58) 0x473f2c LDR	X11, [X11]

    (58) 0x473f30 LDR	X15, [X11, X8,LSL #3]

    (58) 0x473f34 CBZ	X16, 4746a4

    (58) 0x473f38 LDP	X17, X18, [SP, #16]

    (58) 0x473f3c ORR	X1, XZR, X8

    (58) 0x473f40 LDR	X18, [X18]

    (58) 0x473f44 LDR	X17, [X17]

    (58) 0x473f48 ADD	X0, X18, #8

    (58) 0x473f4c B	473f6c

      (74) 0x473f60 ORR	X15, XZR, X3

      (74) 0x473f64 CMP	X1, X9

      (74) 0x473f68 B.EQ	474a80

      (74) 0x473f6c STR	XZR, [X10, X1,LSL #3]

      (74) 0x473f70 ORR	X2, XZR, X1

      (74) 0x473f74 MOVI	D0, #0

      (74) 0x473f78 LDR	X4, [X16, X1,LSL #3]

      (74) 0x473f7c ADD	X1, X1, #1

      (74) 0x473f80 LDR	X3, [X11, X1,LSL #3]

      (74) 0x473f84 CMP	X15, X3

      (74) 0x473f88 B.GE	473fec

      (74) 0x473f8c LDR	X5, [X26]

      (74) 0x473f90 UBFM	X6, X15, #61, #60

      (74) 0x473f94 SUB	X15, X3, X15

      (74) 0x473f98 MOVI	D0, #0

      (74) 0x473f9c ADD	X5, X5, X6

      (74) 0x473fa0 ADD	X6, X12, X6

      (74) 0x473fa4 B	473fb8

        (76) 0x473fa8 ADD	X5, X5, #8

        (76) 0x473fac SUBS	X15, X15, #1

        (76) 0x473fb0 ADD	X6, X6, #8

        (76) 0x473fb4 B.EQ	473fec

        (76) 0x473fb8 LDR	X7, [X6]

        (76) 0x473fbc CMP	X7, X2

        (76) 0x473fc0 CCMP	X7, X8, #8, #1

        (76) 0x473fc4 CCMP	X7, X9, #0, #10

        (76) 0x473fc8 B.LT	473fa8

        (76) 0x473fcc LDR	X7, [X16, X7,LSL #3]

        (76) 0x473fd0 CMP	X4, X7

        (76) 0x473fd4 B.NE	473fa8

        (76) 0x473fd8 LDR	D1, [X5]

        (76) 0x473fdc FABS	D1, D1

        (76) 0x473fe0 FADD	D0, D0, D1

        (76) 0x473fe4 STR	D0, [X10, X2,LSL #3]

        (76) 0x473fe8 B	473fa8

      (74) 0x473fec CBZ	X13, 473f60

      (74) 0x473ff0 LDR	X5, [X14, X2,LSL #3]

      (74) 0x473ff4 LDR	X15, [X14, X1,LSL #3]

      (74) 0x473ff8 CMP	X15, X5

      (74) 0x473ffc B.LE	473f60

      (74) 0x474000 LDR	X6, [X25]

      (74) 0x474004 SUB	W7, W15, W5

      (74) 0x474008 TBNZ	W7, #0, 474020

      (74) 0x47400c ORR	X7, XZR, X5

      (74) 0x474010 ADD	X5, X5, #1

      (74) 0x474014 CMP	X15, X5

      (74) 0x474018 B.EQ	473f60

      (74) 0x47401c B	474050

      (74) 0x474020 LDR	X7, [X18, X5,LSL #3]

      (74) 0x474024 LDR	X7, [X17, X7,LSL #3]

      (74) 0x474028 CMP	X4, X7

      (74) 0x47402c B.NE	474040

      (74) 0x474030 LDR	D1, [X6, X5,LSL #3]

      (74) 0x474034 FABS	D1, D1

      (74) 0x474038 FADD	D0, D0, D1

      (74) 0x47403c STR	D0, [X10, X2,LSL #3]

      (74) 0x474040 ADD	X7, X5, #1

      (74) 0x474044 ADD	X5, X5, #1

      (74) 0x474048 CMP	X15, X5

      (74) 0x47404c B.EQ	473f60

      (74) 0x474050 SUB	X15, X15, X7

      (74) 0x474054 UBFM	X7, X7, #61, #60

      (74) 0x474058 ADD	X6, X6, X7

      (74) 0x47405c ADD	X5, X0, X7

      (74) 0x474060 ADD	X6, X6, #8

      (74) 0x474064 B	474078

        (75) 0x474068 SUBS	X15, X15, #2

        (75) 0x47406c ADD	X5, X5, #16

        (75) 0x474070 ADD	X6, X6, #16

        (75) 0x474074 B.EQ	473f60

        (75) 0x474078 LDUR	X7, [X5, #504]

        (75) 0x47407c LDR	X7, [X17, X7,LSL #3]

        (75) 0x474080 CMP	X4, X7

        (75) 0x474084 B.EQ	4740a0

        (75) 0x474088 LDR	X7, [X5]

        (75) 0x47408c LDR	X7, [X17, X7,LSL #3]

        (75) 0x474090 CMP	X4, X7

        (75) 0x474094 B.NE	474068

        (75) 0x474098 B	4740c0

        (75) 0x4740a0 LDUR	D1, [X6, #504]

        (75) 0x4740a4 FABS	D1, D1

        (75) 0x4740a8 FADD	D0, D0, D1

        (75) 0x4740ac STR	D0, [X10, X2,LSL #3]

        (75) 0x4740b0 LDR	X7, [X5]

        (75) 0x4740b4 LDR	X7, [X17, X7,LSL #3]

        (75) 0x4740b8 CMP	X4, X7

        (75) 0x4740bc B.NE	474068

        (75) 0x4740c0 LDR	D1, [X6]

        (75) 0x4740c4 FABS	D1, D1

        (75) 0x4740c8 FADD	D0, D0, D1

        (75) 0x4740cc STR	D0, [X10, X2,LSL #3]

        (75) 0x4740d0 B	474068

    (58) 0x4740e0 CMP	X9, X8

    (58) 0x4740e4 B.LE	474a80

    (58) 0x4740e8 LDP	X11, X12, [SP, #40]

    (58) 0x4740ec LDP	X13, X10, [SP, #56]

    (58) 0x4740f0 LDR	X15, [X11]

    (58) 0x4740f4 LDUR	X11, [X29, #456]

    (58) 0x4740f8 LDR	X10, [X10]

    (58) 0x4740fc LDR	X12, [X12]

    (58) 0x474100 LDR	X13, [X13]

    (58) 0x474104 LDR	X11, [X11]

    (58) 0x474108 LDR	X14, [X11, X8,LSL #3]

    (58) 0x47410c CBZ	X15, 4748b0

    (58) 0x474110 LDP	X18, X16, [SP, #24]

    (58) 0x474114 LDR	X17, [SP, #16]

    (58) 0x474118 ORR	X2, XZR, X8

    (58) 0x47411c LDR	X16, [X16]

    (58) 0x474120 LDR	X18, [X18]

    (58) 0x474124 LDR	X17, [X17]

    (58) 0x474128 ADD	X0, X16, #8

    (58) 0x47412c ADD	X1, X18, #8

    (58) 0x474130 B	474148

      (67) 0x474140 CMP	X2, X9

      (67) 0x474144 B.EQ	474a80

      (67) 0x474148 STR	XZR, [X10, X2,LSL #3]

      (67) 0x47414c ORR	X3, XZR, X2

      (67) 0x474150 ORR	X5, XZR, X14

      (67) 0x474154 MOVI	D0, #0

      (67) 0x474158 LDR	X4, [X15, X2,LSL #3]

      (67) 0x47415c ADD	X2, X2, #1

      (67) 0x474160 LDR	X14, [X11, X2,LSL #3]

      (67) 0x474164 CMP	X14, X5

      (67) 0x474168 B.LE	4741b0

      (67) 0x47416c LDR	X7, [X26]

      (67) 0x474170 SUB	W30, W14, W5

      (67) 0x474174 MOVI	D0, #0

      (67) 0x474178 ORR	X6, XZR, X5

      (67) 0x47417c TBZ	W30, #0, 4741a4

      (67) 0x474180 LDR	X6, [X16, X5,LSL #3]

      (67) 0x474184 MOVI	D0, #0

      (67) 0x474188 LDR	X6, [X15, X6,LSL #3]

      (67) 0x47418c CMP	X4, X6

      (67) 0x474190 B.NE	4741a0

      (67) 0x474194 LDR	D0, [X7, X5,LSL #3]

      (67) 0x474198 FABS	D0, D0

      (67) 0x47419c STR	D0, [X10, X3,LSL #3]

      (67) 0x4741a0 ADD	X6, X5, #1

      (67) 0x4741a4 ADD	X5, X5, #1

      (67) 0x4741a8 CMP	X14, X5

      (67) 0x4741ac B.NE	4741e4

      (67) 0x4741b0 CBZ	X12, 474140

      (67) 0x4741b4 LDR	X6, [X13, X3,LSL #3]

      (67) 0x4741b8 LDR	X5, [X13, X2,LSL #3]

      (67) 0x4741bc CMP	X5, X6

      (67) 0x4741c0 B.LE	474140

      (67) 0x4741c4 LDR	X7, [X25]

      (67) 0x4741c8 SUB	W30, W5, W6

      (67) 0x4741cc TBNZ	W30, #0, 474274

      (67) 0x4741d0 ORR	X30, XZR, X6

      (67) 0x4741d4 ADD	X6, X6, #1

      (67) 0x4741d8 CMP	X5, X6

      (67) 0x4741dc B.EQ	474140

      (67) 0x4741e0 B	4742a4

      (67) 0x4741e4 UBFM	X30, X6, #61, #60

      (67) 0x4741e8 SUB	X5, X14, X6

      (67) 0x4741ec ADD	X7, X7, X30

      (67) 0x4741f0 ADD	X6, X0, X30

      (67) 0x4741f4 ADD	X7, X7, #8

      (67) 0x4741f8 B	474210

        (69) 0x474200 SUBS	X5, X5, #2

        (69) 0x474204 ADD	X6, X6, #16

        (69) 0x474208 ADD	X7, X7, #16

        (69) 0x47420c B.EQ	4741b0

        (69) 0x474210 LDUR	X30, [X6, #504]

        (69) 0x474214 LDR	X30, [X15, X30,LSL #3]

        (69) 0x474218 CMP	X4, X30

        (69) 0x47421c B.EQ	474240

        (69) 0x474220 LDR	X30, [X6]

        (69) 0x474224 LDR	X30, [X15, X30,LSL #3]

        (69) 0x474228 CMP	X4, X30

        (69) 0x47422c B.NE	474200

        (69) 0x474230 B	474260

        (69) 0x474240 LDUR	D1, [X7, #504]

        (69) 0x474244 FABS	D1, D1

        (69) 0x474248 FADD	D0, D0, D1

        (69) 0x47424c STR	D0, [X10, X3,LSL #3]

        (69) 0x474250 LDR	X30, [X6]

        (69) 0x474254 LDR	X30, [X15, X30,LSL #3]

        (69) 0x474258 CMP	X4, X30

        (69) 0x47425c B.NE	474200

        (69) 0x474260 LDR	D1, [X7]

        (69) 0x474264 FABS	D1, D1

        (69) 0x474268 FADD	D0, D0, D1

        (69) 0x47426c STR	D0, [X10, X3,LSL #3]

        (69) 0x474270 B	474200

      (67) 0x474274 LDR	X30, [X18, X6,LSL #3]

      (67) 0x474278 LDR	X30, [X17, X30,LSL #3]

      (67) 0x47427c CMP	X4, X30

      (67) 0x474280 B.NE	474294

      (67) 0x474284 LDR	D1, [X7, X6,LSL #3]

      (67) 0x474288 FABS	D1, D1

      (67) 0x47428c FADD	D0, D0, D1

      (67) 0x474290 STR	D0, [X10, X3,LSL #3]

      (67) 0x474294 ADD	X30, X6, #1

      (67) 0x474298 ADD	X6, X6, #1

      (67) 0x47429c CMP	X5, X6

      (67) 0x4742a0 B.EQ	474140

      (67) 0x4742a4 SUB	X5, X5, X30

      (67) 0x4742a8 UBFM	X30, X30, #61, #60

      (67) 0x4742ac ADD	X7, X7, X30

      (67) 0x4742b0 ADD	X6, X1, X30

      (67) 0x4742b4 ADD	X7, X7, #8

      (67) 0x4742b8 B	4742d0

        (68) 0x4742c0 SUBS	X5, X5, #2

        (68) 0x4742c4 ADD	X6, X6, #16

        (68) 0x4742c8 ADD	X7, X7, #16

        (68) 0x4742cc B.EQ	474140

        (68) 0x4742d0 LDUR	X30, [X6, #504]

        (68) 0x4742d4 LDR	X30, [X17, X30,LSL #3]

        (68) 0x4742d8 CMP	X4, X30

        (68) 0x4742dc B.EQ	474300

        (68) 0x4742e0 LDR	X30, [X6]

        (68) 0x4742e4 LDR	X30, [X17, X30,LSL #3]

        (68) 0x4742e8 CMP	X4, X30

        (68) 0x4742ec B.NE	4742c0

        (68) 0x4742f0 B	474320

        (68) 0x474300 LDUR	D1, [X7, #504]

        (68) 0x474304 FABS	D1, D1

        (68) 0x474308 FADD	D0, D0, D1

        (68) 0x47430c STR	D0, [X10, X3,LSL #3]

        (68) 0x474310 LDR	X30, [X6]

        (68) 0x474314 LDR	X30, [X17, X30,LSL #3]

        (68) 0x474318 CMP	X4, X30

        (68) 0x47431c B.NE	4742c0

        (68) 0x474320 LDR	D1, [X7]

        (68) 0x474324 FABS	D1, D1

        (68) 0x474328 FADD	D0, D0, D1

        (68) 0x47432c STR	D0, [X10, X3,LSL #3]

        (68) 0x474330 B	4742c0

    (58) 0x474340 CMP	X10, #4

    (58) 0x474344 B.NE	474a80

    (58) 0x474348 CMP	X9, X8

    (58) 0x47434c B.LE	474a80

    (58) 0x474350 LDP	X16, X17, [SP, #16]

    (58) 0x474354 LDP	X15, X10, [SP, #56]

    (58) 0x474358 LDP	X13, X11, [SP, #32]

    (58) 0x47435c ORR	X2, XZR, X8

    (58) 0x474360 LDUR	X12, [X29, #456]

    (58) 0x474364 LDR	X14, [SP, #48]

    (58) 0x474368 LDR	X18, [X25]

    (58) 0x47436c ADD	X1, X18, #16

    (58) 0x474370 LDR	X17, [X17]

    (58) 0x474374 LDR	X10, [X10]

    (58) 0x474378 LDR	X11, [X11]

    (58) 0x47437c LDR	X12, [X12]

    (58) 0x474380 LDR	X13, [X13]

    (58) 0x474384 LDR	X14, [X14]

    (58) 0x474388 LDR	X15, [X15]

    (58) 0x47438c LDR	X16, [X16]

    (58) 0x474390 ADD	X0, X17, #8

    (58) 0x474394 B	4743ac

      (77) 0x4743a0 ADD	X2, X2, #1

      (77) 0x4743a4 CMP	X2, X9

      (77) 0x4743a8 B.EQ	474a80

      (77) 0x4743ac STR	XZR, [X10, X2,LSL #3]

      (77) 0x4743b0 CBZ	X11, 474480

      (77) 0x4743b4 ADD	X4, X2, #1

      (77) 0x4743b8 LDR	X6, [X12, X2,LSL #3]

      (77) 0x4743bc LDR	X3, [X11, X2,LSL #3]

      (77) 0x4743c0 MOVI	D0, #0

      (77) 0x4743c4 LDR	X7, [X12, X4,LSL #3]

      (77) 0x4743c8 CMP	X6, X7

      (77) 0x4743cc B.GE	474440

      (77) 0x4743d0 LDR	X5, [X26]

      (77) 0x4743d4 UBFM	X30, X6, #61, #60

      (77) 0x4743d8 SUB	X6, X7, X6

      (77) 0x4743dc MOVI	D0, #0

      (77) 0x4743e0 ADD	X7, X13, X30

      (77) 0x4743e4 ADD	X5, X5, X30

      (77) 0x4743e8 B	4743fc

        (82) 0x4743ec ADD	X5, X5, #8

        (82) 0x4743f0 SUBS	X6, X6, #1

        (82) 0x4743f4 ADD	X7, X7, #8

        (82) 0x4743f8 B.EQ	474440

        (82) 0x4743fc LDR	X30, [X7]

        (82) 0x474400 CMP	X30, X2

        (82) 0x474404 CCMP	X30, X8, #8, #1

        (82) 0x474408 CCMP	X30, X9, #0, #10

        (82) 0x47440c B.LT	4743ec

        (82) 0x474410 LDR	X21, [X11, X30,LSL #3]

        (82) 0x474414 CMP	X3, X21

        (82) 0x474418 B.NE	4743ec

        (82) 0x47441c LDR	D1, [X5]

        (82) 0x474420 CMP	X30, X2

        (82) 0x474424 FABS	D1, D1

        (82) 0x474428 FMADD	D2, D1, D8, D0

        (82) 0x47442c FADD	D0, D0, D1

        (82) 0x474430 FCSEL	D9, D9, D1, #1

        (82) 0x474434 FCSEL	D0, D2, D0, #1

        (82) 0x474438 STR	D0, [X10, X2,LSL #3]

        (82) 0x47443c B	4743ec

      (77) 0x474440 CBZ	X14, 47468c

      (77) 0x474444 LDR	X5, [X15, X2,LSL #3]

      (77) 0x474448 LDR	X4, [X15, X4,LSL #3]

      (77) 0x47444c CMP	X4, X5

      (77) 0x474450 B.LE	47468c

      (77) 0x474454 LDR	X6, [X25]

      (77) 0x474458 SUB	W7, W4, W5

      (77) 0x47445c TBNZ	W7, #0, 47455c

      (77) 0x474460 ORR	X7, XZR, X5

      (77) 0x474464 ADD	X5, X5, #1

      (77) 0x474468 CMP	X4, X5

      (77) 0x47446c B.NE	47458c

      (77) 0x474470 B	47468c

      (77) 0x474480 ADD	X3, X2, #1

      (77) 0x474484 LDR	X5, [X12, X2,LSL #3]

      (77) 0x474488 MOVI	D0, #0

      (77) 0x47448c LDR	X4, [X12, X3,LSL #3]

      (77) 0x474490 CMP	X5, X4

      (77) 0x474494 B.GE	474508

      (77) 0x474498 LDR	X6, [X26]

      (77) 0x47449c UBFM	X7, X5, #61, #60

      (77) 0x4744a0 SUB	X4, X4, X5

      (77) 0x4744a4 MOVI	D0, #0

      (77) 0x4744a8 ADD	X5, X6, X7

      (77) 0x4744ac ADD	X6, X13, X7

      (77) 0x4744b0 B	4744d0

        (80) 0x4744c0 SUBS	X4, X4, #1

        (80) 0x4744c4 ADD	X5, X5, #8

        (80) 0x4744c8 ADD	X6, X6, #8

        (80) 0x4744cc B.EQ	474508

        (80) 0x4744d0 LDR	X7, [X6]

        (80) 0x4744d4 CMP	X7, X2

        (80) 0x4744d8 CCMP	X7, X8, #8, #1

        (80) 0x4744dc CCMP	X7, X9, #0, #10

        (80) 0x4744e0 B.LT	4744c0

        (80) 0x4744e4 LDR	D1, [X5]

        (80) 0x4744e8 CMP	X7, X2

        (80) 0x4744ec FABS	D1, D1

        (80) 0x4744f0 FMADD	D2, D1, D8, D0

        (80) 0x4744f4 FADD	D0, D0, D1

        (80) 0x4744f8 FCSEL	D9, D9, D1, #1

        (80) 0x4744fc FCSEL	D0, D2, D0, #1

        (80) 0x474500 STR	D0, [X10, X2,LSL #3]

        (80) 0x474504 B	4744c0

      (77) 0x474508 CBZ	X14, 47468c

      (77) 0x47450c LDR	X4, [X15, X2,LSL #3]

      (77) 0x474510 LDR	X3, [X15, X3,LSL #3]

      (77) 0x474514 CMP	X3, X4

      (77) 0x474518 B.LE	47468c

      (77) 0x47451c SUB	W5, W3, W4

      (77) 0x474520 ANDS	X6, X5, #4160

      (77) 0x474524 B.EQ	474614

      (77) 0x474528 ORR	X5, XZR, X4

        (79) 0x47452c LDR	D1, [X18, X5,LSL #3]

        (79) 0x474530 ADD	X5, X5, #1

        (79) 0x474534 SUBS	X6, X6, #1

        (79) 0x474538 FABS	D1, D1

        (79) 0x47453c FMADD	D0, D1, D8, D0

        (79) 0x474540 STR	D0, [X10, X2,LSL #3]

        (79) 0x474544 B.NE	47452c

      (77) 0x474548 ORN	X4, XZR, X4

      (77) 0x47454c ADD	X4, X3, X4

      (77) 0x474550 CMP	X4, #3

      (77) 0x474554 B.CS	474628

      (77) 0x474558 B	47468c

      (77) 0x47455c LDR	X7, [X17, X5,LSL #3]

      (77) 0x474560 LDR	X7, [X16, X7,LSL #3]

      (77) 0x474564 CMP	X3, X7

      (77) 0x474568 B.NE	47457c

      (77) 0x47456c LDR	D1, [X6, X5,LSL #3]

      (77) 0x474570 FABS	D1, D1

      (77) 0x474574 FMADD	D0, D1, D8, D0

      (77) 0x474578 STR	D0, [X10, X2,LSL #3]

      (77) 0x47457c ADD	X7, X5, #1

      (77) 0x474580 ADD	X5, X5, #1

      (77) 0x474584 CMP	X4, X5

      (77) 0x474588 B.EQ	47468c

      (77) 0x47458c SUB	X4, X4, X7

      (77) 0x474590 UBFM	X7, X7, #61, #60

      (77) 0x474594 ADD	X6, X6, X7

      (77) 0x474598 ADD	X5, X0, X7

      (77) 0x47459c ADD	X6, X6, #8

      (77) 0x4745a0 B	4745b4

        (81) 0x4745a4 SUBS	X4, X4, #2

        (81) 0x4745a8 ADD	X5, X5, #16

        (81) 0x4745ac ADD	X6, X6, #16

        (81) 0x4745b0 B.EQ	47468c

        (81) 0x4745b4 LDUR	X7, [X5, #504]

        (81) 0x4745b8 LDR	X7, [X16, X7,LSL #3]

        (81) 0x4745bc CMP	X3, X7

        (81) 0x4745c0 B.EQ	4745e0

        (81) 0x4745c4 LDR	X7, [X5]

        (81) 0x4745c8 LDR	X7, [X16, X7,LSL #3]

        (81) 0x4745cc CMP	X3, X7

        (81) 0x4745d0 B.NE	4745a4

        (81) 0x4745d4 B	474600

        (81) 0x4745e0 LDUR	D1, [X6, #504]

        (81) 0x4745e4 FABS	D1, D1

        (81) 0x4745e8 FMADD	D0, D1, D8, D0

        (81) 0x4745ec STR	D0, [X10, X2,LSL #3]

        (81) 0x4745f0 LDR	X7, [X5]

        (81) 0x4745f4 LDR	X7, [X16, X7,LSL #3]

        (81) 0x4745f8 CMP	X3, X7

        (81) 0x4745fc B.NE	4745a4

        (81) 0x474600 LDR	D1, [X6]

        (81) 0x474604 FABS	D1, D1

        (81) 0x474608 FMADD	D0, D1, D8, D0

        (81) 0x47460c STR	D0, [X10, X2,LSL #3]

        (81) 0x474610 B	4745a4

      (77) 0x474614 ORR	X5, XZR, X4

      (77) 0x474618 ORN	X4, XZR, X4

      (77) 0x47461c ADD	X4, X3, X4

      (77) 0x474620 CMP	X4, #3

      (77) 0x474624 B.CC	47468c

      (77) 0x474628 SUB	X3, X3, X5

      (77) 0x47462c ADD	X4, X1, X5,LSL #3

      (77) 0x474630 HINT	#0

      (77) 0x474634 HINT	#0

      (77) 0x474638 HINT	#0

      (77) 0x47463c HINT	#0

        (78) 0x474640 LDUR	D1, [X4, #496]

        (78) 0x474644 SUBS	X3, X3, #4

        (78) 0x474648 FABS	D1, D1

        (78) 0x47464c FMADD	D0, D1, D8, D0

        (78) 0x474650 STR	D0, [X10, X2,LSL #3]

        (78) 0x474654 LDUR	D1, [X4, #504]

        (78) 0x474658 FABS	D1, D1

        (78) 0x47465c FMADD	D0, D1, D8, D0

        (78) 0x474660 STR	D0, [X10, X2,LSL #3]

        (78) 0x474664 LDR	D1, [X4]

        (78) 0x474668 FABS	D1, D1

        (78) 0x47466c FMADD	D0, D1, D8, D0

        (78) 0x474670 STR	D0, [X10, X2,LSL #3]

        (78) 0x474674 LDR	D1, [X4, #8]

        (78) 0x474678 ADD	X4, X4, #32

        (78) 0x47467c FABS	D1, D1

        (78) 0x474680 FMADD	D0, D1, D8, D0

        (78) 0x474684 STR	D0, [X10, X2,LSL #3]

        (78) 0x474688 B.NE	474640

      (77) 0x47468c FMOV	D1, X20

      (77) 0x474690 FMUL	D1, D9, D1

      (77) 0x474694 FCMP	D0, D1

      (77) 0x474698 B.HI	4743a0

      (77) 0x47469c STR	D9, [X10, X2,LSL #3]

      (77) 0x4746a0 B	4743a0

    (58) 0x4746a4 LDR	X16, [X25]

    (58) 0x4746a8 ORR	X0, XZR, X8

    (58) 0x4746ac ADD	X17, X12, #8

    (58) 0x4746b0 ADD	X18, X16, #16

    (58) 0x4746b4 B	4746c8

      (70) 0x4746c0 CMP	X0, X9

      (70) 0x4746c4 B.EQ	474a80

      (70) 0x4746c8 ORR	X1, XZR, X0

      (70) 0x4746cc STR	XZR, [X10, X0,LSL #3]

      (70) 0x4746d0 ADD	X0, X0, #1

      (70) 0x4746d4 ORR	X2, XZR, X15

      (70) 0x4746d8 MOVI	D0, #0

      (70) 0x4746dc LDR	X15, [X11, X0,LSL #3]

      (70) 0x4746e0 CMP	X15, X2

      (70) 0x4746e4 B.LE	474730

      (70) 0x4746e8 LDR	X3, [X26]

      (70) 0x4746ec SUB	W5, W15, W2

      (70) 0x4746f0 MOVI	D0, #0

      (70) 0x4746f4 ORR	X4, XZR, X2

      (70) 0x4746f8 TBZ	W5, #0, 474724

      (70) 0x4746fc LDR	X4, [X12, X2,LSL #3]

      (70) 0x474700 MOVI	D0, #0

      (70) 0x474704 CMP	X4, X1

      (70) 0x474708 CCMP	X4, X8, #8, #1

      (70) 0x47470c CCMP	X4, X9, #0, #10

      (70) 0x474710 B.LT	474720

      (70) 0x474714 LDR	D0, [X3, X2,LSL #3]

      (70) 0x474718 FABS	D0, D0

      (70) 0x47471c STR	D0, [X10, X1,LSL #3]

      (70) 0x474720 ADD	X4, X2, #1

      (70) 0x474724 ADD	X2, X2, #1

      (70) 0x474728 CMP	X15, X2

      (70) 0x47472c B.NE	4747a0

      (70) 0x474730 CBZ	X13, 4746c0

      (70) 0x474734 LDR	X3, [X14, X1,LSL #3]

      (70) 0x474738 LDR	X2, [X14, X0,LSL #3]

      (70) 0x47473c CMP	X2, X3

      (70) 0x474740 B.LE	4746c0

      (70) 0x474744 SUB	W4, W2, W3

      (70) 0x474748 ANDS	X5, X4, #4160

      (70) 0x47474c B.EQ	474838

      (70) 0x474750 ORR	X4, XZR, X3

      (70) 0x474754 HINT	#0

      (70) 0x474758 HINT	#0

      (70) 0x47475c HINT	#0

        (72) 0x474760 LDR	D1, [X16, X4,LSL #3]

        (72) 0x474764 ADD	X4, X4, #1

        (72) 0x474768 SUBS	X5, X5, #1

        (72) 0x47476c FABS	D1, D1

        (72) 0x474770 FADD	D0, D0, D1

        (72) 0x474774 STR	D0, [X10, X1,LSL #3]

        (72) 0x474778 B.NE	474760

      (70) 0x47477c ORN	X3, XZR, X3

      (70) 0x474780 ADD	X3, X2, X3

      (70) 0x474784 CMP	X3, #3

      (70) 0x474788 B.CC	4746c0

      (70) 0x47478c B	47484c

      (70) 0x4747a0 SUB	X2, X15, X4

      (70) 0x4747a4 UBFM	X4, X4, #61, #60

      (70) 0x4747a8 ADD	X3, X3, X4

      (70) 0x4747ac ADD	X4, X17, X4

      (70) 0x4747b0 ADD	X3, X3, #8

      (70) 0x4747b4 B	4747d0

        (73) 0x4747c0 SUBS	X2, X2, #2

        (73) 0x4747c4 ADD	X3, X3, #16

        (73) 0x4747c8 ADD	X4, X4, #16

        (73) 0x4747cc B.EQ	474730

        (73) 0x4747d0 LDUR	X5, [X4, #504]

        (73) 0x4747d4 CMP	X5, X1

        (73) 0x4747d8 CCMP	X5, X8, #8, #1

        (73) 0x4747dc CCMP	X5, X9, #0, #10

        (73) 0x4747e0 B.GE	474800

        (73) 0x4747e4 LDR	X5, [X4]

        (73) 0x4747e8 CMP	X5, X1

        (73) 0x4747ec CCMP	X5, X8, #8, #1

        (73) 0x4747f0 CCMP	X5, X9, #0, #10

        (73) 0x4747f4 B.LT	4747c0

        (73) 0x4747f8 B	474824

        (73) 0x474800 LDUR	D1, [X3, #504]

        (73) 0x474804 FABS	D1, D1

        (73) 0x474808 FADD	D0, D0, D1

        (73) 0x47480c STR	D0, [X10, X1,LSL #3]

        (73) 0x474810 LDR	X5, [X4]

        (73) 0x474814 CMP	X5, X1

        (73) 0x474818 CCMP	X5, X8, #8, #1

        (73) 0x47481c CCMP	X5, X9, #0, #10

        (73) 0x474820 B.LT	4747c0

        (73) 0x474824 LDR	D1, [X3]

        (73) 0x474828 FABS	D1, D1

        (73) 0x47482c FADD	D0, D0, D1

        (73) 0x474830 STR	D0, [X10, X1,LSL #3]

        (73) 0x474834 B	4747c0

      (70) 0x474838 ORR	X4, XZR, X3

      (70) 0x47483c ORN	X3, XZR, X3

      (70) 0x474840 ADD	X3, X2, X3

      (70) 0x474844 CMP	X3, #3

      (70) 0x474848 B.CC	4746c0

      (70) 0x47484c SUB	X2, X2, X4

      (70) 0x474850 ADD	X3, X18, X4,LSL #3

      (70) 0x474854 HINT	#0

      (70) 0x474858 HINT	#0

      (70) 0x47485c HINT	#0

        (71) 0x474860 LDUR	D1, [X3, #496]

        (71) 0x474864 SUBS	X2, X2, #4

        (71) 0x474868 FABS	D1, D1

        (71) 0x47486c FADD	D0, D0, D1

        (71) 0x474870 STR	D0, [X10, X1,LSL #3]

        (71) 0x474874 LDUR	D1, [X3, #504]

        (71) 0x474878 FABS	D1, D1

        (71) 0x47487c FADD	D0, D0, D1

        (71) 0x474880 STR	D0, [X10, X1,LSL #3]

        (71) 0x474884 LDR	D1, [X3]

        (71) 0x474888 FABS	D1, D1

        (71) 0x47488c FADD	D0, D0, D1

        (71) 0x474890 STR	D0, [X10, X1,LSL #3]

        (71) 0x474894 LDR	D1, [X3, #8]

        (71) 0x474898 ADD	X3, X3, #32

        (71) 0x47489c FABS	D1, D1

        (71) 0x4748a0 FADD	D0, D0, D1

        (71) 0x4748a4 STR	D0, [X10, X1,LSL #3]

        (71) 0x4748a8 B.NE	474860

      (70) 0x4748ac B	4746c0

    (58) 0x4748b0 LDR	X15, [X26]

    (58) 0x4748b4 LDR	X16, [X25]

    (58) 0x4748b8 ORR	X0, XZR, X8

    (58) 0x4748bc ADD	X17, X15, #16

    (58) 0x4748c0 ADD	X18, X16, #16

    (58) 0x4748c4 B	4748d0

      (62) 0x4748c8 CMP	X0, X9

      (62) 0x4748cc B.EQ	474a80

      (62) 0x4748d0 ORR	X1, XZR, X0

      (62) 0x4748d4 STR	XZR, [X10, X0,LSL #3]

      (62) 0x4748d8 ADD	X0, X0, #1

      (62) 0x4748dc ORR	X2, XZR, X14

      (62) 0x4748e0 MOVI	D0, #0

      (62) 0x4748e4 LDR	X14, [X11, X0,LSL #3]

      (62) 0x4748e8 CMP	X14, X2

      (62) 0x4748ec B.LE	4749ac

      (62) 0x4748f0 SUB	W3, W14, W2

      (62) 0x4748f4 MOVI	D0, #0

      (62) 0x4748f8 ANDS	X4, X3, #4160

      (62) 0x4748fc B.EQ	474934

      (62) 0x474900 ORR	X3, XZR, X2

        (66) 0x474904 LDR	D1, [X15, X3,LSL #3]

        (66) 0x474908 ADD	X3, X3, #1

        (66) 0x47490c SUBS	X4, X4, #1

        (66) 0x474910 FABS	D1, D1

        (66) 0x474914 FADD	D0, D0, D1

        (66) 0x474918 STR	D0, [X10, X1,LSL #3]

        (66) 0x47491c B.NE	474904

      (62) 0x474920 ORN	X2, XZR, X2

      (62) 0x474924 ADD	X2, X14, X2

      (62) 0x474928 CMP	X2, #3

      (62) 0x47492c B.CS	474948

      (62) 0x474930 B	4749ac

      (62) 0x474934 ORR	X3, XZR, X2

      (62) 0x474938 ORN	X2, XZR, X2

      (62) 0x47493c ADD	X2, X14, X2

      (62) 0x474940 CMP	X2, #3

      (62) 0x474944 B.CC	4749ac

      (62) 0x474948 SUB	X2, X14, X3

      (62) 0x47494c ADD	X3, X17, X3,LSL #3

      (62) 0x474950 HINT	#0

      (62) 0x474954 HINT	#0

      (62) 0x474958 HINT	#0

      (62) 0x47495c HINT	#0

        (65) 0x474960 LDUR	D1, [X3, #496]

        (65) 0x474964 SUBS	X2, X2, #4

        (65) 0x474968 FABS	D1, D1

        (65) 0x47496c FADD	D0, D0, D1

        (65) 0x474970 STR	D0, [X10, X1,LSL #3]

        (65) 0x474974 LDUR	D1, [X3, #504]

        (65) 0x474978 FABS	D1, D1

        (65) 0x47497c FADD	D0, D0, D1

        (65) 0x474980 STR	D0, [X10, X1,LSL #3]

        (65) 0x474984 LDR	D1, [X3]

        (65) 0x474988 FABS	D1, D1

        (65) 0x47498c FADD	D0, D0, D1

        (65) 0x474990 STR	D0, [X10, X1,LSL #3]

        (65) 0x474994 LDR	D1, [X3, #8]

        (65) 0x474998 ADD	X3, X3, #32

        (65) 0x47499c FABS	D1, D1

        (65) 0x4749a0 FADD	D0, D0, D1

        (65) 0x4749a4 STR	D0, [X10, X1,LSL #3]

        (65) 0x4749a8 B.NE	474960

      (62) 0x4749ac CBZ	X12, 4748c8

      (62) 0x4749b0 LDR	X3, [X13, X1,LSL #3]

      (62) 0x4749b4 LDR	X2, [X13, X0,LSL #3]

      (62) 0x4749b8 CMP	X2, X3

      (62) 0x4749bc B.LE	4748c8

      (62) 0x4749c0 SUB	W4, W2, W3

      (62) 0x4749c4 ANDS	X5, X4, #4160

      (62) 0x4749c8 B.EQ	474a10

      (62) 0x4749cc ORR	X4, XZR, X3

      (62) 0x4749d0 HINT	#0

      (62) 0x4749d4 HINT	#0

      (62) 0x4749d8 HINT	#0

      (62) 0x4749dc HINT	#0

        (64) 0x4749e0 LDR	D1, [X16, X4,LSL #3]

        (64) 0x4749e4 ADD	X4, X4, #1

        (64) 0x4749e8 SUBS	X5, X5, #1

        (64) 0x4749ec FABS	D1, D1

        (64) 0x4749f0 FADD	D0, D0, D1

        (64) 0x4749f4 STR	D0, [X10, X1,LSL #3]

        (64) 0x4749f8 B.NE	4749e0

      (62) 0x4749fc ORN	X3, XZR, X3

      (62) 0x474a00 ADD	X3, X2, X3

      (62) 0x474a04 CMP	X3, #3

      (62) 0x474a08 B.CC	4748c8

      (62) 0x474a0c B	474a24

      (62) 0x474a10 ORR	X4, XZR, X3

      (62) 0x474a14 ORN	X3, XZR, X3

      (62) 0x474a18 ADD	X3, X2, X3

      (62) 0x474a1c CMP	X3, #3

      (62) 0x474a20 B.CC	4748c8

      (62) 0x474a24 SUB	X2, X2, X4

      (62) 0x474a28 ADD	X3, X18, X4,LSL #3

        (63) 0x474a2c LDUR	D1, [X3, #496]

        (63) 0x474a30 SUBS	X2, X2, #4

        (63) 0x474a34 FABS	D1, D1

        (63) 0x474a38 FADD	D0, D0, D1

        (63) 0x474a3c STR	D0, [X10, X1,LSL #3]

        (63) 0x474a40 LDUR	D1, [X3, #504]

        (63) 0x474a44 FABS	D1, D1

        (63) 0x474a48 FADD	D0, D0, D1

        (63) 0x474a4c STR	D0, [X10, X1,LSL #3]

        (63) 0x474a50 LDR	D1, [X3]

        (63) 0x474a54 FABS	D1, D1

        (63) 0x474a58 FADD	D0, D0, D1

        (63) 0x474a5c STR	D0, [X10, X1,LSL #3]

        (63) 0x474a60 LDR	D1, [X3, #8]

        (63) 0x474a64 ADD	X3, X3, #32

        (63) 0x474a68 FABS	D1, D1

        (63) 0x474a6c FADD	D0, D0, D1

        (63) 0x474a70 STR	D0, [X10, X1,LSL #3]

        (63) 0x474a74 B.NE	474a2c

      (62) 0x474a78 B	4748c8

    (58) 0x474a80 SUBS	X10, X9, X8

    (58) 0x474a84 B.LE	473cd8

  (61) 0x474a88 LDUR	X11, [X29, #456]

  (61) 0x474a8c LDR	X12, [X26]

  (61) 0x474a90 ORR	X14, XZR, X8

  (61) 0x474a94 LDR	X13, [X11]

  (61) 0x474a98 LDR	X11, [SP, #64]

  (61) 0x474a9c LDR	X11, [X11]

  (61) 0x474aa0 TBZ	W10, #0, 474ac4

  (61) 0x474aa4 LDR	X14, [X13, X8,LSL #3]

  (61) 0x474aa8 LDR	D0, [X12, X14,LSL #3]

  (61) 0x474aac FCMP	D0, #0

  (61) 0x474ab0 B.PL	474ac0

  (61) 0x474ab4 LDR	D0, [X11, X8,LSL #3]

  (61) 0x474ab8 FNEG	D0, D0

  (61) 0x474abc STR	D0, [X11, X8,LSL #3]

  (61) 0x474ac0 ADD	X14, X8, #1

  (61) 0x474ac4 ADD	X15, X8, #1

  (61) 0x474ac8 CMP	X9, X15

  (61) 0x474acc B.NE	474b00

  (61) 0x474ad0 ADD	X8, X11, X8,LSL #3

  (61) 0x474ad4 HINT	#0

  (61) 0x474ad8 HINT	#0

  (61) 0x474adc HINT	#0

    (88) 0x474ae0 LDR	D0, [X8]

    (88) 0x474ae4 FCMP	D0, #0

    (88) 0x474ae8 B.EQ	473cc0

    (88) 0x474aec SUBS	X10, X10, #1

    (88) 0x474af0 ADD	X8, X8, #8

    (88) 0x474af4 B.NE	474ae0

  (61) 0x474af8 B	473cd8

0x474b00 SUB	X9, X9, X14

0x474b04 UBFM	X14, X14, #61, #60

0x474b08 ADD	X13, X13, X14

0x474b0c ADD	X14, X11, X14

0x474b10 ADD	X13, X13, #8

0x474b14 ADD	X14, X14, #8

0x474b18 B	474b30

0x474b20 SUBS	X9, X9, #2

0x474b24 ADD	X13, X13, #16

0x474b28 ADD	X14, X14, #16

0x474b2c B.EQ	474ad0

0x474b30 LDUR	X15, [X13, #504]

0x474b34 LDR	D0, [X12, X15,LSL #3]

0x474b38 FCMP	D0, #0

0x474b3c B.MI	474b60

0x474b40 LDR	X15, [X13]

0x474b44 LDR	D0, [X12, X15,LSL #3]

0x474b48 FCMP	D0, #0

0x474b4c B.PL	474b20

0x474b50 B	474b7c

0x474b7c LDR	D0, [X14]

0x474b80 FNEG	D0, D0

0x474b84 STR	D0, [X14]

0x474b88 B	474b20

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3365 - 3540

--------------------------------------------------------------------------------

3365:    for (k = 0; k < num_threads; k++)

3366:    {

3367:       size = num_rows/num_threads;

3368:       rest = num_rows - size*num_threads;

3369:       if (k < rest)

3370:       {

3371:          ns = k*size+k;

3372:          ne = (k+1)*size+k+1;

3373:       }

3374:       else

3375:       {

3376:          ns = k*size+rest;

3377:          ne = (k+1)*size+rest;

3378:       }

3379:

3380:       if (option == 1)

3381:       {

3382:          for (i = ns; i < ne; i++)

3383:          {

3384:             l1_norm[i] = 0.0;

3385:             if (cf_marker == NULL)

3386:             {

3387:                /* Add the l1 norm of the diag part of the ith row */

3388:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3389:                   l1_norm[i] += fabs(A_diag_data[j]);

3390:                /* Add the l1 norm of the offd part of the ith row */

3391:                if (num_cols_offd)

3392:                {

3393:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3394:                      l1_norm[i] += fabs(A_offd_data[j]);

3395:                }

3396:             }

3397:             else

3398:             {

3399:                cf_diag = cf_marker[i];

3400:                /* Add the CF l1 norm of the diag part of the ith row */

3401:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3402:                   if (cf_diag == cf_marker[A_diag_J[j]])

3403:                      l1_norm[i] += fabs(A_diag_data[j]);

3404:                /* Add the CF l1 norm of the offd part of the ith row */

3405:                if (num_cols_offd)

3406:                {

3407:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3408:                      if (cf_diag == cf_marker_offd[A_offd_J[j]])

3409:                         l1_norm[i] += fabs(A_offd_data[j]);

[...]

3416:          for (i = ns; i < ne; i++)

3417:          {

3418:             l1_norm[i] = 0.0;

3419:             if (cf_marker == NULL)

3420:             {

3421:                /* Add the diagonal and the local off-thread part of the ith row */

3422:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3423:                {

3424:                   ii = A_diag_J[j];

3425:                   if (ii == i || ii < ns || ii >= ne)

3426:                      l1_norm[i] += fabs(A_diag_data[j]);

3427:                }

3428:                /* Add the l1 norm of the offd part of the ith row */

3429:                if (num_cols_offd)

3430:                {

3431:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3432:                      l1_norm[i] += fabs(A_offd_data[j]);

3433:                }

3434:             }

3435:             else

3436:             {

3437:                cf_diag = cf_marker[i];

3438:                /* Add the diagonal and the local off-thread part of the ith row */

3439:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3440:                {

3441:                   ii = A_diag_J[j];

3442:                   if ((ii == i || ii < ns || ii >= ne) &&

3443:                       (cf_diag == cf_marker[A_diag_J[j]]))

3444:                      l1_norm[i] += fabs(A_diag_data[j]);

3445:                }

3446:                /* Add the CF l1 norm of the offd part of the ith row */

3447:                if (num_cols_offd)

3448:                {

3449:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3450:                      if (cf_diag == cf_marker_offd[A_offd_J[j]])

3451:                         l1_norm[i] += fabs(A_offd_data[j]);

[...]

3458:          for (i = ns; i < ne; i++)

3459:          {

3460:             l1_norm[i] = 0.0;

3461:             for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3462:                l1_norm[i] += A_diag_data[j] * A_diag_data[j];

3463:             if (num_cols_offd)

3464:                for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3465:                   l1_norm[i] += A_offd_data[j] * A_offd_data[j];

3466:          }

3467:       }

3468:       else if (option == 4)

3469:       {

3470:          for (i = ns; i < ne; i++)

3471:          {

3472:             l1_norm[i] = 0.0;

3473:             if (cf_marker == NULL)

3474:             {

3475:                /* Add the diagonal and the local off-thread part of the ith row */

3476:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3477:                {

3478:                   ii = A_diag_J[j];

3479:                   if (ii == i || ii < ns || ii >= ne)

3480:                   {

3481:                      if (ii == i)

[...]

3493:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3494:                      l1_norm[i] += 0.5*fabs(A_offd_data[j]);

3495:                }

3496:             }

3497:             else

3498:             {

3499:                cf_diag = cf_marker[i];

3500:                /* Add the diagonal and the local off-thread part of the ith row */

3501:                for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++)

3502:                {

3503:                   ii = A_diag_J[j];

3504:                   if ((ii == i || ii < ns || ii >= ne) &&

3505:                       (cf_diag == cf_marker[A_diag_J[j]]))

3506:                   {

3507:                      if (ii == i)

[...]

3517:                if (num_cols_offd)

3518:                {

3519:                   for (j = A_offd_I[i]; j < A_offd_I[i+1]; j++)

3520:                      if (cf_diag == cf_marker_offd[A_offd_J[j]])

3521:                         l1_norm[i] += 0.5*fabs(A_offd_data[j]);

3522:                }

3523:             }

3524:

3525:             /* Truncate according to Remark 6.2 */

3526:             if (l1_norm[i] <= 4.0/3.0*diag)

3527:                l1_norm[i] = diag;

3528:          }

3529:       }

3530:

3531:       /* Handle negative definite matrices */

3532:       for (i = ns; i < ne; i++)

3533:          if (A_diag_data[A_diag_I[i]] < 0)

3534:             l1_norm[i] = -l1_norm[i];

3535:

3536:       for (i = ns; i < ne; i++)

3537:          /* if (fabs(l1_norm[i]) < DBL_EPSILON) */

3538:          if (fabs(l1_norm[i]) == 0.0)

3539:          {

3540:             hypre_error_in_arg(1);

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.50
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	micro-operation queue, P0, P1,
Function	.omp_outlined.#0x473be0
Source	ams.c:3532-3534
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	0.75
Front-end cycles	3.00
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	2.25
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.25
P5 cycles	2.00
P6 cycles	1.00
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	2.17
P10 cycles	1.83
P11 cycles	2.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	24.00
Nb uops	24.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	40.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.50
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	micro-operation queue, P0, P1,
Function	.omp_outlined.#0x473be0
Source	ams.c:3532-3534
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	0.75
Front-end cycles	3.00
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	2.25
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.25
P5 cycles	2.00
P6 cycles	1.00
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	2.17
P10 cycles	1.83
P11 cycles	2.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	24.00
Nb uops	24.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	40.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined.#0x473be0
Source file and lines	ams.c:3365-3540
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3365-3409,3416-3451,3458-3481,3493-3507,3517-3540.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3532-3534.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.00 to 2.00 cycles (1.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.75 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 40 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	24
loop length	96
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	2.25	2.25	2.25	2.25	2.00	1.00	0.50	0.50	2.17	1.83	2.00	0.00	0.00
cycles	3.00	3.00	2.25	2.25	2.25	2.25	2.00	1.00	0.50	0.50	2.17	1.83	2.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.00
Overall L1	3.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

13% of peak load performance is reached (13.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.67 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 474b20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
SUB X9, X9, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X14, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X13, X13, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X14, X11, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X13, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X14, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B 474b30 <.omp_outlined.+0xf50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUBS X9, X9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
ADD X13, X13, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X14, X14, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.EQ 474ad0 <.omp_outlined.+0xef0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X15, [X13, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D0, [X12, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMP D0, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 474b60 <.omp_outlined.+0xf80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D0, [X12, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMP D0, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.PL 474b20 <.omp_outlined.+0xf40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 474b7c <.omp_outlined.+0xf9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FNEG D0, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D0, [X14]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B 474b20 <.omp_outlined.+0xf40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined.#0x473be0
Source file and lines	ams.c:3365-3540
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.00 to 2.00 cycles (1.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.75 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 40 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	24
loop length	96
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	2.25	2.25	2.25	2.25	2.00	1.00	0.50	0.50	2.17	1.83	2.00	0.00	0.00
cycles	3.00	3.00	2.25	2.25	2.25	2.25	2.00	1.00	0.50	0.50	2.17	1.83	2.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.00
Overall L1	3.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

13% of peak load performance is reached (13.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.67 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 474b20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
SUB X9, X9, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X14, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X13, X13, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X14, X11, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X13, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X14, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B 474b30 <.omp_outlined.+0xf50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUBS X9, X9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
ADD X13, X13, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X14, X14, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.EQ 474ad0 <.omp_outlined.+0xef0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X15, [X13, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D0, [X12, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMP D0, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 474b60 <.omp_outlined.+0xf80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D0, [X12, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMP D0, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.PL 474b20 <.omp_outlined.+0xf40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 474b7c <.omp_outlined.+0xf9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FNEG D0, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D0, [X14]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B 474b20 <.omp_outlined.+0xf40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code