OV - exec - Loop 570

  (569) 0x462260 LDUR	X17, [X29, #496]

  (569) 0x462264 CMP	X10, X17

  (569) 0x462268 B.GE	462324

  (569) 0x46226c ORR	X17, XZR, X10

  (569) 0x462270 LDUR	X10, [X29, #488]

  (569) 0x462274 LDR	X18, [X11, X17,LSL #3]

  (569) 0x462278 ADD	X10, X18, X10

  (569) 0x46227c STR	X10, [X11, X17,LSL #3]

  (569) 0x462280 LDUR	X10, [X29, #480]

  (569) 0x462284 LDR	X18, [X12, X17,LSL #3]

  (569) 0x462288 ADD	X10, X18, X10

  (569) 0x46228c STR	X10, [X12, X17,LSL #3]

  (569) 0x462290 ADD	X10, X17, #1

  (569) 0x462294 LDR	X18, [X13, X17,LSL #3]

  (569) 0x462298 LDR	X0, [X13, X10,LSL #3]

  (569) 0x46229c CMP	X18, X0

  (569) 0x4622a0 B.GE	4622e4

0x4622a4 LDR	X1, [X11, X17,LSL #3]

0x4622a8 LDR	X2, [X9]

0x4622ac B	4622cc

0x4622c0 ADD	X18, X18, #1

0x4622c4 CMP	X18, X0

0x4622c8 B.GE	4622e4

0x4622cc LDR	X3, [X14, X18,LSL #3]

0x4622d0 TBNZ	X3, #63, 4622c0

0x4622d4 STR	X3, [X2, X1,LSL #3]

0x4622d8 ADD	X1, X1, #1

0x4622dc LDR	X0, [X13, X10,LSL #3]

0x4622e0 B	4622c0

  (569) 0x4622e4 LDR	X18, [X15, X17,LSL #3]

  (569) 0x4622e8 LDR	X0, [X15, X10,LSL #3]

  (569) 0x4622ec CMP	X18, X0

  (569) 0x4622f0 B.GE	462260

  (569) 0x4622f4 LDR	X17, [X12, X17,LSL #3]

  (569) 0x4622f8 LDR	X1, [X8]

  (569) 0x4622fc B	46230c

    (571) 0x462300 ADD	X18, X18, #1

    (571) 0x462304 CMP	X18, X0

    (571) 0x462308 B.GE	462260

    (571) 0x46230c LDR	X2, [X16, X18,LSL #3]

    (571) 0x462310 TBNZ	X2, #63, 462300

    (571) 0x462314 STR	X2, [X1, X17,LSL #3]

    (571) 0x462318 ADD	X17, X17, #1

    (571) 0x46231c LDR	X0, [X15, X10,LSL #3]

    (571) 0x462320 B	462300

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 492 - 513

--------------------------------------------------------------------------------

492:    for (i = start; i < stop; i++)

493:    {

494:       S_diag_i[i] += jS_diag;

495:       S_offd_i[i] += jS_offd;

496:

497:       jS = S_diag_i[i];

498:       for (jA = A_diag_i[i]; jA < A_diag_i[i+1]; jA++)

499:       {

500:          if (S_temp_diag_j[jA] > -1)

501:          {

502:             S_diag_j[jS]    = S_temp_diag_j[jA];

503:             jS++;

504:          }

505:       }

506:

507:       jS = S_offd_i[i];

508:       for (jA = A_offd_i[i]; jA < A_offd_i[i+1]; jA++)

509:       {

510:          if (S_temp_offd_j[jA] > -1)

511:          {

512:             S_offd_j[jS]    = S_temp_offd_j[jA];

513:             jS++;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	P0, P1,
Function	.omp_outlined..2#0x461580
Source	par_strength.c:497-503
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.00
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	2.00
CQA cycles if fully vectorized	0.50
Front-end cycles	1.50
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.83
P10 cycles	1.50
P11 cycles	1.67
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	12.00
Nb uops	12.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.00
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	P0, P1,
Function	.omp_outlined..2#0x461580
Source	par_strength.c:497-503
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.00
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	2.00
CQA cycles if fully vectorized	0.50
Front-end cycles	1.50
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.83
P10 cycles	1.50
P11 cycles	1.67
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	12.00
Nb uops	12.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.00
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..2#0x461580
Source file and lines	par_strength.c:492-513
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:492-513.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:497-503.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 2.00 to 0.50 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 32 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	12
loop length	48
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	1.83	1.50	1.67	0.50	0.50
cycles	2.00	2.00	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	1.83	1.50	1.67	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	1.50
Overall L1	2.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (4.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4622c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X1, [X11, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X9]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4622cc <.omp_outlined..2+0xd4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X18, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4622e4 <.omp_outlined..2+0xd64>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X3, [X14, X18,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
TBNZ X3, #63, 4622c0 <.omp_outlined..2+0xd40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X3, [X2, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X13, X10,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4622c0 <.omp_outlined..2+0xd40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..2#0x461580
Source file and lines	par_strength.c:492-513
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:492-513.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:497-503.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 2.00 to 0.50 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 32 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	12
loop length	48
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	1.83	1.50	1.67	0.50	0.50
cycles	2.00	2.00	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	1.83	1.50	1.67	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	1.50
Overall L1	2.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (4.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4622c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X1, [X11, X17,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X9]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4622cc <.omp_outlined..2+0xd4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X18, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4622e4 <.omp_outlined..2+0xd64>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X3, [X14, X18,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
TBNZ X3, #63, 4622c0 <.omp_outlined..2+0xd40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR X3, [X2, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X13, X10,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4622c0 <.omp_outlined..2+0xd40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code