OV - exec - Loop 497

  (498) 0x421220 ORR	W1, WZR, W19

  (498) 0x421224 ADRP	X0,

  (498) 0x421228 ADD	X0, X0, #680

  (498) 0x42122c BL	40f990

  (498) 0x421230 LDP	X20, X19, [SP, #80]

  (498) 0x421234 LDP	X22, X21, [SP, #64]

  (498) 0x421238 LDR	X23, [SP, #48]

  (498) 0x42123c LDP	X29, X30, [SP, #32]

  (498) 0x421240 ADD	SP, SP, #96

  (498) 0x421244 RET

  (498) 0x421248 SUB	X8, X8, X10

  (498) 0x42124c ADD	X9, X22, X10,LSL #3

  (498) 0x421250 FMOV	D0, #1.0000000

  (498) 0x421254 MOVZ	W10, #1

  (498) 0x421258 ADD	X8, X8, #1

  (498) 0x42125c ADD	X9, X9, #8

  (498) 0x421260 B	421270

  (498) 0x421264 SUBS	X8, X8, #2

  (498) 0x421268 ADD	X9, X9, #16

  (498) 0x42126c B.EQ	421220

  (498) 0x421270 LDUR	X11, [X9, #504]

  (498) 0x421274 LDR	D1, [X20, X11,LSL #3]

  (498) 0x421278 FCMP	D1, D0

  (498) 0x42127c B.GT	4212a0

  (498) 0x421280 LDR	X11, [X9]

  (498) 0x421284 LDR	D1, [X20, X11,LSL #3]

  (498) 0x421288 FCMP	D1, D0

  (498) 0x42128c B.LE	421264

  (498) 0x421290 B	4212b4

0x4212a0 STR	X10, [X21, X11,LSL #3]

0x4212a4 LDR	X11, [X9]

0x4212a8 LDR	D1, [X20, X11,LSL #3]

0x4212ac FCMP	D1, D0

0x4212b0 B.LE	421264

  (498) 0x4212b4 STR	X10, [X21, X11,LSL #3]

  (498) 0x4212b8 B	421264

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 2327 - 2334

--------------------------------------------------------------------------------

2327: #pragma omp parallel for private(ig, i) HYPRE_SMP_SCHEDULE

2328: #endif

2329:         for (ig = 0; ig < graph_size; ig++)

2330:         {

2331:            i = graph_array[ig];

2332:            if (measure_array[i] > 1)

2333:            {

2334:               CF_marker[i] = 1;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.17
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.17
Bottlenecks	P10,
Function	.omp_outlined..15
Source	par_coarsen.c:2331-2334
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.17
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	1.17
CQA cycles if fully vectorized	0.29
Front-end cycles	0.63
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.00
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	0.00
P5 cycles	1.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.17
P10 cycles	0.83
P11 cycles	1.00
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	5.00
Nb uops	5.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.57
Bytes prefetched	0.00
Bytes loaded	16.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.17
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.17
Bottlenecks	P10,
Function	.omp_outlined..15
Source	par_coarsen.c:2331-2334
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.17
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	1.17
CQA cycles if fully vectorized	0.29
Front-end cycles	0.63
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.00
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	0.00
P5 cycles	1.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.17
P10 cycles	0.83
P11 cycles	1.00
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	5.00
Nb uops	5.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.57
Bytes prefetched	0.00
Bytes loaded	16.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..15
Source file and lines	par_coarsen.c:2327-2334
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2327-2334.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2331-2334.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 1.17 to 1.00 cycles (1.17x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 1.17 to 0.29 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 16 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	5
loop length	20
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

0.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.00	0.00	0.00	0.00	1.00	0.00	0.00	0.00	1.17	0.83	1.00	0.50	0.50
cycles	0.50	0.50	0.00	0.00	0.00	0.00	1.00	0.00	0.00	0.00	1.17	0.83	1.00	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	0.63
Overall L1	1.17

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.17 cycles. At this rate:

14% of peak load performance is reached (13.71 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (6.86 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4212a0

Instruction	Nb FU	P0	P1	P6	P10	P11	P12	P13	P14	Latency	Recip. throughput
STR X10, [X21, X11,LSL #3]	1	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X11, [X9]	1	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D1, [X20, X11,LSL #3]	1	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMP D1, D0	1	0	0	1	0	0	0	0	0	2	1
B.LE 421264 <.omp_outlined..15+0x114>	1	0.50	0.50	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..15
Source file and lines	par_coarsen.c:2327-2334
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2327-2334.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:2331-2334.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 1.17 to 1.00 cycles (1.17x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 1.17 to 0.29 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 16 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	5
loop length	20
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

0.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.00	0.00	0.00	0.00	1.00	0.00	0.00	0.00	1.17	0.83	1.00	0.50	0.50
cycles	0.50	0.50	0.00	0.00	0.00	0.00	1.00	0.00	0.00	0.00	1.17	0.83	1.00	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	0.63
Overall L1	1.17

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.17 cycles. At this rate:

14% of peak load performance is reached (13.71 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (6.86 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4212a0

Instruction	Nb FU	P0	P1	P6	P10	P11	P12	P13	P14	Latency	Recip. throughput
STR X10, [X21, X11,LSL #3]	1	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X11, [X9]	1	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D1, [X20, X11,LSL #3]	1	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMP D1, D0	1	0	0	1	0	0	0	0	0	2	1
B.LE 421264 <.omp_outlined..15+0x114>	1	0.50	0.50	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code