OV - exec - Loop 49

0x47de80 LDUR	X14, [X29, #496]

  (48) 0x47de84 STR	X30, [X5, X20,LSL #3]

  (48) 0x47de88 STR	X27, [X7, X20,LSL #3]

  (48) 0x47de8c ORR	X27, XZR, X24

  (48) 0x47de90 ORR	X30, XZR, X6

  (48) 0x47de94 ORR	X20, XZR, X25

  (48) 0x47de98 CMP	X25, X14

  (48) 0x47de9c B.EQ	47e098

  (48) 0x47dea0 LDUR	X8, [X29, #504]

  (48) 0x47dea4 LDR	X8, [X8]

  (48) 0x47dea8 CBZ	X8, 47deb4

  (48) 0x47deac ADD	X6, X30, #1

  (48) 0x47deb0 STR	X30, [X0, X20,LSL #3]

  (48) 0x47deb4 LDR	X8, [X15]

  (48) 0x47deb8 CBZ	X8, 47df80

  (48) 0x47debc LDUR	X8, [X29, #488]

  (48) 0x47dec0 LDR	X13, [X8, X20,LSL #3]

  (48) 0x47dec4 LDR	X8, [X23, X20,LSL #3]

  (48) 0x47dec8 CMP	X13, X8

  (48) 0x47decc B.GE	47df80

  (48) 0x47ded0 LDP	X8, X9, [SP, #56]

  (48) 0x47ded4 ORR	X24, XZR, X27

  (48) 0x47ded8 LDR	X8, [X8]

  (48) 0x47dedc LDR	X14, [X9]

  (48) 0x47dee0 B	47def4

    (52) 0x47dee4 LDR	X9, [X23, X20,LSL #3]

    (52) 0x47dee8 ADD	X13, X13, #1

    (52) 0x47deec CMP	X13, X9

    (52) 0x47def0 B.GE	47dfa0

    (52) 0x47def4 LDR	X10, [X17, X13,LSL #3]

    (52) 0x47def8 ADD	X9, X10, #1

    (52) 0x47defc LDR	X19, [X18, X10,LSL #3]

    (52) 0x47df00 LDR	X12, [X18, X9,LSL #3]

    (52) 0x47df04 B	47df0c

      (54) 0x47df08 ADD	X19, X19, #1

      (54) 0x47df0c CMP	X19, X12

      (54) 0x47df10 B.GE	47df40

      (54) 0x47df14 LDR	X16, [X22]

      (54) 0x47df18 LDR	X25, [X8, X19,LSL #3]

      (54) 0x47df1c ADD	X16, X16, X25

      (54) 0x47df20 LDR	X25, [X0, X16,LSL #3]

      (54) 0x47df24 CMP	X25, X27

      (54) 0x47df28 B.GE	47df08

      (54) 0x47df2c STR	X24, [X0, X16,LSL #3]

      (54) 0x47df30 ADD	X24, X24, #1

      (54) 0x47df34 LDR	X12, [X18, X9,LSL #3]

      (54) 0x47df38 B	47df08

    (52) 0x47df40 LDR	X10, [X1, X10,LSL #3]

    (52) 0x47df44 LDR	X12, [X1, X9,LSL #3]

    (52) 0x47df48 B	47df50

      (53) 0x47df4c ADD	X10, X10, #1

      (53) 0x47df50 CMP	X10, X12

      (53) 0x47df54 B.GE	47dee4

      (53) 0x47df58 LDR	X16, [X14, X10,LSL #3]

      (53) 0x47df5c LDR	X19, [X0, X16,LSL #3]

      (53) 0x47df60 CMP	X19, X30

      (53) 0x47df64 B.GE	47df4c

      (53) 0x47df68 STR	X6, [X0, X16,LSL #3]

      (53) 0x47df6c ADD	X6, X6, #1

      (53) 0x47df70 LDR	X12, [X1, X9,LSL #3]

      (53) 0x47df74 B	47df4c

  (48) 0x47df80 ORR	X24, XZR, X27

  (48) 0x47df84 ADD	X25, X20, #1

  (48) 0x47df88 LDR	X28, [X2, X20,LSL #3]

  (48) 0x47df8c LDR	X8, [X2, X25,LSL #3]

  (48) 0x47df90 CMP	X28, X8

  (48) 0x47df94 B.GE	47de84

0x47df98 B	47dfb8

  (48) 0x47dfa0 LDUR	X14, [X29, #496]

  (48) 0x47dfa4 ADD	X25, X20, #1

  (48) 0x47dfa8 LDR	X28, [X2, X20,LSL #3]

  (48) 0x47dfac LDR	X8, [X2, X25,LSL #3]

  (48) 0x47dfb0 CMP	X28, X8

  (48) 0x47dfb4 B.GE	47de84

0x47dfb8 LDUR	X8, [X29, #456]

0x47dfbc LDR	X13, [X8]

0x47dfc0 LDUR	X8, [X29, #464]

0x47dfc4 LDR	X14, [X8]

0x47dfc8 LDUR	X8, [X29, #472]

0x47dfcc LDR	X19, [X8]

0x47dfd0 LDUR	X8, [X29, #480]

0x47dfd4 LDR	X8, [X8]

0x47dfd8 B	47dff0

0x47dfe0 LDR	X9, [X2, X25,LSL #3]

0x47dfe4 ADD	X28, X28, #1

0x47dfe8 CMP	X28, X9

0x47dfec B.GE	47de80

0x47dff0 LDR	X10, [X3, X28,LSL #3]

0x47dff4 ADD	X9, X10, #1

0x47dff8 LDR	X12, [X4, X10,LSL #3]

0x47dffc LDR	X16, [X4, X9,LSL #3]

0x47e000 B	47e008

  (51) 0x47e004 ADD	X12, X12, #1

  (51) 0x47e008 CMP	X12, X16

  (51) 0x47e00c B.GE	47e040

  (51) 0x47e010 LDR	X26, [X13, X12,LSL #3]

  (51) 0x47e014 LDR	X21, [X0, X26,LSL #3]

  (51) 0x47e018 CMP	X21, X30

  (51) 0x47e01c B.GE	47e004

  (51) 0x47e020 STR	X6, [X0, X26,LSL #3]

  (51) 0x47e024 ADD	X6, X6, #1

  (51) 0x47e028 LDR	X16, [X4, X9,LSL #3]

  (51) 0x47e02c B	47e004

0x47e040 LDR	X12, [X11]

0x47e044 CBZ	X12, 47dfe0

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 127 - 242

--------------------------------------------------------------------------------

127:     for (i1 = ns; i1 < ne; i1++)

[...]

135:       if ( allsquare ) {

136:          B_marker[i1] = jj_count_diag;

137:          jj_count_diag++;

[...]

144:       if (num_cols_offd_A)

145:       {

146:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

147:          {

148:             i2 = A_offd_j[jj2];

[...]

154:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

155:             {

156:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

164:                if (B_marker[i3] < jj_row_begin_offd)

165:                {

166:                   B_marker[i3] = jj_count_offd;

167:                   jj_count_offd++;

168:                }

169:             }

170:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

171:             {

172:                i3 = B_ext_diag_j[jj3];

173:

174:                if (B_marker[i3] < jj_row_begin_diag)

175:                {

176:                   B_marker[i3] = jj_count_diag;

177:                   jj_count_diag++;

[...]

187:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

188:       {

189:          i2 = A_diag_j[jj2];

[...]

195:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

196:          {

197:             i3 = B_diag_j[jj3];

[...]

205:             if (B_marker[i3] < jj_row_begin_diag)

206:             {

207:                B_marker[i3] = jj_count_diag;

208:                jj_count_diag++;

[...]

216:          if (num_cols_offd_B)

[...]

241:       (*C_diag_i)[i1] = jj_row_begin_diag;

242:       (*C_offd_i)[i1] = jj_row_begin_offd;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.70
Bottlenecks	P10, P11, P12,
Function	.omp_outlined.#0x47dce0
Source	par_csr_matop.c:127-127,par_csr_matop.c:187-189,par_csr_matop.c:195-195,par_csr_matop.c:216-216
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.67
CQA cycles if no scalar integer	4.67
CQA cycles if FP arith vectorized	4.67
CQA cycles if fully vectorized	1.17
Front-end cycles	2.75
DIV/SQRT cycles	2.50
P0 cycles	2.50
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	4.67
P10 cycles	4.67
P11 cycles	4.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	22.00
Nb uops	22.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	112.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.70
Bottlenecks	P10, P11, P12,
Function	.omp_outlined.#0x47dce0
Source	par_csr_matop.c:127-127,par_csr_matop.c:187-189,par_csr_matop.c:195-195,par_csr_matop.c:216-216
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.67
CQA cycles if no scalar integer	4.67
CQA cycles if FP arith vectorized	4.67
CQA cycles if fully vectorized	1.17
Front-end cycles	2.75
DIV/SQRT cycles	2.50
P0 cycles	2.50
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	4.67
P10 cycles	4.67
P11 cycles	4.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	22.00
Nb uops	22.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	112.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined.#0x47dce0
Source file and lines	par_csr_matop.c:127-242
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:127,135-137,144-148,154-156,164-177,187-189,195-197,205-208,216,241-242.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:127,187-189,195,216.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 4.67 to 1.17 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 112 bytes.

General properties

nb instructions	22
loop length	88
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	4.67	4.67	4.67	0.00	0.00
cycles	2.50	2.50	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	4.67	4.67	4.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.75
Overall L1	4.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.67 cycles. At this rate:

25% of peak load performance is reached (24.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 47dfe0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDUR X14, [X29, #496]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 47dfb8 <.omp_outlined.+0x2d8>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X13, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR X8, [X29, #464]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X14, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR X8, [X29, #472]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X19, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR X8, [X29, #480]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 47dff0 <.omp_outlined.+0x310>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X9, [X2, X25,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X28, X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X28, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GE 47de80 <.omp_outlined.+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X10, [X3, X28,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X9, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X12, [X4, X10,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X16, [X4, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 47e008 <.omp_outlined.+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X12, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CBZ X12, 47dfe0 <.omp_outlined.+0x300>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined.#0x47dce0
Source file and lines	par_csr_matop.c:127-242
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:127,135-137,144-148,154-156,164-177,187-189,195-197,205-208,216,241-242.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:127,187-189,195,216.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 4.67 to 1.17 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 112 bytes.

General properties

nb instructions	22
loop length	88
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	4.67	4.67	4.67	0.00	0.00
cycles	2.50	2.50	0.75	0.75	0.75	0.75	0.00	0.00	0.00	0.00	4.67	4.67	4.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.75
Overall L1	4.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.67 cycles. At this rate:

25% of peak load performance is reached (24.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 47dfe0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDUR X14, [X29, #496]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 47dfb8 <.omp_outlined.+0x2d8>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X13, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR X8, [X29, #464]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X14, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR X8, [X29, #472]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X19, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR X8, [X29, #480]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 47dff0 <.omp_outlined.+0x310>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X9, [X2, X25,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X28, X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X28, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GE 47de80 <.omp_outlined.+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X10, [X3, X28,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X9, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X12, [X4, X10,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X16, [X4, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 47e008 <.omp_outlined.+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X12, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CBZ X12, 47dfe0 <.omp_outlined.+0x300>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code