OV - exec - Loop 437

0x47fbc0 LDP	X30, X21, [SP, #88]

  (436) 0x47fbc4 LDUR	X8, [X29, #440]

  (436) 0x47fbc8 ORR	X19, XZR, X3

  (436) 0x47fbcc ORR	X22, XZR, X2

  (436) 0x47fbd0 CMP	X26, X8

  (436) 0x47fbd4 B.GE	47ff18

  (436) 0x47fbd8 LDUR	X8, [X29, #432]

  (436) 0x47fbdc LDR	X8, [X8]

  (436) 0x47fbe0 CBZ	X8, 47fc04

  (436) 0x47fbe4 LDUR	X8, [X29, #416]

  (436) 0x47fbe8 ADD	X2, X22, #1

  (436) 0x47fbec STR	X22, [X0, X26,LSL #3]

  (436) 0x47fbf0 LDR	D0, [X8]

  (436) 0x47fbf4 LDUR	X8, [X29, #408]

  (436) 0x47fbf8 STR	D0, [X8, X22,LSL #3]

  (436) 0x47fbfc LDR	X8, [SP, #112]

  (436) 0x47fc00 STR	X26, [X8, X22,LSL #3]

  (436) 0x47fc04 LDUR	X8, [X29, #424]

  (436) 0x47fc08 LDR	X8, [X8]

  (436) 0x47fc0c CBZ	X8, 47fd80

  (436) 0x47fc10 LDR	X8, [SP, #104]

  (436) 0x47fc14 LDR	X4, [X8, X26,LSL #3]

  (436) 0x47fc18 LDR	X8, [X1, X26,LSL #3]

  (436) 0x47fc1c CMP	X4, X8

  (436) 0x47fc20 B.GE	47fda0

  (436) 0x47fc24 LDR	X8, [SP, #40]

  (436) 0x47fc28 ORR	X3, XZR, X19

  (436) 0x47fc2c LDR	X5, [X8]

  (436) 0x47fc30 LDR	X8, [SP, #48]

  (436) 0x47fc34 LDR	X6, [X8]

  (436) 0x47fc38 B	47fc50

    (440) 0x47fc40 LDR	X8, [X1, X26,LSL #3]

    (440) 0x47fc44 ADD	X4, X4, #1

    (440) 0x47fc48 CMP	X4, X8

    (440) 0x47fc4c B.GE	47fd84

    (440) 0x47fc50 LDUR	X8, [X29, #472]

    (440) 0x47fc54 LDR	X7, [X8, X4,LSL #3]

    (440) 0x47fc58 LDUR	X8, [X29, #464]

    (440) 0x47fc5c LDR	D0, [X8, X4,LSL #3]

    (440) 0x47fc60 ADD	X8, X7, #1

    (440) 0x47fc64 LDR	X9, [X13, X7,LSL #3]

    (440) 0x47fc68 LDR	X24, [X13, X8,LSL #3]

    (440) 0x47fc6c CMP	X9, X24

    (440) 0x47fc70 B.GE	47fcf0

    (440) 0x47fc74 LDUR	X11, [X29, #480]

    (440) 0x47fc78 LDR	X10, [X30]

    (440) 0x47fc7c LDR	X27, [X11]

    (440) 0x47fc80 LDUR	X11, [X29, #488]

    (440) 0x47fc84 LDR	X23, [X11]

    (440) 0x47fc88 B	47fca8

      (442) 0x47fc8c LDR	D1, [X10, X9,LSL #3]

      (442) 0x47fc90 LDR	D2, [X27, X12,LSL #3]

      (442) 0x47fc94 FMADD	D1, D0, D1, D2

      (442) 0x47fc98 STR	D1, [X27, X12,LSL #3]

      (442) 0x47fc9c ADD	X9, X9, #1

      (442) 0x47fca0 CMP	X9, X24

      (442) 0x47fca4 B.GE	47fcf0

      (442) 0x47fca8 LDR	X11, [X20]

      (442) 0x47fcac LDR	X12, [X5, X9,LSL #3]

      (442) 0x47fcb0 ADD	X11, X12, X11

      (442) 0x47fcb4 LDR	X12, [X0, X11,LSL #3]

      (442) 0x47fcb8 CMP	X12, X19

      (442) 0x47fcbc B.GE	47fc8c

      (442) 0x47fcc0 STR	X3, [X0, X11,LSL #3]

      (442) 0x47fcc4 LDR	D1, [X10, X9,LSL #3]

      (442) 0x47fcc8 LDR	X12, [X20]

      (442) 0x47fccc SUB	X11, X11, X12

      (442) 0x47fcd0 FMUL	D1, D0, D1

      (442) 0x47fcd4 STR	X11, [X23, X3,LSL #3]

      (442) 0x47fcd8 LDR	X24, [X13, X8,LSL #3]

      (442) 0x47fcdc STR	D1, [X27, X3,LSL #3]

      (442) 0x47fce0 ADD	X3, X3, #1

      (442) 0x47fce4 ADD	X9, X9, #1

      (442) 0x47fce8 CMP	X9, X24

      (442) 0x47fcec B.LT	47fca8

    (440) 0x47fcf0 LDR	X9, [X14, X7,LSL #3]

    (440) 0x47fcf4 LDR	X23, [X14, X8,LSL #3]

    (440) 0x47fcf8 CMP	X9, X23

    (440) 0x47fcfc B.GE	47fc40

    (440) 0x47fd00 LDUR	X11, [X29, #496]

    (440) 0x47fd04 LDR	X10, [X21]

    (440) 0x47fd08 LDR	X7, [X25]

    (440) 0x47fd0c LDR	X24, [X11]

    (440) 0x47fd10 B	47fd3c

      (441) 0x47fd20 LDR	D1, [X10, X9,LSL #3]

      (441) 0x47fd24 LDR	D2, [X7, X12,LSL #3]

      (441) 0x47fd28 FMADD	D1, D0, D1, D2

      (441) 0x47fd2c STR	D1, [X7, X12,LSL #3]

      (441) 0x47fd30 ADD	X9, X9, #1

      (441) 0x47fd34 CMP	X9, X23

      (441) 0x47fd38 B.GE	47fc40

      (441) 0x47fd3c LDR	X11, [X6, X9,LSL #3]

      (441) 0x47fd40 LDR	X12, [X0, X11,LSL #3]

      (441) 0x47fd44 CMP	X12, X22

      (441) 0x47fd48 B.GE	47fd20

      (441) 0x47fd4c LDR	D1, [X10, X9,LSL #3]

      (441) 0x47fd50 STR	X2, [X0, X11,LSL #3]

      (441) 0x47fd54 STR	X11, [X24, X2,LSL #3]

      (441) 0x47fd58 LDR	X23, [X14, X8,LSL #3]

      (441) 0x47fd5c FMUL	D1, D0, D1

      (441) 0x47fd60 STR	D1, [X7, X2,LSL #3]

      (441) 0x47fd64 ADD	X2, X2, #1

      (441) 0x47fd68 ADD	X9, X9, #1

      (441) 0x47fd6c CMP	X9, X23

      (441) 0x47fd70 B.LT	47fd3c

    (440) 0x47fd74 B	47fc40

  (436) 0x47fd80 ORR	X3, XZR, X19

  (436) 0x47fd84 LDR	X4, [X15, X26,LSL #3]

  (436) 0x47fd88 ADD	X26, X26, #1

  (436) 0x47fd8c LDR	X8, [X15, X26,LSL #3]

  (436) 0x47fd90 CMP	X4, X8

  (436) 0x47fd94 B.GE	47fbc4

0x47fd98 B	47fdb8

  (436) 0x47fda0 ORR	X3, XZR, X19

  (436) 0x47fda4 LDR	X4, [X15, X26,LSL #3]

  (436) 0x47fda8 ADD	X26, X26, #1

  (436) 0x47fdac LDR	X8, [X15, X26,LSL #3]

  (436) 0x47fdb0 CMP	X4, X8

  (436) 0x47fdb4 B.GE	47fbc4

0x47fdb8 LDR	X8, [SP, #56]

0x47fdbc LDR	X5, [X8]

0x47fdc0 LDR	X8, [SP, #64]

0x47fdc4 LDR	X6, [X8]

0x47fdc8 LDR	X8, [SP, #72]

0x47fdcc LDR	X7, [X8]

0x47fdd0 LDR	X8, [SP, #80]

0x47fdd4 LDR	X30, [X8]

0x47fdd8 B	47fdf0

0x47fde0 LDR	X8, [X15, X26,LSL #3]

0x47fde4 ADD	X4, X4, #1

0x47fde8 CMP	X4, X8

0x47fdec B.GE	47fbc0

0x47fdf0 LDR	X9, [X16, X4,LSL #3]

0x47fdf4 LDR	D0, [X17, X4,LSL #3]

0x47fdf8 ADD	X8, X9, #1

0x47fdfc LDR	X10, [X18, X9,LSL #3]

0x47fe00 LDR	X27, [X18, X8,LSL #3]

0x47fe04 CMP	X10, X27

0x47fe08 B.GE	47fe78

0x47fe0c LDUR	X11, [X29, #456]

0x47fe10 LDR	X24, [X25]

0x47fe14 LDR	X23, [X11]

0x47fe18 LDUR	X11, [X29, #496]

0x47fe1c LDR	X11, [X11]

0x47fe20 B	47fe40

  (439) 0x47fe24 LDR	D1, [X23, X10,LSL #3]

  (439) 0x47fe28 LDR	D2, [X24, X21,LSL #3]

  (439) 0x47fe2c FMADD	D1, D0, D1, D2

  (439) 0x47fe30 STR	D1, [X24, X21,LSL #3]

  (439) 0x47fe34 ADD	X10, X10, #1

  (439) 0x47fe38 CMP	X10, X27

  (439) 0x47fe3c B.GE	47fe78

  (439) 0x47fe40 LDR	X12, [X5, X10,LSL #3]

  (439) 0x47fe44 LDR	X21, [X0, X12,LSL #3]

  (439) 0x47fe48 CMP	X21, X22

  (439) 0x47fe4c B.GE	47fe24

  (439) 0x47fe50 LDR	D1, [X23, X10,LSL #3]

  (439) 0x47fe54 STR	X2, [X0, X12,LSL #3]

  (439) 0x47fe58 STR	X12, [X11, X2,LSL #3]

  (439) 0x47fe5c LDR	X27, [X18, X8,LSL #3]

  (439) 0x47fe60 FMUL	D1, D0, D1

  (439) 0x47fe64 STR	D1, [X24, X2,LSL #3]

  (439) 0x47fe68 ADD	X2, X2, #1

  (439) 0x47fe6c ADD	X10, X10, #1

  (439) 0x47fe70 CMP	X10, X27

  (439) 0x47fe74 B.LT	47fe40

0x47fe78 LDR	X10, [X28]

0x47fe7c CBZ	X10, 47fde0

0x47fe80 LDR	X9, [X6, X9,LSL #3]

0x47fe84 LDR	X24, [X6, X8,LSL #3]

0x47fe88 CMP	X9, X24

0x47fe8c B.GE	47fde0

0x47fe90 LDUR	X11, [X29, #480]

0x47fe94 LDUR	X10, [X29, #448]

0x47fe98 LDR	X27, [X11]

0x47fe9c LDUR	X11, [X29, #488]

0x47fea0 LDR	X10, [X10]

0x47fea4 LDR	X23, [X11]

0x47fea8 B	47fec8

  (438) 0x47feac LDR	D1, [X10, X9,LSL #3]

  (438) 0x47feb0 LDR	D2, [X27, X12,LSL #3]

  (438) 0x47feb4 FMADD	D1, D0, D1, D2

  (438) 0x47feb8 STR	D1, [X27, X12,LSL #3]

  (438) 0x47febc ADD	X9, X9, #1

  (438) 0x47fec0 CMP	X9, X24

  (438) 0x47fec4 B.GE	47fde0

  (438) 0x47fec8 LDR	X12, [X30, X9,LSL #3]

  (438) 0x47fecc LDR	X11, [X20]

  (438) 0x47fed0 LDR	X12, [X7, X12,LSL #3]

  (438) 0x47fed4 ADD	X11, X12, X11

  (438) 0x47fed8 LDR	X12, [X0, X11,LSL #3]

  (438) 0x47fedc CMP	X12, X19

  (438) 0x47fee0 B.GE	47feac

  (438) 0x47fee4 STR	X3, [X0, X11,LSL #3]

  (438) 0x47fee8 LDR	D1, [X10, X9,LSL #3]

  (438) 0x47feec LDR	X12, [X20]

  (438) 0x47fef0 SUB	X11, X11, X12

  (438) 0x47fef4 FMUL	D1, D0, D1

  (438) 0x47fef8 STR	X11, [X23, X3,LSL #3]

  (438) 0x47fefc LDR	X24, [X6, X8,LSL #3]

  (438) 0x47ff00 STR	D1, [X27, X3,LSL #3]

  (438) 0x47ff04 ADD	X3, X3, #1

  (438) 0x47ff08 ADD	X9, X9, #1

  (438) 0x47ff0c CMP	X9, X24

  (438) 0x47ff10 B.LT	47fec8

0x47ff14 B	47fde0

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 865 - 989

--------------------------------------------------------------------------------

865:     for (i1 = ns; i1 < ne; i1++)

[...]

874:       if ( allsquare )

875:       {

876:          B_marker[i1] = jj_count_diag;

877:          C_diag_data[jj_count_diag] = zero;

878:          C_diag_j[jj_count_diag] = i1;

879:          jj_count_diag++;

[...]

886:       if (num_cols_offd_A)

887:       {

888:          for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++)

889:          {

890:             i2 = A_offd_j[jj2];

891:             a_entry = A_offd_data[jj2];

[...]

897:             for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++)

898:             {

899:                i3 = num_cols_diag_B+B_ext_offd_j[jj3];

[...]

907:                if (B_marker[i3] < jj_row_begin_offd)

908:                {

909:                   B_marker[i3] = jj_count_offd;

910:                   C_offd_data[jj_count_offd] = a_entry*B_ext_offd_data[jj3];

911:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

912:                   jj_count_offd++;

913:                }

914:                else

915:                   C_offd_data[B_marker[i3]] += a_entry*B_ext_offd_data[jj3];

916:             }

917:             for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++)

918:             {

919:                i3 = B_ext_diag_j[jj3];

920:                if (B_marker[i3] < jj_row_begin_diag)

921:                {

922:                   B_marker[i3] = jj_count_diag;

923:                   C_diag_data[jj_count_diag] = a_entry*B_ext_diag_data[jj3];

924:                   C_diag_j[jj_count_diag] = i3;

925:                   jj_count_diag++;

926:                }

927:                else

928:                   C_diag_data[B_marker[i3]] += a_entry*B_ext_diag_data[jj3];

[...]

937:       for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++)

938:       {

939:          i2 = A_diag_j[jj2];

940:          a_entry = A_diag_data[jj2];

[...]

946:          for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++)

947:          {

948:             i3 = B_diag_j[jj3];

[...]

956:             if (B_marker[i3] < jj_row_begin_diag)

957:             {

958:                B_marker[i3] = jj_count_diag;

959:                C_diag_data[jj_count_diag] = a_entry*B_diag_data[jj3];

960:                C_diag_j[jj_count_diag] = i3;

961:                jj_count_diag++;

962:             }

963:             else

964:             {

965:                C_diag_data[B_marker[i3]] += a_entry*B_diag_data[jj3];

966:             }

967:          }

968:          if (num_cols_offd_B)

969:          {

970:             for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++)

971:             {

972:                i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]];

[...]

980:                if (B_marker[i3] < jj_row_begin_offd)

981:                {

982:                   B_marker[i3] = jj_count_offd;

983:                   C_offd_data[jj_count_offd] = a_entry*B_offd_data[jj3];

984:                   C_offd_j[jj_count_offd] = i3-num_cols_diag_B;

985:                   jj_count_offd++;

986:                }

987:                else

988:                {

989:                   C_offd_data[B_marker[i3]] += a_entry*B_offd_data[jj3];

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	5.60
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.78
Bottlenecks	P10, P11, P12,
Function	.omp_outlined..9#0x47f990
Source	par_csr_matop.c:865-865,par_csr_matop.c:937-940,par_csr_matop.c:946-946,par_csr_matop.c:968-970
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.33
CQA cycles if no scalar integer	1.67
CQA cycles if FP arith vectorized	9.33
CQA cycles if fully vectorized	2.33
Front-end cycles	5.25
DIV/SQRT cycles	4.50
P0 cycles	4.50
P1 cycles	1.25
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	9.33
P10 cycles	9.33
P11 cycles	9.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	42.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.86
Bytes prefetched	0.00
Bytes loaded	232.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	5.60
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.78
Bottlenecks	P10, P11, P12,
Function	.omp_outlined..9#0x47f990
Source	par_csr_matop.c:865-865,par_csr_matop.c:937-940,par_csr_matop.c:946-946,par_csr_matop.c:968-970
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.33
CQA cycles if no scalar integer	1.67
CQA cycles if FP arith vectorized	9.33
CQA cycles if fully vectorized	2.33
Front-end cycles	5.25
DIV/SQRT cycles	4.50
P0 cycles	4.50
P1 cycles	1.25
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	9.33
P10 cycles	9.33
P11 cycles	9.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	42.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.86
Bytes prefetched	0.00
Bytes loaded	232.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..9#0x47f990
Source file and lines	par_csr_matop.c:865-989
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:865,874-879,886-891,897-899,907-928,937-940,946-948,956-972,980-989.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:865,937-940,946,968-970.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.33 to 1.67 cycles (5.60x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 9.33 to 2.33 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 232 bytes.

General properties

nb instructions	42
loop length	168
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	9.33	9.33	9.33	0.00	0.00
cycles	4.50	4.50	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	9.33	9.33	9.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	5.25
Overall L1	9.33

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.33 cycles. At this rate:

25% of peak load performance is reached (24.86 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 47fde0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDP X30, X21, [SP, #88]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
B 47fdb8 <.omp_outlined..9+0x428>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X5, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X8, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X6, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X8, [SP, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X7, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X8, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X30, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 47fdf0 <.omp_outlined..9+0x460>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X8, [X15, X26,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X4, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GE 47fbc0 <.omp_outlined..9+0x230>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X9, [X16, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D0, [X17, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X8, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X10, [X18, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X27, [X18, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X10, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GE 47fe78 <.omp_outlined..9+0x4e8>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDUR X11, [X29, #456]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X24, [X25]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X23, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR X11, [X29, #496]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 47fe40 <.omp_outlined..9+0x4b0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X10, [X28]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CBZ X10, 47fde0 <.omp_outlined..9+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X9, [X6, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X24, [X6, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X9, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GE 47fde0 <.omp_outlined..9+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDUR X11, [X29, #480]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR X10, [X29, #448]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X27, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR X11, [X29, #488]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X23, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 47fec8 <.omp_outlined..9+0x538>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
B 47fde0 <.omp_outlined..9+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..9#0x47f990
Source file and lines	par_csr_matop.c:865-989
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:865,874-879,886-891,897-899,907-928,937-940,946-948,956-972,980-989.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c:865,937-940,946,968-970.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.33 to 1.67 cycles (5.60x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 9.33 to 2.33 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 232 bytes.

General properties

nb instructions	42
loop length	168
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	9.33	9.33	9.33	0.00	0.00
cycles	4.50	4.50	1.25	1.25	1.25	1.25	0.00	0.00	0.00	0.00	9.33	9.33	9.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	5.25
Overall L1	9.33

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.33 cycles. At this rate:

25% of peak load performance is reached (24.86 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 47fde0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDP X30, X21, [SP, #88]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	1
B 47fdb8 <.omp_outlined..9+0x428>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X5, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X8, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X6, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X8, [SP, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X7, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X8, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X30, [X8]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 47fdf0 <.omp_outlined..9+0x460>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X8, [X15, X26,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X4, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GE 47fbc0 <.omp_outlined..9+0x230>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X9, [X16, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D0, [X17, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X8, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X10, [X18, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X27, [X18, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X10, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GE 47fe78 <.omp_outlined..9+0x4e8>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDUR X11, [X29, #456]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X24, [X25]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X23, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR X11, [X29, #496]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 47fe40 <.omp_outlined..9+0x4b0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X10, [X28]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CBZ X10, 47fde0 <.omp_outlined..9+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X9, [X6, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X24, [X6, X8,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP X9, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GE 47fde0 <.omp_outlined..9+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDUR X11, [X29, #480]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR X10, [X29, #448]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X27, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR X11, [X29, #488]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X23, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B 47fec8 <.omp_outlined..9+0x538>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
B 47fde0 <.omp_outlined..9+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code