OV - exec - Loop 26

0x4973b8 LDR	X7, [X0, X3,LSL #3]    [1]

0x4973bc LDR	D1, [X1, X3,LSL #3]    [2]

0x4973c0 LDR	X24, [X20, X7,LSL #3]    [5]

0x4973c4 CMP	X24, X17

0x4973c8 B.GE	4973a0

0x4973cc STR	X9, [X20, X7,LSL #3]    [5]

0x4973d0 STR	X7, [X6, X9,LSL #3]    [4]

0x4973d4 FMUL	D1, D0, D1

0x4973d8 ADD	X9, X9, #1

0x4973dc LDR	X5, [X20, X7,LSL #3]    [5]

0x4973e0 STR	D1, [X4, X5,LSL #3]    [3]

0x4973e4 LDR	X5, [X16, X2,LSL #3]    [6]

0x4973e8 ADD	X3, X3, #1

0x4973ec CMP	X3, X5

0x4973f0 B.LT	4973b8

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c: 286 - 295

--------------------------------------------------------------------------------

286: 	 for (ib = B_i[ja]; ib < B_i[ja+1]; ib++)

287: 	 {

288: 	    jb = B_j[ib];

289: 	    b_entry = B_data[ib];

290: 	    if (B_marker[jb] < row_start)

291: 	    {

292: 		B_marker[jb] = counter;

293: 		C_j[B_marker[jb]] = jb;

294: 		C_data[B_marker[jb]] = a_entry*b_entry;

295: 		counter++;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.89
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.06
Bottlenecks	P10,
Function	.omp_outlined.#0x496ee0
Source	csr_matop.c:286-295
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.83
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	2.83
CQA cycles if fully vectorized	0.71
Front-end cycles	1.88
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	2.83
P10 cycles	2.50
P11 cycles	2.67
P12 cycles	1.00
P13 cycles	1.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	15.00
Nb uops	15.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.35
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.59
Bytes prefetched	0.00
Bytes loaded	40.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.89
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.06
Bottlenecks	P10,
Function	.omp_outlined.#0x496ee0
Source	csr_matop.c:286-295
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.83
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	2.83
CQA cycles if fully vectorized	0.71
Front-end cycles	1.88
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	1.00
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	2.83
P10 cycles	2.50
P11 cycles	2.67
P12 cycles	1.00
P13 cycles	1.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	15.00
Nb uops	15.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.35
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.59
Bytes prefetched	0.00
Bytes loaded	40.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined.#0x496ee0
Source file and lines	csr_matop.c:286-295
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:286-295.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 2.83 to 1.50 cycles (1.89x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 2.83 to 0.71 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is loading 40 bytes. The binary loop is storing 24 bytes.

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	15
loop length	60
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	1.00	1.00	1.00	1.00	0.50	0.50	0.50	0.50	2.83	2.50	2.67	1.00	1.00
cycles	1.00	1.00	1.00	1.00	1.00	1.00	0.50	0.50	0.50	0.50	2.83	2.50	2.67	1.00	1.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.88
Data deps.	1.00
Overall L1	2.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.83 cycles. At this rate:

14% of peak load performance is reached (14.12 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (8.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4973b8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X7, [X0, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D1, [X1, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X24, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X24, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4973a0 <.omp_outlined.+0x4c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X9, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X7, [X6, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
FMUL D1, D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X5, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR D1, [X4, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR X5, [X16, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X3, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4973b8 <.omp_outlined.+0x4d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined.#0x496ee0
Source file and lines	csr_matop.c:286-295
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:286-295.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 2.83 to 1.50 cycles (1.89x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 2.83 to 0.71 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is loading 40 bytes. The binary loop is storing 24 bytes.

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	15
loop length	60
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	1.00	1.00	1.00	1.00	0.50	0.50	0.50	0.50	2.83	2.50	2.67	1.00	1.00
cycles	1.00	1.00	1.00	1.00	1.00	1.00	0.50	0.50	0.50	0.50	2.83	2.50	2.67	1.00	1.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.88
Data deps.	1.00
Overall L1	2.83

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.83 cycles. At this rate:

14% of peak load performance is reached (14.12 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (8.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4973b8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X7, [X0, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D1, [X1, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X24, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X24, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4973a0 <.omp_outlined.+0x4c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X9, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X7, [X6, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
FMUL D1, D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X5, [X20, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR D1, [X4, X5,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR X5, [X16, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X3, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4973b8 <.omp_outlined.+0x4d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code