OV - exec - Loop 169

	Loop Id: 169	Module: exec	Source: par_lr_interp.c:1494-1545 [...]	Coverage: 0.01%

0x43a054 LDUR	X0, [X29, #440]

0x43a058 HINT	#0

0x43a05c HINT	#0

0x43a060 LDR	X15, [X11, X9,LSL #3]

0x43a064 ADD	X8, X8, #1

0x43a068 CMP	X8, X15

0x43a06c B.GE	43a20c

0x43a070 LDR	X15, [X12, X8,LSL #3]

0x43a074 LDR	X17, [X10, X15,LSL #3]

0x43a078 TBNZ	X17, #63, 43a0a8

0x43a07c LDR	X17, [X22, X15,LSL #3]

0x43a080 CMP	X17, X5

0x43a084 B.GE	43a060

0x43a088 STR	X7, [X22, X15,LSL #3]

0x43a08c LDR	X15, [X18, X15,LSL #3]

0x43a090 STR	X15, [X6, X7,LSL #3]

0x43a094 LDUR	X15, [X29, #496]

0x43a098 LDR	D2, [X15]

0x43a09c STR	D2, [X19, X7,LSL #3]

0x43a0a0 ADD	X7, X7, #1

0x43a0a4 B	43a060

0x43a0a8 CMN	X17, #3

0x43a0ac B.EQ	43a060

0x43a0b0 STR	X30, [X22, X15,LSL #3]

0x43a0b4 ADD	X20, X15, #1

0x43a0b8 LDR	X2, [X11, X15,LSL #3]

0x43a0bc LDR	X27, [X11, X20,LSL #3]

0x43a0c0 CMP	X2, X27

0x43a0c4 B.GE	43a12c

0x43a0c8 LDUR	X17, [X29, #408]

0x43a0cc LDR	X3, [X17]

0x43a0d0 LDUR	X17, [X29, #392]

0x43a0d4 LDR	X21, [X17]

0x43a0d8 LDUR	X17, [X29, #448]

0x43a0dc LDR	X0, [X17]

0x43a0e0 B	43a0f0

  (172) 0x43a0e4 ADD	X2, X2, #1

  (172) 0x43a0e8 CMP	X2, X27

  (172) 0x43a0ec B.GE	43a12c

  (172) 0x43a0f0 LDR	X17, [X12, X2,LSL #3]

  (172) 0x43a0f4 LDR	X25, [X10, X17,LSL #3]

  (172) 0x43a0f8 TBNZ	X25, #63, 43a0e4

  (172) 0x43a0fc LDR	X25, [X22, X17,LSL #3]

  (172) 0x43a100 CMP	X25, X5

  (172) 0x43a104 B.GE	43a0e4

  (172) 0x43a108 STR	X7, [X22, X17,LSL #3]

  (172) 0x43a10c LDR	X17, [X3, X17,LSL #3]

  (172) 0x43a110 STR	X17, [X21, X7,LSL #3]

  (172) 0x43a114 LDUR	X17, [X29, #496]

  (172) 0x43a118 LDR	D2, [X17]

  (172) 0x43a11c LDR	X27, [X11, X20,LSL #3]

  (172) 0x43a120 STR	D2, [X0, X7,LSL #3]

  (172) 0x43a124 ADD	X7, X7, #1

  (172) 0x43a128 B	43a0e4

0x43a12c LDUR	X17, [X29, #488]

0x43a130 LDUR	X0, [X29, #440]

0x43a134 LDR	X17, [X17]

0x43a138 CMP	X17, #2

0x43a13c B.LT	43a060

0x43a140 LDR	X21, [X13, X15,LSL #3]

0x43a144 LDR	X2, [X13, X20,LSL #3]

0x43a148 CMP	X21, X2

0x43a14c B.GE	43a060

0x43a150 LDUR	X15, [X29, #344]

0x43a154 LDR	X27, [X15]

0x43a158 LDUR	X15, [X29, #336]

0x43a15c LDR	X3, [X15]

0x43a160 LDUR	X15, [X29, #416]

0x43a164 LDR	X15, [X15]

0x43a168 CBNZ	X14, 43a18c

0x43a16c B	43a1d4

  (170) 0x43a180 ADD	X21, X21, #1

  (170) 0x43a184 CMP	X21, X2

  (170) 0x43a188 B.GE	43a054

  (170) 0x43a18c LDR	X17, [X27, X21,LSL #3]

  (170) 0x43a190 LDR	X17, [X14, X17,LSL #3]

  (170) 0x43a194 LDR	X0, [X16, X17,LSL #3]

  (170) 0x43a198 TBNZ	X0, #63, 43a180

  (170) 0x43a19c LDR	X0, [X23, X17,LSL #3]

  (170) 0x43a1a0 CMP	X0, X1

  (170) 0x43a1a4 B.GE	43a180

  (170) 0x43a1a8 STR	X4, [X23, X17,LSL #3]

  (170) 0x43a1ac STR	X17, [X3, X4,LSL #3]

  (170) 0x43a1b0 LDUR	X17, [X29, #496]

  (170) 0x43a1b4 LDR	X2, [X13, X20,LSL #3]

  (170) 0x43a1b8 LDR	D2, [X17]

  (170) 0x43a1bc STR	D2, [X15, X4,LSL #3]

  (170) 0x43a1c0 ADD	X4, X4, #1

  (170) 0x43a1c4 B	43a180

  (171) 0x43a1c8 ADD	X21, X21, #1

  (171) 0x43a1cc CMP	X21, X2

  (171) 0x43a1d0 B.GE	43a054

  (171) 0x43a1d4 LDR	X17, [X27, X21,LSL #3]

  (171) 0x43a1d8 LDR	X0, [X16, X17,LSL #3]

  (171) 0x43a1dc TBNZ	X0, #63, 43a1c8

  (171) 0x43a1e0 LDR	X0, [X23, X17,LSL #3]

  (171) 0x43a1e4 CMP	X0, X1

  (171) 0x43a1e8 B.GE	43a1c8

  (171) 0x43a1ec STR	X4, [X23, X17,LSL #3]

  (171) 0x43a1f0 STR	X17, [X3, X4,LSL #3]

  (171) 0x43a1f4 LDUR	X17, [X29, #496]

  (171) 0x43a1f8 LDR	X2, [X13, X20,LSL #3]

  (171) 0x43a1fc LDR	D2, [X17]

  (171) 0x43a200 STR	D2, [X15, X4,LSL #3]

  (171) 0x43a204 ADD	X4, X4, #1

  (171) 0x43a208 B	43a1c8

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c: 1494 - 1545

--------------------------------------------------------------------------------

1494:            for (jj = S_diag_i[i]; jj < S_diag_i[i+1]; jj++)

1495:            {

1496:              i1 = S_diag_j[jj];

[...]

1503:              if (CF_marker[i1] >= 0)

1504:              {

1505:                if (P_marker[i1] < jj_begin_row)

1506:                {

1507:                  P_marker[i1] = jj_counter;

1508:                  P_diag_j[jj_counter]    = fine_to_coarse[i1];

1509:                  P_diag_data[jj_counter] = zero;

1510:                  jj_counter++;

1511:                }

1512:              }

1513:              else  if (CF_marker[i1] != -3)

1514:              {

1515:                P_marker[i1] = strong_f_marker;

1516:                for (kk = S_diag_i[i1]; kk < S_diag_i[i1+1]; kk++)

1517:                {

1518:                  k1 = S_diag_j[kk];

1519:                  if (CF_marker[k1] >= 0)

1520:                  {

1521:                    if(P_marker[k1] < jj_begin_row)

1522:                    {

1523:                      P_marker[k1] = jj_counter;

1524:                      P_diag_j[jj_counter] = fine_to_coarse[k1];

1525:                      P_diag_data[jj_counter] = zero;

1526:                      jj_counter++;

1527:                    }

1528:                  }

1529:                }

1530:                if(num_procs > 1)

1531:                {

1532:                  for (kk = S_offd_i[i1]; kk < S_offd_i[i1+1]; kk++)

1533:                  {

1534:                    if(col_offd_S_to_A)

1535:                     k1 = col_offd_S_to_A[S_offd_j[kk]];

1536:                    else

1537:                     k1 = S_offd_j[kk];

1538:                    if(CF_marker_offd[k1] >= 0)

1539:                    {

1540:                      if(P_marker_offd[k1] < jj_begin_row_offd)

1541:                      {

1542:                        P_marker_offd[k1] = jj_counter_offd;

1543:                        P_offd_j[jj_counter_offd] = k1;

1544:                        P_offd_data[jj_counter_offd] = zero;

1545:                        jj_counter_offd++;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	4.77
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.62
Bottlenecks	P10, P11, P12,
Function	.omp_outlined.#0x439400
Source	par_lr_interp.c:1494-1496,par_lr_interp.c:1503-1510,par_lr_interp.c:1513-1516,par_lr_interp.c:1526-1526,par_lr_interp.c:1530-1534
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.33
CQA cycles if no scalar integer	2.17
CQA cycles if FP arith vectorized	10.33
CQA cycles if fully vectorized	2.58
Front-end cycles	6.38
DIV/SQRT cycles	5.50
P0 cycles	5.50
P1 cycles	2.25
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.25
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	10.33
P10 cycles	10.33
P11 cycles	10.33
P12 cycles	1.50
P13 cycles	1.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	53.00
Nb uops	51.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	216.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	4.77
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.62
Bottlenecks	P10, P11, P12,
Function	.omp_outlined.#0x439400
Source	par_lr_interp.c:1494-1496,par_lr_interp.c:1503-1510,par_lr_interp.c:1513-1516,par_lr_interp.c:1526-1526,par_lr_interp.c:1530-1534
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.33
CQA cycles if no scalar integer	2.17
CQA cycles if FP arith vectorized	10.33
CQA cycles if fully vectorized	2.58
Front-end cycles	6.38
DIV/SQRT cycles	5.50
P0 cycles	5.50
P1 cycles	2.25
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.25
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	10.33
P10 cycles	10.33
P11 cycles	10.33
P12 cycles	1.50
P13 cycles	1.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	53.00
Nb uops	51.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	216.00
Bytes stored	32.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined.#0x439400
Source file and lines	par_lr_interp.c:1494-1545
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1494-1496,1503-1545.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1494-1496,1503-1510,1513-1516,1526,1530-1534.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.33 to 2.17 cycles (4.77x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 10.33 to 2.58 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 216 bytes. The binary loop is storing 32 bytes.

General properties

nb instructions	53
loop length	212
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	2.25	2.25	2.25	2.25	0.50	0.50	0.00	0.00	10.33	10.33	10.33	1.50	1.50
cycles	5.50	5.50	2.25	2.25	2.25	2.25	0.50	0.50	0.00	0.00	10.33	10.33	10.33	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.38
Overall L1	10.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.33 cycles. At this rate:

21% of peak load performance is reached (20.90 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.10 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 43a070

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDUR X0, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
HINT #0
HINT #0
LDR X15, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 43a20c <.omp_outlined.+0xe0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [X12, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X10, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
TBNZ X17, #63, 43a0a8 <.omp_outlined.+0xca8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X17, [X22, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X17, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 43a060 <.omp_outlined.+0xc60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X7, [X22, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [X18, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X15, [X6, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X15, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D2, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D2, [X19, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X7, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 43a060 <.omp_outlined.+0xc60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMN X17, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 43a060 <.omp_outlined.+0xc60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X30, [X22, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X20, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X2, [X11, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [X11, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X2, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 43a12c <.omp_outlined.+0xd2c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X17, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X17, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X17, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 43a0f0 <.omp_outlined.+0xcf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X17, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X0, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X17, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 43a060 <.omp_outlined.+0xc60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X21, [X13, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X13, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X21, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 43a060 <.omp_outlined.+0xc60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X15, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X15, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X15, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X14, 43a18c <.omp_outlined.+0xd8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 43a1d4 <.omp_outlined.+0xdd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined.#0x439400
Source file and lines	par_lr_interp.c:1494-1545
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.33 to 2.17 cycles (4.77x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 216 bytes. The binary loop is storing 32 bytes.

General properties

nb instructions	53
loop length	212
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	2.25	2.25	2.25	2.25	0.50	0.50	0.00	0.00	10.33	10.33	10.33	1.50	1.50
cycles	5.50	5.50	2.25	2.25	2.25	2.25	0.50	0.50	0.00	0.00	10.33	10.33	10.33	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.38
Overall L1	10.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.33 cycles. At this rate:

21% of peak load performance is reached (20.90 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.10 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 43a070

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDUR X0, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
HINT #0
HINT #0
LDR X15, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 43a20c <.omp_outlined.+0xe0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X15, [X12, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X10, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
TBNZ X17, #63, 43a0a8 <.omp_outlined.+0xca8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X17, [X22, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X17, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 43a060 <.omp_outlined.+0xc60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X7, [X22, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [X18, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X15, [X6, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X15, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D2, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR D2, [X19, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
ADD X7, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 43a060 <.omp_outlined.+0xc60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMN X17, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 43a060 <.omp_outlined.+0xc60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X30, [X22, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X20, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X2, [X11, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [X11, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X2, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 43a12c <.omp_outlined.+0xd2c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X17, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X17, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X17, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 43a0f0 <.omp_outlined.+0xcf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X17, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X0, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X17, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 43a060 <.omp_outlined.+0xc60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X21, [X13, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X13, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X21, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 43a060 <.omp_outlined.+0xc60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X15, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X15, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X15, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X14, 43a18c <.omp_outlined.+0xd8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 43a1d4 <.omp_outlined.+0xdd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code