OV - exec - Loop 1617

0x4979a0 SDIV	X12, X11, X26

0x4979a4 MSUB	X13, X26, X12, X11

0x4979a8 MADD	X12, X9, X13, X12

0x4979ac SDIV	X13, X10, X26

0x4979b0 MSUB	X10, X13, X26, X10

0x4979b4 MADD	X9, X9, X10, X13

0x4979b8 LDR	X10, [X8, X12,LSL #3]    [1]

0x4979bc LDR	X9, [X8, X9,LSL #3]    [2]

0x4979c0 ADD	X9, X10, X9

0x4979c4 ORR	X10, XZR, X11

0x4979c8 ADD	X11, X11, #1

0x4979cc STR	X9, [X8, X12,LSL #3]    [1]

0x4979d0 LDR	X9, [X19]    [3]

0x4979d4 MADD	X12, X9, X28, XZR

0x4979d8 CMP	X11, X12

0x4979dc B.LT	4979a0

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c: 380 - 500

--------------------------------------------------------------------------------

380:   return idx%dim1*dim2 + idx/dim1;

[...]

496:    for (i = my_thread_num*num_colsA + 1; i < (my_thread_num + 1)*num_colsA; ++i) {

497:      HYPRE_Int transpose_i = transpose_idx(i, num_threads, num_colsA);

498:      HYPRE_Int transpose_i_minus_1 = transpose_idx(i - 1, num_threads, num_colsA);

499:

500:      bucket[transpose_i] += bucket[transpose_i_minus_1];

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.43 - 5.71
Bottlenecks	P6, P8,
Function	.omp_outlined..7#0x4977a0
Source	csr_matop.c:380-380,csr_matop.c:496-500
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.00 - 40.00
CQA cycles if no scalar integer	10.00 - 40.00
CQA cycles if FP arith vectorized	10.00 - 40.00
CQA cycles if fully vectorized	5.00 - 20.00
Front-end cycles	2.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	1.50
P2 cycles	1.25
P3 cycles	7.00
P4 cycles	1.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.50
P10 cycles	1.17
P11 cycles	1.33
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	10.00 - 40.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	16.00
Nb uops	16.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00 - 0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.80 - 3.20
Bytes prefetched	0.00
Bytes loaded	24.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.43 - 5.71
Bottlenecks	P6, P8,
Function	.omp_outlined..7#0x4977a0
Source	csr_matop.c:380-380,csr_matop.c:496-500
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.00 - 40.00
CQA cycles if no scalar integer	10.00 - 40.00
CQA cycles if FP arith vectorized	10.00 - 40.00
CQA cycles if fully vectorized	5.00 - 20.00
Front-end cycles	2.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	1.50
P2 cycles	1.25
P3 cycles	7.00
P4 cycles	1.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.50
P10 cycles	1.17
P11 cycles	1.33
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	10.00 - 40.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	16.00
Nb uops	16.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00 - 0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.80 - 3.20
Bytes prefetched	0.00
Bytes loaded	24.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..7#0x4977a0
Source file and lines	csr_matop.c:380-500
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:380,496-500.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 40.00 to 20.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 24 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	16
loop length	64
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.50	1.25	7.00	1.25	0.00	0.00	0.00	0.00	1.50	1.17	1.33	0.50	0.50
cycles	0.50	0.50	1.50	1.25	7.00	1.25	0.00	0.00	0.00	0.00	1.50	1.17	1.33	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	10.00-40.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.00
Data deps.	1.00
Overall L1	10.00-40.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 40.00 cycles. At this rate:

0% of peak load performance is reached (0.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4979a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
SDIV X12, X11, X26	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20
MSUB X13, X26, X12, X11	1	0	0	0	0	1	0	0	0	0	0	0	2	1
MADD X12, X9, X13, X12	1	0	0	0	0	1	0	0	0	0	0	0	2	1
SDIV X13, X10, X26	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20
MSUB X10, X13, X26, X10	1	0	0	0	0	1	0	0	0	0	0	0	2	1
MADD X9, X9, X10, X13	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X10, [X8, X12,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X10, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X9, [X8, X12,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X19]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X12, X9, X28, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 4979a0 <.omp_outlined..7+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..7#0x4977a0
Source file and lines	csr_matop.c:380-500
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:380,496-500.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 40.00 to 20.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 24 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	16
loop length	64
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.50	1.25	7.00	1.25	0.00	0.00	0.00	0.00	1.50	1.17	1.33	0.50	0.50
cycles	0.50	0.50	1.50	1.25	7.00	1.25	0.00	0.00	0.00	0.00	1.50	1.17	1.33	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	10.00-40.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.00
Data deps.	1.00
Overall L1	10.00-40.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 40.00 cycles. At this rate:

0% of peak load performance is reached (0.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4979a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
SDIV X12, X11, X26	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20
MSUB X13, X26, X12, X11	1	0	0	0	0	1	0	0	0	0	0	0	2	1
MADD X12, X9, X13, X12	1	0	0	0	0	1	0	0	0	0	0	0	2	1
SDIV X13, X10, X26	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20
MSUB X10, X13, X26, X10	1	0	0	0	0	1	0	0	0	0	0	0	2	1
MADD X9, X9, X10, X13	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X10, [X8, X12,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X10, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X11, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR X9, [X8, X12,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X19]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X12, X9, X28, XZR	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 4979a0 <.omp_outlined..7+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code