OV - exec - Loop 1169

	Loop Id: 1169	Module: exec	Source: par_multi_interp.c:1774-1876 [...]	Coverage: 0.15%

0x435fc8 LDUR	X9, [X29, #368]

0x435fcc ADD	X27, X27, #1

0x435fd0 CMP	X27, X9

0x435fd4 B.GE	4367d8

0x435fd8 LDUR	X9, [X29, #400]

0x435fdc LDR	X11, [X9, X27,LSL #3]

0x435fe0 LDUR	X9, [X29, #392]

0x435fe4 ADD	X12, X11, #1

0x435fe8 LDR	X9, [X9, X11,LSL #3]

0x435fec LDR	X16, [X4, X11,LSL #3]

0x435ff0 LDR	X0, [X4, X12,LSL #3]

0x435ff4 ADD	X13, X0, X9

0x435ff8 SUB	X13, X13, X16

0x435ffc CMP	X9, X13

0x436000 B.GE	4360ac

0x436004 SUB	W18, W0, W16

0x436008 ADD	X15, X16, #1

0x43600c TBZ	W18, #0, 436034

0x436010 LDR	X18, [X28]

0x436014 LDR	X14, [SP, #56]

0x436018 STR	XZR, [X8, X16,LSL #3]

0x43601c LDR	X18, [X2, X18,LSL #3]

0x436020 LDR	X18, [X18, X9,LSL #3]

0x436024 ADD	X9, X9, #1

0x436028 STR	X16, [X21, X18,LSL #3]

0x43602c STR	X18, [X14, X16,LSL #3]

0x436030 ORR	X16, XZR, X15

0x436034 CMP	X0, X15

0x436038 B.EQ	4360ac

0x43603c LDR	X14, [SP, #40]

0x436040 UBFM	X15, X16, #61, #60

0x436044 ADD	X0, X14, X15

0x436048 LDR	X14, [SP, #32]

0x43604c ADD	X1, X14, X15

0x436050 HINT	#0

0x436054 HINT	#0

0x436058 HINT	#0

0x43605c HINT	#0

  (1176) 0x436060 LDR	X15, [X28]

  (1176) 0x436064 UBFM	X18, X9, #61, #60

  (1176) 0x436068 ADD	X9, X9, #2

  (1176) 0x43606c CMP	X13, X9

  (1176) 0x436070 LDR	X15, [X2, X15,LSL #3]

  (1176) 0x436074 LDR	X15, [X15, X18]

  (1176) 0x436078 STR	X16, [X21, X15,LSL #3]

  (1176) 0x43607c STP	XZR, XZR, [X1, #1016]

  (1176) 0x436080 STUR	X15, [X0, #504]

  (1176) 0x436084 ADD	X1, X1, #16

  (1176) 0x436088 LDR	X15, [X28]

  (1176) 0x43608c LDR	X15, [X2, X15,LSL #3]

  (1176) 0x436090 ADD	X15, X15, X18

  (1176) 0x436094 ADD	X18, X16, #1

  (1176) 0x436098 ADD	X16, X16, #2

  (1176) 0x43609c LDR	X15, [X15, #8]

  (1176) 0x4360a0 STR	X18, [X21, X15,LSL #3]

  (1176) 0x4360a4 STR	X15, [X0], #16

  (1176) 0x4360a8 B.NE	436060

0x4360ac LDUR	X9, [X29, #384]

0x4360b0 LDUR	X14, [X29, #464]

0x4360b4 LDR	X9, [X9, X11,LSL #3]

0x4360b8 LDR	X0, [X14, X12,LSL #3]

0x4360bc LDR	X16, [X14, X11,LSL #3]

0x4360c0 ADD	X13, X0, X9

0x4360c4 SUB	X13, X13, X16

0x4360c8 CMP	X9, X13

0x4360cc B.GE	43616c

0x4360d0 SUB	W18, W0, W16

0x4360d4 ADD	X15, X16, #1

0x4360d8 TBZ	W18, #0, 436100

0x4360dc LDR	X18, [X28]

0x4360e0 LDR	X14, [SP, #48]

0x4360e4 STR	XZR, [X10, X16,LSL #3]

0x4360e8 LDR	X18, [X3, X18,LSL #3]

0x4360ec LDR	X18, [X18, X9,LSL #3]

0x4360f0 ADD	X9, X9, #1

0x4360f4 STR	X16, [X22, X18,LSL #3]

0x4360f8 STR	X18, [X14, X16,LSL #3]

0x4360fc ORR	X16, XZR, X15

0x436100 CMP	X0, X15

0x436104 B.EQ	43616c

0x436108 LDR	X14, [SP, #24]

0x43610c UBFM	X15, X16, #61, #60

0x436110 ADD	X0, X14, X15

0x436114 LDR	X14, [SP, #16]

0x436118 ADD	X1, X14, X15

0x43611c HINT	#0

  (1175) 0x436120 LDR	X15, [X28]

  (1175) 0x436124 UBFM	X18, X9, #61, #60

  (1175) 0x436128 ADD	X9, X9, #2

  (1175) 0x43612c CMP	X13, X9

  (1175) 0x436130 LDR	X15, [X3, X15,LSL #3]

  (1175) 0x436134 LDR	X15, [X15, X18]

  (1175) 0x436138 STR	X16, [X22, X15,LSL #3]

  (1175) 0x43613c STP	XZR, XZR, [X1, #1016]

  (1175) 0x436140 STUR	X15, [X0, #504]

  (1175) 0x436144 ADD	X1, X1, #16

  (1175) 0x436148 LDR	X15, [X28]

  (1175) 0x43614c LDR	X15, [X3, X15,LSL #3]

  (1175) 0x436150 ADD	X15, X15, X18

  (1175) 0x436154 ADD	X18, X16, #1

  (1175) 0x436158 ADD	X16, X16, #2

  (1175) 0x43615c LDR	X15, [X15, #8]

  (1175) 0x436160 STR	X18, [X22, X15,LSL #3]

  (1175) 0x436164 STR	X15, [X0], #16

  (1175) 0x436168 B.NE	436120

0x43616c LDR	X9, [X5, X11,LSL #3]

0x436170 LDR	X13, [X5, X12,LSL #3]

0x436174 B	436184

  (1174) 0x436180 ADD	X9, X9, #1

  (1174) 0x436184 CMP	X9, X13

  (1174) 0x436188 B.GE	4361c0

  (1174) 0x43618c LDR	X15, [X6, X9,LSL #3]

  (1174) 0x436190 LDR	X18, [X28]

  (1174) 0x436194 LDR	X16, [X23, X15,LSL #3]

  (1174) 0x436198 SUB	X18, X18, #1

  (1174) 0x43619c CMP	X16, X18

  (1174) 0x4361a0 B.NE	436180

  (1174) 0x4361a4 STR	X11, [X19, X15,LSL #3]

  (1174) 0x4361a8 LDR	X13, [X5, X12,LSL #3]

  (1174) 0x4361ac B	436180

0x4361c0 LDR	X9, [X24, X11,LSL #3]

0x4361c4 LDR	X13, [X24, X12,LSL #3]

0x4361c8 B	4361d0

  (1173) 0x4361cc ADD	X9, X9, #1

  (1173) 0x4361d0 CMP	X9, X13

  (1173) 0x4361d4 B.GE	436200

  (1173) 0x4361d8 LDR	X15, [X25, X9,LSL #3]

  (1173) 0x4361dc LDR	X18, [X28]

  (1173) 0x4361e0 LDR	X16, [X26, X15,LSL #3]

  (1173) 0x4361e4 SUB	X18, X18, #1

  (1173) 0x4361e8 CMP	X16, X18

  (1173) 0x4361ec B.NE	4361cc

  (1173) 0x4361f0 STR	X11, [X20, X15,LSL #3]

  (1173) 0x4361f4 LDR	X13, [X24, X12,LSL #3]

  (1173) 0x4361f8 B	4361cc

0x436200 LDUR	X9, [X29, #376]

0x436204 MOVI	D2, #0

0x436208 LDR	X13, [X9, X11,LSL #3]

0x43620c LDR	X16, [X9, X12,LSL #3]

0x436210 ADD	X7, X13, #1

0x436214 STP	X13, X27, [X29, #936]

0x436218 CMP	X7, X16

0x43621c B.GE	4364a0

0x436220 LDUR	X13, [X29, #408]

0x436224 LDR	X9, [SP, #72]

0x436228 MOVI	D1, #0

0x43622c MOVI	D2, #0

0x436230 LDR	X6, [X13]

0x436234 LDUR	X13, [X29, #416]

0x436238 LDR	X9, [X9]

0x43623c LDR	X26, [X13]

0x436240 LDP	X15, X13, [SP, #160]

0x436244 LDR	X23, [X13]

0x436248 LDR	X13, [SP, #152]

0x43624c LDR	X17, [X15]

0x436250 LDR	X25, [X13]

0x436254 LDP	X13, X15, [X29, #1000]

0x436258 LDR	X27, [X15]

0x43625c LDR	X13, [X13]

0x436260 ADD	X14, X25, #8

0x436264 ADD	X15, X13, #8

0x436268 STP	X14, X15, [X29, #984]

0x43626c ADD	X14, X27, #8

0x436270 ADD	X15, X17, #8

0x436274 STP	X15, X14, [X29, #952]

0x436278 ORR	X14, XZR, X17

0x43627c LDUR	X17, [X29, #464]

0x436280 LDR	X5, [SP, #64]

0x436284 B	4362ac

  (1170) 0x436288 LDR	D3, [X23, X7,LSL #3]

  (1170) 0x43628c FADD	D1, D1, D3

  (1170) 0x436290 HINT	#0

  (1170) 0x436294 HINT	#0

  (1170) 0x436298 HINT	#0

  (1170) 0x43629c HINT	#0

  (1170) 0x4362a0 ADD	X7, X7, #1

  (1170) 0x4362a4 CMP	X7, X16

  (1170) 0x4362a8 B.EQ	4364c0

  (1170) 0x4362ac LDR	X0, [X5, X7,LSL #3]

  (1170) 0x4362b0 LDR	X15, [X19, X0,LSL #3]

  (1170) 0x4362b4 CMP	X15, X11

  (1170) 0x4362b8 B.NE	4362e8

  (1170) 0x4362bc ADD	X1, X0, #1

  (1170) 0x4362c0 LDR	X24, [X4, X0,LSL #3]

  (1170) 0x4362c4 LDR	X2, [X4, X1,LSL #3]

  (1170) 0x4362c8 CMP	X2, X24

  (1170) 0x4362cc B.LE	4363bc

  (1170) 0x4362d0 SUB	W15, W2, W24

  (1170) 0x4362d4 ADD	X3, X24, #1

  (1170) 0x4362d8 TBNZ	W15, #0, 436310

  (1170) 0x4362dc CMP	X2, X3

  (1170) 0x4362e0 B.NE	436344

  (1170) 0x4362e4 B	4363bc

  (1170) 0x4362e8 LDR	X15, [X9, X0,LSL #3]

  (1170) 0x4362ec CMN	X15, #3

  (1170) 0x4362f0 B.EQ	4362a0

  (1170) 0x4362f4 CMP	X6, #1

  (1170) 0x4362f8 B.EQ	436288

  (1170) 0x4362fc LDR	X15, [X26, X11,LSL #3]

  (1170) 0x436300 LDR	X18, [X26, X0,LSL #3]

  (1170) 0x436304 CMP	X15, X18

  (1170) 0x436308 B.EQ	436288

  (1170) 0x43630c B	4362a0

  (1170) 0x436310 LDR	X15, [X25, X24,LSL #3]

  (1170) 0x436314 LDR	D0, [X23, X7,LSL #3]

  (1170) 0x436318 LDR	D3, [X13, X24,LSL #3]

  (1170) 0x43631c ORR	X24, XZR, X3

  (1170) 0x436320 FMUL	D0, D0, D3

  (1170) 0x436324 LDR	X15, [X21, X15,LSL #3]

  (1170) 0x436328 LDR	D3, [X13, X15,LSL #3]

  (1170) 0x43632c FADD	D2, D2, D0

  (1170) 0x436330 FADD	D1, D1, D0

  (1170) 0x436334 FADD	D3, D0, D3

  (1170) 0x436338 STR	D3, [X13, X15,LSL #3]

  (1170) 0x43633c CMP	X2, X3

  (1170) 0x436340 B.EQ	4363bc

  (1170) 0x436344 LDUR	X18, [X29, #480]

  (1170) 0x436348 UBFM	X15, X24, #61, #60

  (1170) 0x43634c SUB	X2, X2, X24

  (1170) 0x436350 ADD	X3, X18, X15

  (1170) 0x436354 LDUR	X18, [X29, #472]

  (1170) 0x436358 ADD	X4, X18, X15

  (1170) 0x43635c HINT	#0

    (1172) 0x436360 LDUR	X15, [X4, #504]

    (1172) 0x436364 LDR	D0, [X23, X7,LSL #3]

    (1172) 0x436368 LDUR	D3, [X3, #504]

    (1172) 0x43636c SUBS	X2, X2, #2

    (1172) 0x436370 FMUL	D0, D0, D3

    (1172) 0x436374 LDR	X15, [X21, X15,LSL #3]

    (1172) 0x436378 LDR	D3, [X13, X15,LSL #3]

    (1172) 0x43637c FADD	D2, D2, D0

    (1172) 0x436380 FADD	D1, D1, D0

    (1172) 0x436384 FADD	D3, D0, D3

    (1172) 0x436388 STR	D3, [X13, X15,LSL #3]

    (1172) 0x43638c LDR	X15, [X4], #16

    (1172) 0x436390 LDR	D0, [X23, X7,LSL #3]

    (1172) 0x436394 LDR	D3, [X3], #16

    (1172) 0x436398 FMUL	D0, D0, D3

    (1172) 0x43639c LDR	X15, [X21, X15,LSL #3]

    (1172) 0x4363a0 LDR	D3, [X13, X15,LSL #3]

    (1172) 0x4363a4 FADD	D2, D2, D0

    (1172) 0x4363a8 FADD	D1, D1, D0

    (1172) 0x4363ac FADD	D3, D0, D3

    (1172) 0x4363b0 STR	D3, [X13, X15,LSL #3]

    (1172) 0x4363b4 B.NE	436360

  (1170) 0x4363b8 LDUR	X4, [X29, #456]

  (1170) 0x4363bc LDR	X3, [X17, X0,LSL #3]

  (1170) 0x4363c0 LDR	X0, [X17, X1,LSL #3]

  (1170) 0x4363c4 CMP	X0, X3

  (1170) 0x4363c8 B.LE	4362a0

  (1170) 0x4363cc SUB	W15, W0, W3

  (1170) 0x4363d0 ADD	X1, X3, #1

  (1170) 0x4363d4 TBNZ	W15, #0, 4363e4

  (1170) 0x4363d8 CMP	X0, X1

  (1170) 0x4363dc B.EQ	4362a0

  (1170) 0x4363e0 B	436418

  (1170) 0x4363e4 LDR	X15, [X14, X3,LSL #3]

  (1170) 0x4363e8 LDR	D0, [X23, X7,LSL #3]

  (1170) 0x4363ec LDR	D3, [X27, X3,LSL #3]

  (1170) 0x4363f0 ORR	X3, XZR, X1

  (1170) 0x4363f4 FMUL	D0, D0, D3

  (1170) 0x4363f8 LDR	X15, [X22, X15,LSL #3]

  (1170) 0x4363fc LDR	D3, [X27, X15,LSL #3]

  (1170) 0x436400 FADD	D2, D2, D0

  (1170) 0x436404 FADD	D1, D1, D0

  (1170) 0x436408 FADD	D3, D0, D3

  (1170) 0x43640c STR	D3, [X27, X15,LSL #3]

  (1170) 0x436410 CMP	X0, X1

  (1170) 0x436414 B.EQ	4362a0

  (1170) 0x436418 LDUR	X18, [X29, #448]

  (1170) 0x43641c UBFM	X15, X3, #61, #60

  (1170) 0x436420 SUB	X0, X0, X3

  (1170) 0x436424 ADD	X1, X18, X15

  (1170) 0x436428 LDUR	X18, [X29, #440]

  (1170) 0x43642c ADD	X2, X18, X15

  (1170) 0x436430 HINT	#0

  (1170) 0x436434 HINT	#0

  (1170) 0x436438 HINT	#0

  (1170) 0x43643c HINT	#0

    (1171) 0x436440 LDUR	X15, [X2, #504]

    (1171) 0x436444 LDR	D0, [X23, X7,LSL #3]

    (1171) 0x436448 LDUR	D3, [X1, #504]

    (1171) 0x43644c SUBS	X0, X0, #2

    (1171) 0x436450 FMUL	D0, D0, D3

    (1171) 0x436454 LDR	X15, [X22, X15,LSL #3]

    (1171) 0x436458 LDR	D3, [X27, X15,LSL #3]

    (1171) 0x43645c FADD	D2, D2, D0

    (1171) 0x436460 FADD	D1, D1, D0

    (1171) 0x436464 FADD	D3, D0, D3

    (1171) 0x436468 STR	D3, [X27, X15,LSL #3]

    (1171) 0x43646c LDR	X15, [X2], #16

    (1171) 0x436470 LDR	D0, [X23, X7,LSL #3]

    (1171) 0x436474 LDR	D3, [X1], #16

    (1171) 0x436478 FMUL	D0, D0, D3

    (1171) 0x43647c LDR	X15, [X22, X15,LSL #3]

    (1171) 0x436480 LDR	D3, [X27, X15,LSL #3]

    (1171) 0x436484 FADD	D2, D2, D0

    (1171) 0x436488 FADD	D1, D1, D0

    (1171) 0x43648c FADD	D3, D0, D3

    (1171) 0x436490 STR	D3, [X27, X15,LSL #3]

    (1171) 0x436494 B.NE	436440

  (1170) 0x436498 B	4362a0

0x4364a0 MOVI	D1, #0

0x4364a4 LDUR	X13, [X29, #360]

0x4364a8 LDR	X9, [X13, X11,LSL #3]

0x4364ac LDR	X13, [X13, X12,LSL #3]

0x4364b0 CMP	X9, X13

0x4364b4 B.LT	4364e8

0x4364b8 B	436678

0x4364c0 LDP	X3, X2, [X29, #848]

0x4364c4 LDP	X6, X5, [X29, #832]

0x4364c8 LDP	X24, X23, [SP, #192]

0x4364cc LDP	X26, X25, [SP, #176]

0x4364d0 LDUR	X27, [X29, #432]

0x4364d4 LDUR	X13, [X29, #360]

0x4364d8 LDR	X9, [X13, X11,LSL #3]

0x4364dc LDR	X13, [X13, X12,LSL #3]

0x4364e0 CMP	X9, X13

0x4364e4 B.GE	436678

0x436678 LDUR	X13, [X29, #424]

0x43667c LDUR	X9, [X29, #352]

0x436680 LDR	D3, [X9, X13,LSL #3]

0x436684 FMUL	D2, D2, D3

0x436688 FCMP	D2, #0

0x43668c B.EQ	436698

0x436690 FNEG	D0, D1

0x436694 FDIV	D0, D0, D2

0x436698 LDR	X13, [X4, X11,LSL #3]

0x43669c LDR	X9, [X4, X12,LSL #3]

0x4366a0 CMP	X9, X13

0x4366a4 B.LE	436734

0x4366a8 SUB	W15, W9, W13

0x4366ac ANDS	X16, X15, #4160

0x4366b0 B.EQ	4366ec

0x4366b4 ORR	X15, XZR, X13

0x4366b8 HINT	#0

0x4366bc HINT	#0

  (1180) 0x4366c0 LDR	D1, [X8, X15,LSL #3]

  (1180) 0x4366c4 SUBS	X16, X16, #1

  (1180) 0x4366c8 FMUL	D1, D0, D1

  (1180) 0x4366cc STR	D1, [X8, X15,LSL #3]

  (1180) 0x4366d0 ADD	X15, X15, #1

  (1180) 0x4366d4 B.NE	4366c0

0x4366d8 ORN	X13, XZR, X13

0x4366dc ADD	X13, X9, X13

0x4366e0 CMP	X13, #3

0x4366e4 B.CS	436700

0x4366e8 B	436734

0x4366ec ORR	X15, XZR, X13

0x4366f0 ORN	X13, XZR, X13

0x4366f4 ADD	X13, X9, X13

0x4366f8 CMP	X13, #3

0x4366fc B.CC	436734

0x436700 LDR	X13, [SP, #8]

0x436704 SUB	X9, X9, X15

0x436708 ADD	X13, X13, X15,LSL #3

  (1179) 0x43670c LDP	D1, D2, [X13, #1008]

  (1179) 0x436710 SUBS	X9, X9, #4

  (1179) 0x436714 FMUL	D2, D0, D2

  (1179) 0x436718 FMUL	D1, D0, D1

  (1179) 0x43671c STP	D1, D2, [X13, #1008]

  (1179) 0x436720 LDP	D1, D2, [X13]

  (1179) 0x436724 FMUL	D2, D0, D2

  (1179) 0x436728 FMUL	D1, D0, D1

  (1179) 0x43672c STP	D1, D2, [X13], #32

  (1179) 0x436730 B.NE	43670c

0x436734 LDUR	X9, [X29, #464]

0x436738 LDR	X11, [X9, X11,LSL #3]

0x43673c LDR	X9, [X9, X12,LSL #3]

0x436740 CMP	X9, X11

0x436744 B.LE	435fc8

0x436748 SUB	W12, W9, W11

0x43674c ANDS	X13, X12, #4160

0x436750 B.EQ	43678c

0x436754 ORR	X12, XZR, X11

0x436758 HINT	#0

0x43675c HINT	#0

  (1178) 0x436760 LDR	D1, [X10, X12,LSL #3]

  (1178) 0x436764 SUBS	X13, X13, #1

  (1178) 0x436768 FMUL	D1, D0, D1

  (1178) 0x43676c STR	D1, [X10, X12,LSL #3]

  (1178) 0x436770 ADD	X12, X12, #1

  (1178) 0x436774 B.NE	436760

0x436778 ORN	X11, XZR, X11

0x43677c ADD	X11, X9, X11

0x436780 CMP	X11, #3

0x436784 B.CC	435fc8

0x436788 B	4367a0

0x43678c ORR	X12, XZR, X11

0x436790 ORN	X11, XZR, X11

0x436794 ADD	X11, X9, X11

0x436798 CMP	X11, #3

0x43679c B.CC	435fc8

0x4367a0 LDR	X11, [SP]

0x4367a4 SUB	X9, X9, X12

0x4367a8 ADD	X11, X11, X12,LSL #3

  (1177) 0x4367ac LDP	D1, D2, [X11, #1008]

  (1177) 0x4367b0 SUBS	X9, X9, #4

  (1177) 0x4367b4 FMUL	D2, D0, D2

  (1177) 0x4367b8 FMUL	D1, D0, D1

  (1177) 0x4367bc STP	D1, D2, [X11, #1008]

  (1177) 0x4367c0 LDP	D1, D2, [X11]

  (1177) 0x4367c4 FMUL	D2, D0, D2

  (1177) 0x4367c8 FMUL	D1, D0, D1

  (1177) 0x4367cc STP	D1, D2, [X11], #32

  (1177) 0x4367d0 B.NE	4367ac

0x4367d4 B	435fc8

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1774 - 1876

--------------------------------------------------------------------------------

1774:              for (i=thread_start; i < thread_stop; i++)

1775:              {

1776:                 i1 = pass_array[i];

1777:                 sum_C = 0;

1778:                 sum_N = 0;

1779:                 j_start = P_diag_start[i1];

1780:                 j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1781:                 cnt = P_diag_i[i1];

1782:                 for (j=j_start; j < j_end; j++)

1783:                 {

1784:                    k1 = P_diag_pass[pass][j];

1785:                tmp_array[k1] = cnt;

1786:                P_diag_data[cnt] = 0;

1787:                P_diag_j[cnt++] = k1;

1788:                 }

1789:                 j_start = P_offd_start[i1];

1790:                 j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1791:                 cnt_offd = P_offd_i[i1];

1792:                 for (j=j_start; j < j_end; j++)

1793:                 {

1794:                    k1 = P_offd_pass[pass][j];

1795:                tmp_array_offd[k1] = cnt_offd;

1796:                P_offd_data[cnt_offd] = 0;

1797:                P_offd_j[cnt_offd++] = k1;

1798:                 }

1799:                 for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1800:                 {

1801:                j1 = S_diag_j[j];

1802:                if (assigned[j1] == pass-1)

1803:                   tmp_marker[j1] = i1;

1804:                 }

1805:                 for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

1806:                 {

1807:                j1 = S_offd_j[j];

1808:                if (assigned_offd[j1] == pass-1)

1809:                   tmp_marker_offd[j1] = i1;

1810:                 }

1811:                 for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1812:                 {

1813:                j1 = A_diag_j[j];

1814:                if (tmp_marker[j1] == i1)

1815:                {

1816:                   for (k=P_diag_i[j1]; k < P_diag_i[j1+1]; k++)

1817:                   {

1818:                  k1 = P_diag_j[k];

1819:                      alfa = A_diag_data[j]*P_diag_data[k];

1820:                      P_diag_data[tmp_array[k1]] += alfa;

1821:                      sum_C += alfa;

1822:                      sum_N += alfa;

1823:                       }

1824:                   for (k=P_offd_i[j1]; k < P_offd_i[j1+1]; k++)

1825:                   {

1826:                  k1 = P_offd_j[k];

1827:                      alfa = A_diag_data[j]*P_offd_data[k];

1828:                      P_offd_data[tmp_array_offd[k1]] += alfa;

1829:                      sum_C += alfa;

1830:                      sum_N += alfa;

1831:                       }

1832:                    }

1833:                    else

1834:                    {

1835:                       if (CF_marker[j1] != -3 &&

1836:                 (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1837:                  sum_N += A_diag_data[j];

1838:                    }

1839:                 }

1840:                 for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

[...]

1865:                       if (CF_marker_offd[j1] != -3 &&

1866:                 (num_functions == 1 || dof_func_offd[j1] == dof_func[i1]))

1867:                  sum_N += A_offd_data[j];

1868:                    }

1869:                 }

1870:                 diagonal = A_diag_data[A_diag_i[i1]];

1871:                 if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1872:

1873:                 for (j=P_diag_i[i1]; j < P_diag_i[i1+1]; j++)

1874:                P_diag_data[j] *= alfa;

1875:                 for (j=P_offd_i[i1]; j < P_offd_i[i1+1]; j++)

1876:                P_offd_data[j] *= alfa;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	12.92
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.01
Bottlenecks	P10,
Function	.omp_outlined..22#0x435ca0
Source	par_multi_interp.c:1774-1776,par_multi_interp.c:1779-1799,par_multi_interp.c:1805-1805,par_multi_interp.c:1811-1811,par_multi_interp.c:1824-1824,par_multi_interp.c:1840-1840,par_multi_interp.c:1865-1865,par_multi_interp.c:1870-1875
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	25.83
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	25.83
CQA cycles if fully vectorized	6.46
Front-end cycles	21.38
DIV/SQRT cycles	13.00
P0 cycles	13.00
P1 cycles	15.00
P2 cycles	15.00
P3 cycles	15.00
P4 cycles	15.00
P5 cycles	2.00
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	25.83
P10 cycles	25.50
P11 cycles	25.67
P12 cycles	4.50
P13 cycles	4.50
P14 cycles	1.75 - 3.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	180.00
Nb uops	171.00
Nb loads	NA
Nb stores	9.00
Nb stack references	0.00
FLOP/cycle	0.08
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	26.63
Bytes prefetched	0.00
Bytes loaded	592.00
Bytes stored	96.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	12.92
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.01
Bottlenecks	P10,
Function	.omp_outlined..22#0x435ca0
Source	par_multi_interp.c:1774-1776,par_multi_interp.c:1779-1799,par_multi_interp.c:1805-1805,par_multi_interp.c:1811-1811,par_multi_interp.c:1824-1824,par_multi_interp.c:1840-1840,par_multi_interp.c:1865-1865,par_multi_interp.c:1870-1875
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	25.83
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	25.83
CQA cycles if fully vectorized	6.46
Front-end cycles	21.38
DIV/SQRT cycles	13.00
P0 cycles	13.00
P1 cycles	15.00
P2 cycles	15.00
P3 cycles	15.00
P4 cycles	15.00
P5 cycles	2.00
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	25.83
P10 cycles	25.50
P11 cycles	25.67
P12 cycles	4.50
P13 cycles	4.50
P14 cycles	1.75 - 3.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	180.00
Nb uops	171.00
Nb loads	NA
Nb stores	9.00
Nb stack references	0.00
FLOP/cycle	0.08
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	26.63
Bytes prefetched	0.00
Bytes loaded	592.00
Bytes stored	96.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..22#0x435ca0
Source file and lines	par_multi_interp.c:1774-1876
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1774-1840,1865-1876.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1774-1776,1779-1799,1805,1811,1824,1840,1865,1870-1875.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.83 to 2.00 cycles (12.92x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 25.83 to 6.46 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 2 FP arithmetical operations:

1: multiply
1: divide

The binary loop is loading 592 bytes. The binary loop is storing 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	180
loop length	720
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

21.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	13.00	13.00	15.00	15.00	15.00	15.00	2.00	2.00	2.00	2.00	25.83	25.50	25.67	4.50	4.50
cycles	13.00	13.00	15.00	15.00	15.00	15.00	2.00	2.00	2.00	2.00	25.83	25.50	25.67	4.50	4.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.75-3.50

Cycles summary

Front-end	21.38
Overall L1	25.83

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 25.83 cycles. At this rate:

23% of peak load performance is reached (22.92 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (3.72 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 436678

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDUR X9, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X27, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X27, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4367d8 <.omp_outlined..22+0xb38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X9, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X9, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X4, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X4, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X0, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X13, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4360ac <.omp_outlined..22+0x40c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W18, W0, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
TBZ W18, #0, 436034 <.omp_outlined..22+0x394>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X8, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X2, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X18, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X16, [X21, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X18, [X14, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X16, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X0, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4360ac <.omp_outlined..22+0x40c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X15, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
LDUR X9, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X14, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X14, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X14, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X0, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X13, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 43616c <.omp_outlined..22+0x4cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W18, W0, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
TBZ W18, #0, 436100 <.omp_outlined..22+0x460>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X10, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X3, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X18, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X16, [X22, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X18, [X14, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X16, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X0, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 43616c <.omp_outlined..22+0x4cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X15, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
LDR X9, [X5, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X5, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 436184 <.omp_outlined..22+0x4e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X24, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4361d0 <.omp_outlined..22+0x530>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVI D2, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR X13, [X9, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X7, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X13, X27, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X7, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4364a0 <.omp_outlined..22+0x800>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X13, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVI D2, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR X6, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X13, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X15, X13, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X23, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X13, X15, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X27, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X25, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X14, X15, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X14, X27, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X15, X14, [X29, #952]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X14, XZR, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X17, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4362ac <.omp_outlined..22+0x60c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDUR X13, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X13, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X13, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4364e8 <.omp_outlined..22+0x848>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 436678 <.omp_outlined..22+0x9d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X3, X2, [X29, #848]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X6, X5, [X29, #832]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDUR X27, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X13, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X13, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X13, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 436678 <.omp_outlined..22+0x9d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X13, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D3, [X9, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D2, D2, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FCMP D2, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.EQ 436698 <.omp_outlined..22+0x9f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FNEG D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FDIV D0, D0, D2	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50
LDR X13, [X4, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X4, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 436734 <.omp_outlined..22+0xa94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W15, W9, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X16, X15, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4366ec <.omp_outlined..22+0xa4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X15, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
ORN X13, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X9, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X13, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 436700 <.omp_outlined..22+0xa60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 436734 <.omp_outlined..22+0xa94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X15, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN X13, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X9, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X13, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 436734 <.omp_outlined..22+0xa94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X9, X9, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X13, X15,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X9, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 435fc8 <.omp_outlined..22+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W12, W9, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X13, X12, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 43678c <.omp_outlined..22+0xaec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X12, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
ORN X11, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 435fc8 <.omp_outlined..22+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 4367a0 <.omp_outlined..22+0xb00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X12, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN X11, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 435fc8 <.omp_outlined..22+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X9, X9, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X11, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 435fc8 <.omp_outlined..22+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..22#0x435ca0
Source file and lines	par_multi_interp.c:1774-1876
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 2 FP arithmetical operations:

1: multiply
1: divide

The binary loop is loading 592 bytes. The binary loop is storing 96 bytes.

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	180
loop length	720
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

21.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	13.00	13.00	15.00	15.00	15.00	15.00	2.00	2.00	2.00	2.00	25.83	25.50	25.67	4.50	4.50
cycles	13.00	13.00	15.00	15.00	15.00	15.00	2.00	2.00	2.00	2.00	25.83	25.50	25.67	4.50	4.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.75-3.50

Cycles summary

Front-end	21.38
Overall L1	25.83

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 25.83 cycles. At this rate:

23% of peak load performance is reached (22.92 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (3.72 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 436678

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDUR X9, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X27, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X27, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4367d8 <.omp_outlined..22+0xb38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X9, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X9, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X4, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X4, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X0, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X13, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4360ac <.omp_outlined..22+0x40c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W18, W0, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
TBZ W18, #0, 436034 <.omp_outlined..22+0x394>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X8, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X2, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X18, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X16, [X21, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X18, [X14, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X16, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X0, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4360ac <.omp_outlined..22+0x40c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X15, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
LDUR X9, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X14, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X14, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X14, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X0, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X13, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 43616c <.omp_outlined..22+0x4cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W18, W0, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
TBZ W18, #0, 436100 <.omp_outlined..22+0x460>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X10, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X3, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X18, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X16, [X22, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X18, [X14, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X16, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X0, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 43616c <.omp_outlined..22+0x4cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X15, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
LDR X9, [X5, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X5, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 436184 <.omp_outlined..22+0x4e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X24, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4361d0 <.omp_outlined..22+0x530>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVI D2, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR X13, [X9, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X7, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X13, X27, [X29, #936]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X7, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4364a0 <.omp_outlined..22+0x800>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X13, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVI D2, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR X6, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X13, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X15, X13, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X23, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X13, X15, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X27, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X25, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X14, X15, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X14, X27, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X15, X14, [X29, #952]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X14, XZR, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X17, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4362ac <.omp_outlined..22+0x60c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDUR X13, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X13, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X13, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4364e8 <.omp_outlined..22+0x848>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 436678 <.omp_outlined..22+0x9d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X3, X2, [X29, #848]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X6, X5, [X29, #832]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDUR X27, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X13, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X13, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X13, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 436678 <.omp_outlined..22+0x9d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X13, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D3, [X9, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D2, D2, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FCMP D2, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.EQ 436698 <.omp_outlined..22+0x9f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FNEG D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FDIV D0, D0, D2	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50
LDR X13, [X4, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X4, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 436734 <.omp_outlined..22+0xa94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W15, W9, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X16, X15, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4366ec <.omp_outlined..22+0xa4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X15, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
ORN X13, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X9, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X13, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 436700 <.omp_outlined..22+0xa60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 436734 <.omp_outlined..22+0xa94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X15, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN X13, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X9, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X13, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 436734 <.omp_outlined..22+0xa94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X13, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X9, X9, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X13, X15,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X9, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 435fc8 <.omp_outlined..22+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB W12, W9, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ANDS X13, X12, #4160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 43678c <.omp_outlined..22+0xaec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X12, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
ORN X11, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 435fc8 <.omp_outlined..22+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 4367a0 <.omp_outlined..22+0xb00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X12, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORN X11, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 435fc8 <.omp_outlined..22+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X9, X9, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X11, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 435fc8 <.omp_outlined..22+0x328>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code