OV - exec - Loop 1071

0x466384 LDR	X7, [X9, X0,LSL #3]

0x466388 ADD	X2, X2, #1

0x46638c CMP	X2, X7

0x466390 B.GE	4664e0

0x466394 LDR	X19, [X10, X2,LSL #3]

0x466398 LDR	X7, [X11, X19,LSL #3]

0x46639c CMP	X7, #1

0x4663a0 B.LT	4663d0

0x4663a4 LDR	X7, [X3, X19,LSL #3]

0x4663a8 LDR	X20, [X24, X7,LSL #3]

0x4663ac CMP	X20, X17

0x4663b0 B.GE	4663d0

0x4663b4 LDUR	X20, [X29, #480]

0x4663b8 STR	X20, [X24, X7,LSL #3]

0x4663bc LDUR	X20, [X29, #480]

0x4663c0 STR	X7, [X4, X20,LSL #3]

0x4663c4 LDUR	X7, [X29, #480]

0x4663c8 ADD	X7, X7, #1

0x4663cc STUR	X7, [X29, #480]

0x4663d0 ADD	X7, X19, #1

0x4663d4 LDR	X20, [X9, X19,LSL #3]

0x4663d8 LDR	X23, [X9, X7,LSL #3]

0x4663dc CMP	X20, X23

0x4663e0 B.GE	466464

0x4663e4 LDP	X26, X21, [X29, #960]

0x4663e8 LDR	X21, [X21]

0x4663ec LDR	X26, [X26]

0x4663f0 B	46640c

  (1073) 0x466400 ADD	X20, X20, #1

  (1073) 0x466404 CMP	X20, X23

  (1073) 0x466408 B.GE	466460

  (1073) 0x46640c LDR	X27, [X10, X20,LSL #3]

  (1073) 0x466410 LDR	X28, [X11, X27,LSL #3]

  (1073) 0x466414 CMP	X28, #1

  (1073) 0x466418 B.LT	466400

  (1073) 0x46641c LDR	X27, [X21, X27,LSL #3]

  (1073) 0x466420 CMP	X27, X22

  (1073) 0x466424 B.EQ	466400

  (1073) 0x466428 LDR	X28, [X24, X27,LSL #3]

  (1073) 0x46642c CMP	X28, X17

  (1073) 0x466430 B.GE	466400

  (1073) 0x466434 LDUR	X23, [X29, #480]

  (1073) 0x466438 STR	X23, [X24, X27,LSL #3]

  (1073) 0x46643c LDUR	X23, [X29, #480]

  (1073) 0x466440 STR	X27, [X26, X23,LSL #3]

  (1073) 0x466444 LDUR	X23, [X29, #480]

  (1073) 0x466448 ADD	X23, X23, #1

  (1073) 0x46644c STUR	X23, [X29, #480]

  (1073) 0x466450 LDR	X23, [X9, X7,LSL #3]

  (1073) 0x466454 B	466400

0x466460 LDUR	X28, [X29, #432]

0x466464 LDR	X19, [X12, X19,LSL #3]

0x466468 LDR	X23, [X12, X7,LSL #3]

0x46646c CMP	X19, X23

0x466470 B.GE	466384

0x466474 LDUR	X20, [X29, #464]

0x466478 LDR	X21, [X28]

0x46647c LDR	X20, [X20]

0x466480 B	466490

  (1072) 0x466484 ADD	X19, X19, #1

  (1072) 0x466488 CMP	X19, X23

  (1072) 0x46648c B.GE	466384

  (1072) 0x466490 LDR	X26, [X5, X19,LSL #3]

  (1072) 0x466494 LDR	X27, [X6, X26,LSL #3]

  (1072) 0x466498 CMP	X27, #1

  (1072) 0x46649c B.LT	466484

  (1072) 0x4664a0 LDR	X26, [X20, X26,LSL #3]

  (1072) 0x4664a4 LDR	X27, [X25, X26,LSL #3]

  (1072) 0x4664a8 CMP	X27, X18

  (1072) 0x4664ac B.GE	466484

  (1072) 0x4664b0 LDUR	X23, [X29, #472]

  (1072) 0x4664b4 STR	X23, [X25, X26,LSL #3]

  (1072) 0x4664b8 LDUR	X23, [X29, #472]

  (1072) 0x4664bc STR	X26, [X21, X23,LSL #3]

  (1072) 0x4664c0 LDUR	X23, [X29, #472]

  (1072) 0x4664c4 ADD	X23, X23, #1

  (1072) 0x4664c8 STUR	X23, [X29, #472]

  (1072) 0x4664cc LDR	X23, [X12, X7,LSL #3]

  (1072) 0x4664d0 B	466484

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 2011 - 2048

--------------------------------------------------------------------------------

2011:              for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++)

2012:              {

2013:                  i2 = S_diag_j[jj1];

2014:                  if (CF_marker[i2] > 0)

2015:                  {

2016:                     index = fine_to_coarse[i2];

2017:                     if (S_marker[index] < jj_row_begin_diag)

2018:                     {

2019:                        S_marker[index] = num_nonzeros_diag;

2020:                        C_diag_j[num_nonzeros_diag] = index;

2021:                        num_nonzeros_diag++;

2022:                     }

2023:                  }

2024:                  for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++)

2025:                  {

2026:                     i3 = S_diag_j[jj2];

2027:                     if (CF_marker[i3] > 0)

2028:                     {

2029:                        index = fine_to_coarse[i3];

2030:                        if (index != ic && S_marker[index] < jj_row_begin_diag)

2031:                        {

2032:                           S_marker[index] = num_nonzeros_diag;

2033:                           C_diag_j[num_nonzeros_diag] = index;

2034:                           num_nonzeros_diag++;

2035:                        }

2036:                     }

2037:                  }

2038:                  for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++)

2039:                  {

2040:                     i3 = S_offd_j[jj2];

2041:                     if (CF_marker_offd[i3] > 0)

2042:                     {

2043:                        index = map_S_to_C[i3];

2044:                        if (S_marker_offd[index] < jj_row_begin_offd)

2045:                        {

2046:                           S_marker_offd[index] = num_nonzeros_offd;

2047:                           C_offd_j[num_nonzeros_offd] = index;

2048:                           num_nonzeros_offd++;

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P10,
Function	.omp_outlined..20#0x465590
Source	par_strength.c:2011-2021,par_strength.c:2024-2024,par_strength.c:2038-2038
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.50
CQA cycles if no scalar integer	7.50
CQA cycles if FP arith vectorized	7.50
CQA cycles if fully vectorized	1.88
Front-end cycles	4.63
DIV/SQRT cycles	3.50
P0 cycles	3.50
P1 cycles	2.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	7.50
P10 cycles	7.17
P11 cycles	7.33
P12 cycles	1.50
P13 cycles	1.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	37.00
Nb uops	37.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.53
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P10,
Function	.omp_outlined..20#0x465590
Source	par_strength.c:2011-2021,par_strength.c:2024-2024,par_strength.c:2038-2038
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.50
CQA cycles if no scalar integer	7.50
CQA cycles if FP arith vectorized	7.50
CQA cycles if fully vectorized	1.88
Front-end cycles	4.63
DIV/SQRT cycles	3.50
P0 cycles	3.50
P1 cycles	2.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	7.50
P10 cycles	7.17
P11 cycles	7.33
P12 cycles	1.50
P13 cycles	1.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	37.00
Nb uops	37.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.53
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	.omp_outlined..20#0x465590
Source file and lines	par_strength.c:2011-2048
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:2011-2048.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:2011-2021,2024,2038.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 7.50 to 1.87 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 160 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	37
loop length	148
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	7.50	7.17	7.33	1.50	1.50
cycles	3.50	3.50	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	7.50	7.17	7.33	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	4.63
Overall L1	7.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.50 cycles. At this rate:

22% of peak load performance is reached (21.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 466394

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X7, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X2, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4664e0 <.omp_outlined..20+0xf50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X19, [X10, X2,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X11, X19,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 4663d0 <.omp_outlined..20+0xe40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X7, [X3, X19,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X20, [X24, X7,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X20, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4663d0 <.omp_outlined..20+0xe40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X20, [X29, #480]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X20, [X24, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X20, [X29, #480]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X7, [X4, X20,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X7, [X29, #480]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X7, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STUR X7, [X29, #480]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X7, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X20, [X9, X19,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X9, X7,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X20, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 466464 <.omp_outlined..20+0xed4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X26, X21, [X29, #960]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X21, [X21]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [X26]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 46640c <.omp_outlined..20+0xe7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X28, [X29, #432]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X19, [X12, X19,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X12, X7,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X19, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 466384 <.omp_outlined..20+0xdf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X20, [X29, #464]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X28]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X20, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 466490 <.omp_outlined..20+0xf00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	.omp_outlined..20#0x465590
Source file and lines	par_strength.c:2011-2048
Module	exec

The loop is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:2011-2048.

Analyzed code is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:2011-2021,2024,2038.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 7.50 to 1.87 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 160 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	37
loop length	148
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	7.50	7.17	7.33	1.50	1.50
cycles	3.50	3.50	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	7.50	7.17	7.33	1.50	1.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	4.63
Overall L1	7.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.50 cycles. At this rate:

22% of peak load performance is reached (21.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 466394

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X7, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP X2, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4664e0 <.omp_outlined..20+0xf50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X19, [X10, X2,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X11, X19,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 4663d0 <.omp_outlined..20+0xe40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X7, [X3, X19,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X20, [X24, X7,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X20, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 4663d0 <.omp_outlined..20+0xe40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X20, [X29, #480]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X20, [X24, X7,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X20, [X29, #480]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X7, [X4, X20,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X7, [X29, #480]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X7, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STUR X7, [X29, #480]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X7, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X20, [X9, X19,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X9, X7,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X20, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 466464 <.omp_outlined..20+0xed4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDP X26, X21, [X29, #960]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X21, [X21]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [X26]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 46640c <.omp_outlined..20+0xe7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X28, [X29, #432]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X19, [X12, X19,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X12, X7,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X19, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GE 466384 <.omp_outlined..20+0xdf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X20, [X29, #464]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X28]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X20, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 466490 <.omp_outlined..20+0xf00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code