| Function: hypre_BoomerAMGBuildMultipass | Module: exec | Source: par_multi_interp.c:41-2060 [...] | Coverage: 0.27% |
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| Function: hypre_BoomerAMGBuildMultipass | Module: exec | Source: par_multi_interp.c:41-2060 [...] | Coverage: 0.27% |
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/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 41 - 2060 |
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41: { |
42: #ifdef HYPRE_PROFILE |
43: hypre_profile_times[HYPRE_TIMER_ID_MULTIPASS_INTERP] -= hypre_MPI_Wtime(); |
44: #endif |
45: |
46: MPI_Comm comm = hypre_ParCSRMatrixComm(A); |
47: hypre_ParCSRCommPkg *comm_pkg = hypre_ParCSRMatrixCommPkg(S); |
48: hypre_ParCSRCommHandle *comm_handle; |
49: hypre_ParCSRCommPkg *tmp_comm_pkg; |
50: |
51: hypre_CSRMatrix *A_diag = hypre_ParCSRMatrixDiag(A); |
52: HYPRE_Real *A_diag_data = hypre_CSRMatrixData(A_diag); |
53: HYPRE_Int *A_diag_i = hypre_CSRMatrixI(A_diag); |
54: HYPRE_Int *A_diag_j = hypre_CSRMatrixJ(A_diag); |
55: |
56: hypre_CSRMatrix *A_offd = hypre_ParCSRMatrixOffd(A); |
57: HYPRE_Real *A_offd_data = NULL; |
58: HYPRE_Int *A_offd_i = hypre_CSRMatrixI(A_offd); |
59: HYPRE_Int *A_offd_j = NULL; |
60: HYPRE_Int *col_map_offd_A = hypre_ParCSRMatrixColMapOffd(A); |
61: HYPRE_Int num_cols_offd_A = hypre_CSRMatrixNumCols(A_offd); |
62: |
63: hypre_CSRMatrix *S_diag = hypre_ParCSRMatrixDiag(S); |
64: HYPRE_Int *S_diag_i = hypre_CSRMatrixI(S_diag); |
65: HYPRE_Int *S_diag_j = hypre_CSRMatrixJ(S_diag); |
66: |
67: hypre_CSRMatrix *S_offd = hypre_ParCSRMatrixOffd(S); |
68: HYPRE_Int *S_offd_i = hypre_CSRMatrixI(S_offd); |
69: HYPRE_Int *S_offd_j = NULL; |
70: HYPRE_Int *col_map_offd_S = hypre_ParCSRMatrixColMapOffd(S); |
71: HYPRE_Int num_cols_offd_S = hypre_CSRMatrixNumCols(S_offd); |
[...] |
83: HYPRE_Real *P_offd_data = NULL; |
84: HYPRE_Int *P_offd_i; /*at first counter of nonzero cols for each row, |
85: finally will be pointer to start of row */ |
86: HYPRE_Int *P_offd_j = NULL; |
[...] |
99: HYPRE_Int *Pext_start = NULL; |
100: HYPRE_Int *P_ncols = NULL; |
101: |
102: HYPRE_Int *CF_marker_offd = NULL; |
103: HYPRE_Int *dof_func_offd = NULL; |
104: HYPRE_Int *P_marker; |
105: HYPRE_Int *P_marker_offd = NULL; |
106: HYPRE_Int *C_array; |
107: HYPRE_Int *C_array_offd = NULL; |
108: HYPRE_Int *pass_array = NULL; /* contains points ordered according to pass */ |
109: HYPRE_Int *pass_pointer = NULL; /* pass_pointer[j] contains pointer to first |
110: point of pass j contained in pass_array */ |
111: HYPRE_Int *P_diag_start; |
112: HYPRE_Int *P_offd_start = NULL; |
113: HYPRE_Int **P_diag_pass; |
114: HYPRE_Int **P_offd_pass = NULL; |
115: HYPRE_Int **Pext_pass = NULL; |
116: HYPRE_Int **new_elmts = NULL; /* new neighbors generated in each pass */ |
117: HYPRE_Int *new_counter = NULL; /* contains no. of new neighbors for |
118: each pass */ |
119: HYPRE_Int *loc = NULL; /* contains locations for new neighbor |
120: connections in int_o_buffer to avoid searching */ |
121: HYPRE_Int *Pext_i = NULL; /*contains P_diag_i and P_offd_i info for nonzero |
122: cols of off proc neighbors */ |
123: HYPRE_Int *Pext_send_buffer = NULL; /* used to collect global nonzero |
124: col ids in P_diag for send_map_elmts */ |
125: |
126: HYPRE_Int *map_S_to_new = NULL; |
127: /*HYPRE_Int *map_A_to_new = NULL;*/ |
128: HYPRE_Int *map_A_to_S = NULL; |
129: HYPRE_Int *new_col_map_offd = NULL; |
130: HYPRE_Int *col_map_offd_P = NULL; |
131: HYPRE_Int *permute = NULL; |
[...] |
141: HYPRE_Int n_coarse = 0; |
142: HYPRE_Int n_coarse_offd = 0; |
143: HYPRE_Int n_SF = 0; |
144: HYPRE_Int n_SF_offd = 0; |
145: |
146: HYPRE_Int *fine_to_coarse = NULL; |
147: HYPRE_Int *fine_to_coarse_offd = NULL; |
148: |
149: HYPRE_Int *assigned = NULL; |
150: HYPRE_Int *assigned_offd = NULL; |
151: |
152: HYPRE_Real *Pext_send_data = NULL; |
153: HYPRE_Real *Pext_data = NULL; |
[...] |
184: HYPRE_Int P_offd_size = 0; |
185: HYPRE_Int local_index = -1; |
186: HYPRE_Int new_num_cols_offd = 0; |
[...] |
194: HYPRE_Int * max_num_threads = hypre_CTAlloc(HYPRE_Int, 1); |
[...] |
202: max_num_threads[0] = hypre_NumThreads(); |
203: cnt_nz_per_thread = hypre_CTAlloc(HYPRE_Int, max_num_threads[0]); |
204: cnt_nz_offd_per_thread = hypre_CTAlloc(HYPRE_Int, max_num_threads[0]); |
205: for(i=0; i < max_num_threads[0]; i++) |
206: { |
207: cnt_nz_offd_per_thread[i] = 0; |
208: cnt_nz_per_thread[i] = 0; |
[...] |
216: hypre_MPI_Comm_size(comm,&num_procs); |
217: hypre_MPI_Comm_rank(comm,&my_id); |
218: |
219: #ifdef HYPRE_NO_GLOBAL_PARTITION |
220: my_first_cpt = num_cpts_global[0]; |
221: /* total_global_cpts = 0; */ |
222: if (my_id == (num_procs -1)) total_global_cpts = num_cpts_global[1]; |
223: hypre_MPI_Bcast(&total_global_cpts, 1, HYPRE_MPI_INT, num_procs-1, comm); |
[...] |
229: if (!comm_pkg) |
230: { |
231: comm_pkg = hypre_ParCSRMatrixCommPkg(A); |
232: if (!comm_pkg) |
233: { |
234: hypre_MatvecCommPkgCreate(A); |
235: |
236: comm_pkg = hypre_ParCSRMatrixCommPkg(A); |
237: } |
238: col_offd_S_to_A = NULL; |
239: } |
240: |
241: if (col_offd_S_to_A) |
[...] |
252: if (num_cols_offd_A) |
253: { |
254: A_offd_data = hypre_CSRMatrixData(A_offd); |
255: A_offd_j = hypre_CSRMatrixJ(A_offd); |
256: } |
257: |
258: if (num_cols_offd) |
259: S_offd_j = hypre_CSRMatrixJ(S_offd); |
260: |
261: n_fine = hypre_CSRMatrixNumRows(A_diag); |
[...] |
267: if (n_fine) fine_to_coarse = hypre_CTAlloc(HYPRE_Int, n_fine); |
268: |
269: n_coarse = 0; |
270: n_SF = 0; |
271: #ifdef HYPRE_USING_OPENMP |
272: #pragma omp parallel for private(i) reduction(+:n_coarse,n_SF ) HYPRE_SMP_SCHEDULE |
[...] |
278: pass_array_size = n_fine-n_coarse-n_SF; |
279: if (pass_array_size) pass_array = hypre_CTAlloc(HYPRE_Int, pass_array_size); |
280: pass_pointer = hypre_CTAlloc(HYPRE_Int, max_num_passes+1); |
281: if (n_fine) assigned = hypre_CTAlloc(HYPRE_Int, n_fine); |
282: P_diag_i = hypre_CTAlloc(HYPRE_Int, n_fine+1); |
283: P_offd_i = hypre_CTAlloc(HYPRE_Int, n_fine+1); |
284: if (n_coarse) C_array = hypre_CTAlloc(HYPRE_Int, n_coarse); |
285: |
286: if (num_cols_offd) |
287: { |
288: CF_marker_offd = hypre_CTAlloc(HYPRE_Int, num_cols_offd); |
289: if (num_functions > 1) dof_func_offd = hypre_CTAlloc(HYPRE_Int, num_cols_offd); |
290: } |
291: |
292: if (num_procs > 1) |
293: { |
294: num_sends = hypre_ParCSRCommPkgNumSends(comm_pkg); |
295: send_procs = hypre_ParCSRCommPkgSendProcs(comm_pkg); |
296: send_map_start = hypre_ParCSRCommPkgSendMapStarts(comm_pkg); |
297: send_map_elmt = hypre_ParCSRCommPkgSendMapElmts(comm_pkg); |
298: num_recvs = hypre_ParCSRCommPkgNumRecvs(comm_pkg); |
299: recv_procs = hypre_ParCSRCommPkgRecvProcs(comm_pkg); |
300: recv_vec_start = hypre_ParCSRCommPkgRecvVecStarts(comm_pkg); |
301: if (send_map_start[num_sends]) |
302: int_buf_data = hypre_CTAlloc(HYPRE_Int, send_map_start[num_sends]); |
303: } |
304: |
305: |
306: index = 0; |
307: for (i=0; i < num_sends; i++) |
308: { |
309: start = send_map_start[i]; |
310: for (j = start; j < send_map_start[i+1]; j++) |
311: int_buf_data[index++] = CF_marker[send_map_elmt[j]]; |
312: } |
313: if (num_procs > 1) |
314: { |
315: comm_handle = hypre_ParCSRCommHandleCreate(11, comm_pkg, int_buf_data, |
316: CF_marker_offd); |
317: hypre_ParCSRCommHandleDestroy(comm_handle); |
318: } |
319: |
320: if (num_functions > 1) |
321: { |
322: index = 0; |
323: for (i=0; i < num_sends; i++) |
324: { |
325: start = send_map_start[i]; |
326: for (j = start; j < send_map_start[i+1]; j++) |
327: int_buf_data[index++] = dof_func[send_map_elmt[j]]; |
328: } |
329: if (num_procs > 1) |
330: { |
331: comm_handle = hypre_ParCSRCommHandleCreate(11, comm_pkg, int_buf_data, |
332: dof_func_offd); |
333: hypre_ParCSRCommHandleDestroy(comm_handle); |
334: } |
335: } |
336: |
337: n_coarse_offd = 0; |
338: n_SF_offd = 0; |
339: #ifdef HYPRE_USING_OPENMP |
340: #pragma omp parallel for private(i) reduction(+:n_coarse_offd,n_SF_offd) HYPRE_SMP_SCHEDULE |
[...] |
346: if (num_cols_offd) |
347: { |
348: assigned_offd = hypre_CTAlloc(HYPRE_Int, num_cols_offd); |
349: map_S_to_new = hypre_CTAlloc(HYPRE_Int, num_cols_offd); |
350: fine_to_coarse_offd = hypre_CTAlloc(HYPRE_Int, num_cols_offd); |
351: new_col_map_offd = hypre_CTAlloc(HYPRE_Int, n_coarse_offd); |
[...] |
382: p_cnt = pass_array_size-1; |
383: P_diag_i[0] = 0; |
384: P_offd_i[0] = 0; |
385: for (i = 0; i < n_fine; i++) |
386: { |
387: if (CF_marker[i] == 1) |
388: { |
389: fine_to_coarse[i] = cnt; /* this C point is assigned index |
390: coarse_counter on coarse grid, |
391: and in column of P */ |
392: C_array[cnt++] = i; |
393: assigned[i] = 0; |
394: P_diag_i[i+1] = 1; /* one element in row i1 of P */ |
395: P_offd_i[i+1] = 0; |
396: } |
397: else if (CF_marker[i] == -1) |
398: { |
399: pass_array[p_cnt--] = i; |
400: P_diag_i[i+1] = 0; |
[...] |
415: for (i=0; i < num_sends; i++) |
416: { |
417: start = send_map_start[i]; |
418: for (j = start; j < send_map_start[i+1]; j++) |
419: { |
420: int_buf_data[index] = fine_to_coarse[send_map_elmt[j]]; |
421: if (int_buf_data[index] > -1) |
422: int_buf_data[index] += my_first_cpt; |
423: index++; |
424: } |
425: } |
426: if (num_procs > 1) |
427: { |
428: comm_handle = hypre_ParCSRCommHandleCreate(11, comm_pkg, int_buf_data, |
429: fine_to_coarse_offd); |
430: hypre_ParCSRCommHandleDestroy(comm_handle); |
431: } |
432: |
433: new_recv_vec_start = hypre_CTAlloc(HYPRE_Int,num_recvs+1); |
434: |
435: if (n_coarse_offd) |
436: C_array_offd = hypre_CTAlloc(HYPRE_Int,n_coarse_offd); |
437: |
438: cnt = 0; |
439: new_recv_vec_start[0] = 0; |
440: for (j = 0; j < num_recvs; j++) |
441: { |
442: for (i = recv_vec_start[j]; i < recv_vec_start[j+1]; i++) |
443: { |
444: if (CF_marker_offd[i] == 1) |
445: { |
446: map_S_to_new[i] = cnt; |
447: C_array_offd[cnt] = i; |
448: new_col_map_offd[cnt++] = fine_to_coarse_offd[i]; |
449: assigned_offd[i] = 0; |
450: } |
451: else |
452: { |
453: assigned_offd[i] = -1; |
454: map_S_to_new[i] = -1; |
455: } |
456: } |
457: new_recv_vec_start[j+1] = cnt; |
458: } |
459: |
460: cnt = 0; |
461: hypre_TFree(fine_to_coarse_offd); |
462: |
463: if (col_offd_S_to_A) |
464: { |
465: map_A_to_S = hypre_CTAlloc(HYPRE_Int,num_cols_offd_A); |
466: for (i=0; i < num_cols_offd_A; i++) |
467: { |
468: if (cnt < num_cols_offd && col_map_offd_A[i] == col_map_offd[cnt]) |
[...] |
479: pass_pointer[0] = 0; |
480: pass_pointer[1] = 0; |
481: total_nz = n_coarse; /* accumulates total number of nonzeros in P_diag */ |
482: total_nz_offd = 0; /* accumulates total number of nonzeros in P_offd */ |
[...] |
488: for (i = pass_array_size-1; i > cnt-1; i--) |
489: { |
490: i1 = pass_array[i]; |
491: for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++) |
492: { |
493: j1 = S_diag_j[j]; |
494: if (CF_marker[j1] == 1) |
495: { |
496: P_diag_i[i1+1]++; |
497: cnt_nz++; |
498: assigned[i1] = 1; |
499: } |
500: } |
501: for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++) |
502: { |
503: j1 = S_offd_j[j]; |
504: if (CF_marker_offd[j1] == 1) |
505: { |
506: P_offd_i[i1+1]++; |
507: cnt_nz_offd++; |
508: assigned[i1] = 1; |
509: } |
510: } |
511: if (assigned[i1] == 1) |
512: { |
513: pass_array[i++] = pass_array[cnt]; |
514: pass_array[cnt++] = i1; |
515: } |
516: } |
517: |
518: pass_pointer[2] = cnt; |
[...] |
526: for (i=0; i < num_sends; i++) |
527: { |
528: start = send_map_start[i]; |
529: for (j = start; j < send_map_start[i+1]; j++) |
530: { int_buf_data[index++] = assigned[send_map_elmt[j]]; } |
531: } |
532: if (num_procs > 1) |
533: { |
534: comm_handle = hypre_ParCSRCommHandleCreate(11, comm_pkg, int_buf_data, |
535: assigned_offd); |
536: hypre_ParCSRCommHandleDestroy(comm_handle); |
[...] |
544: pass = 2; |
545: local_pass_array_size = pass_array_size - cnt; |
546: hypre_MPI_Allreduce(&local_pass_array_size, &global_pass_array_size, 1, HYPRE_MPI_INT, |
547: hypre_MPI_SUM, comm); |
548: while (global_pass_array_size && pass < max_num_passes) |
549: { |
550: for (i = pass_array_size-1; i > cnt-1; i--) |
551: { |
552: i1 = pass_array[i]; |
553: no_break = 1; |
554: for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++) |
555: { |
556: j1 = S_diag_j[j]; |
557: if (assigned[j1] == pass-1) |
[...] |
568: for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++) |
569: { |
570: j1 = S_offd_j[j]; |
571: if (assigned_offd[j1] == pass-1) |
[...] |
583: pass++; |
584: pass_pointer[pass] = cnt; |
585: |
586: local_pass_array_size = pass_array_size - cnt; |
587: hypre_MPI_Allreduce(&local_pass_array_size, &global_pass_array_size, 1, HYPRE_MPI_INT, |
588: hypre_MPI_SUM, comm); |
589: index = 0; |
590: for (i=0; i < num_sends; i++) |
591: { |
592: start = send_map_start[i]; |
593: for (j = start; j < send_map_start[i+1]; j++) |
594: { int_buf_data[index++] = assigned[send_map_elmt[j]]; } |
595: } |
596: if (num_procs > 1) |
597: { |
598: comm_handle = hypre_ParCSRCommHandleCreate(11, comm_pkg, int_buf_data, |
599: assigned_offd); |
600: hypre_ParCSRCommHandleDestroy(comm_handle); |
601: } |
602: } |
603: |
604: hypre_TFree(int_buf_data); |
605: |
606: num_passes = pass; |
607: |
608: P_diag_pass = hypre_CTAlloc(HYPRE_Int*,num_passes); /* P_diag_pass[i] will contain |
609: all column numbers for points of pass i */ |
610: |
611: P_diag_pass[1] = hypre_CTAlloc(HYPRE_Int,cnt_nz); |
612: |
613: P_diag_start = hypre_CTAlloc(HYPRE_Int, n_fine); /* P_diag_start[i] contains |
614: pointer to begin of column numbers in P_pass for point i, |
615: P_diag_i[i+1] contains number of columns for point i */ |
616: |
617: P_offd_start = hypre_CTAlloc(HYPRE_Int, n_fine); |
618: |
619: if (num_procs > 1) |
620: { |
621: P_offd_pass = hypre_CTAlloc(HYPRE_Int*,num_passes); |
622: |
623: if (cnt_nz_offd) |
624: P_offd_pass[1] = hypre_CTAlloc(HYPRE_Int,cnt_nz_offd); |
625: else |
626: P_offd_pass[1] = NULL; |
627: |
628: new_elmts = hypre_CTAlloc(HYPRE_Int*,num_passes); |
629: |
630: new_counter = hypre_CTAlloc(HYPRE_Int, num_passes+1); |
631: |
632: new_counter[0] = 0; |
633: new_counter[1] = n_coarse_offd; |
634: new_num_cols_offd = n_coarse_offd; |
635: |
636: new_elmts[0] = new_col_map_offd; |
[...] |
646: for (i=pass_pointer[1]; i < pass_pointer[2]; i++) |
647: { |
648: i1 = pass_array[i]; |
649: P_diag_start[i1] = cnt_nz; |
650: P_offd_start[i1] = cnt_nz_offd; |
651: for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++) |
652: { |
653: j1 = S_diag_j[j]; |
654: if (CF_marker[j1] == 1) |
655: { P_diag_pass[1][cnt_nz++] = fine_to_coarse[j1]; } |
656: } |
657: for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++) |
658: { |
659: j1 = S_offd_j[j]; |
660: if (CF_marker_offd[j1] == 1) |
661: { P_offd_pass[1][cnt_nz_offd++] = map_S_to_new[j1]; } |
662: } |
663: } |
664: |
665: |
666: total_nz += cnt_nz; |
667: total_nz_offd += cnt_nz_offd; |
668: |
669: if (num_procs > 1) |
670: { |
671: tmp_comm_pkg = hypre_CTAlloc(hypre_ParCSRCommPkg,1); |
672: Pext_send_map_start = hypre_CTAlloc(HYPRE_Int*,num_passes); |
673: Pext_recv_vec_start = hypre_CTAlloc(HYPRE_Int*,num_passes); |
674: Pext_pass = hypre_CTAlloc(HYPRE_Int*,num_passes); |
675: Pext_i = hypre_CTAlloc(HYPRE_Int, num_cols_offd+1); |
676: if (num_cols_offd) Pext_start = hypre_CTAlloc(HYPRE_Int, num_cols_offd); |
677: if (send_map_start[num_sends]) |
678: P_ncols = hypre_CTAlloc(HYPRE_Int,send_map_start[num_sends]); |
679: #ifdef HYPRE_USING_OPENMP |
680: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE |
681: #endif |
682: for (i=0; i < num_cols_offd+1; i++) |
683: { Pext_i[i] = 0; } |
684: #ifdef HYPRE_USING_OPENMP |
685: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE |
[...] |
693: for (pass=2; pass < num_passes; pass++) |
694: { |
695: |
696: if (num_procs > 1) |
697: { |
698: Pext_send_map_start[pass] = hypre_CTAlloc(HYPRE_Int, num_sends+1); |
699: Pext_recv_vec_start[pass] = hypre_CTAlloc(HYPRE_Int, num_recvs+1); |
700: Pext_send_size = 0; |
701: Pext_send_map_start[pass][0] = 0; |
702: |
703: for (i=0; i < num_sends; i++) |
704: { |
705: #ifdef HYPRE_USING_OPENMP |
706: #pragma omp parallel for private(j,j1) reduction(+:Pext_send_size) HYPRE_SMP_SCHEDULE |
[...] |
717: Pext_send_map_start[pass][i+1] = Pext_send_size; |
718: } |
719: |
720: comm_handle = hypre_ParCSRCommHandleCreate (11, comm_pkg, |
721: P_ncols, &Pext_i[1]); |
722: hypre_ParCSRCommHandleDestroy(comm_handle); |
723: |
724: if (Pext_send_size > old_Pext_send_size) |
725: { |
726: hypre_TFree(Pext_send_buffer); |
727: Pext_send_buffer = hypre_CTAlloc(HYPRE_Int, Pext_send_size); |
728: } |
729: old_Pext_send_size = Pext_send_size; |
730: } |
731: |
732: cnt_offd = 0; |
733: for (i=0; i < num_sends; i++) |
734: { |
735: for (j=send_map_start[i]; j < send_map_start[i+1]; j++) |
736: { |
737: j1 = send_map_elmt[j]; |
738: if (assigned[j1] == pass-1) |
739: { |
740: j_start = P_diag_start[j1]; |
741: j_end = j_start+P_diag_i[j1+1]; |
742: for (k=j_start; k < j_end; k++) |
743: { |
744: Pext_send_buffer[cnt_offd++] = my_first_cpt |
745: +P_diag_pass[pass-1][k]; |
746: } |
747: j_start = P_offd_start[j1]; |
748: j_end = j_start+P_offd_i[j1+1]; |
749: for (k=j_start; k < j_end; k++) |
750: { |
751: k1 = P_offd_pass[pass-1][k]; |
752: k3 = 0; |
753: while (k3 < pass-1) |
754: { |
755: if (k1 < new_counter[k3+1]) |
756: { |
757: k2 = k1-new_counter[k3]; |
758: Pext_send_buffer[cnt_offd++] = new_elmts[k3][k2]; |
[...] |
768: if (num_procs > 1) |
769: { |
770: Pext_recv_size = 0; |
771: Pext_recv_vec_start[pass][0] = 0; |
772: cnt_offd = 0; |
773: for (i=0; i < num_recvs; i++) |
774: { |
775: for (j=recv_vec_start[i]; j<recv_vec_start[i+1]; j++) |
776: { |
777: if (assigned_offd[j] == pass-1) |
778: { |
779: Pext_start[j] = cnt_offd; |
780: cnt_offd += Pext_i[j+1]; |
781: } |
782: } |
783: Pext_recv_size = cnt_offd; |
784: Pext_recv_vec_start[pass][i+1] = Pext_recv_size; |
785: } |
786: |
787: hypre_ParCSRCommPkgComm(tmp_comm_pkg) = comm; |
788: hypre_ParCSRCommPkgNumSends(tmp_comm_pkg) = num_sends; |
789: hypre_ParCSRCommPkgSendProcs(tmp_comm_pkg) = send_procs; |
790: hypre_ParCSRCommPkgSendMapStarts(tmp_comm_pkg) = |
791: Pext_send_map_start[pass]; |
792: hypre_ParCSRCommPkgNumRecvs(tmp_comm_pkg) = num_recvs; |
793: hypre_ParCSRCommPkgRecvProcs(tmp_comm_pkg) = recv_procs; |
794: hypre_ParCSRCommPkgRecvVecStarts(tmp_comm_pkg) = |
795: Pext_recv_vec_start[pass]; |
796: |
797: if (Pext_recv_size) |
798: { |
799: Pext_pass[pass] = hypre_CTAlloc(HYPRE_Int, Pext_recv_size); |
800: new_elmts[pass-1] = hypre_CTAlloc(HYPRE_Int,Pext_recv_size); |
801: } |
802: else |
803: { |
804: Pext_pass[pass] = NULL; |
805: new_elmts[pass-1] = NULL; |
806: } |
807: |
808: comm_handle = hypre_ParCSRCommHandleCreate (11, tmp_comm_pkg, |
809: Pext_send_buffer, Pext_pass[pass]); |
810: hypre_ParCSRCommHandleDestroy(comm_handle); |
811: |
812: if (Pext_recv_size > old_Pext_recv_size) |
813: { |
814: hypre_TFree(loc); |
815: loc = hypre_CTAlloc(HYPRE_Int,Pext_recv_size); |
[...] |
823: for (i=0; i < num_recvs; i++) |
824: { |
825: for (j=recv_vec_start[i]; j < recv_vec_start[i+1]; j++) |
826: { |
827: if (assigned_offd[j] == pass-1) |
828: { |
829: for (j1 = cnt_offd; j1 < cnt_offd+Pext_i[j+1]; j1++) |
830: { |
831: k1 = Pext_pass[pass][j1]; |
832: k2 = k1 - my_first_cpt; |
833: if (k2 > -1 && k2 < n_coarse) |
834: { Pext_pass[pass][j1] = -k2-1; } |
835: else |
836: { |
837: not_found = 1; |
838: k3 = 0; |
839: while (k3 < pass-1 && not_found) |
840: { |
841: k2 = hypre_BinarySearch(new_elmts[k3], k1, |
842: (new_counter[k3+1]-new_counter[k3])); |
843: if (k2 > -1) |
844: { |
845: Pext_pass[pass][j1] = k2 + new_counter[k3]; |
[...] |
855: new_elmts[pass-1][cnt_new] = Pext_pass[pass][j1]; |
856: loc[cnt_new++] = j1; |
[...] |
865: if (cnt_new) |
866: { |
867: hypre_qsort2i(new_elmts[pass-1],loc,0,cnt_new-1); |
868: cnt = 0; |
869: local_index = new_counter[pass-1]; |
870: Pext_pass[pass][loc[0]] = local_index; |
871: |
872: for (i=1; i < cnt_new; i++) |
873: { |
874: if (new_elmts[pass-1][i] > new_elmts[pass-1][cnt]) |
875: { |
876: new_elmts[pass-1][++cnt] = new_elmts[pass-1][i]; |
877: local_index++; |
878: } |
879: Pext_pass[pass][loc[i]] = local_index; |
880: } |
881: new_counter[pass] = local_index+1; |
882: } |
883: else if (num_procs > 1) |
884: new_counter[pass] = new_counter[pass-1]; |
885: |
886: if (new_num_cols_offd < local_index+1) |
887: { new_num_cols_offd = local_index+1; } |
888: |
889: pass_length = pass_pointer[pass+1] - pass_pointer[pass]; |
890: #ifdef HYPRE_USING_OPENMP |
891: #pragma omp parallel private(i,my_thread_num,num_threads,thread_start,thread_stop,cnt_nz,cnt_nz_offd,i1,j,j1,j_start,j_end,k1,k,P_marker,P_marker_offd) |
[...] |
1140: hypre_TFree(loc); |
1141: hypre_TFree(P_ncols); |
1142: hypre_TFree(Pext_send_buffer); |
1143: hypre_TFree(new_recv_vec_start); |
1144: hypre_TFree(cnt_nz_per_thread); |
1145: hypre_TFree(cnt_nz_offd_per_thread); |
1146: hypre_TFree(max_num_threads); |
1147: |
1148: P_diag_j = hypre_CTAlloc(HYPRE_Int,total_nz); |
1149: P_diag_data = hypre_CTAlloc(HYPRE_Real,total_nz); |
1150: |
1151: |
1152: if (total_nz_offd) |
1153: { |
1154: P_offd_j = hypre_CTAlloc(HYPRE_Int,total_nz_offd); |
1155: P_offd_data = hypre_CTAlloc(HYPRE_Real,total_nz_offd); |
1156: } |
1157: |
1158: for (i=0; i < n_fine; i++) |
1159: { |
1160: P_diag_i[i+1] += P_diag_i[i]; |
1161: P_offd_i[i+1] += P_offd_i[i]; |
[...] |
1167: #pragma omp parallel for private(i,i1) HYPRE_SMP_SCHEDULE |
[...] |
1177: if (weight_option) /*if this is set, weights are separated into |
[...] |
1184: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,P_marker,P_marker_offd,i,i1,sum_C_pos,sum_C_neg,sum_N_pos,sum_N_neg,j_start,j_end,j,k1,cnt,j1,cnt_offd,diagonal,alfa,beta) |
[...] |
1304: if (n_coarse) hypre_TFree(C_array); |
1305: hypre_TFree(C_array_offd); |
1306: hypre_TFree(P_diag_pass[1]); |
1307: if (num_procs > 1) hypre_TFree(P_offd_pass[1]); |
1308: |
1309: |
1310: for (pass = 2; pass < num_passes; pass++) |
1311: { |
1312: |
1313: if (num_procs > 1) |
1314: { |
1315: Pext_send_size = Pext_send_map_start[pass][num_sends]; |
1316: if (Pext_send_size > old_Pext_send_size) |
1317: { |
1318: hypre_TFree(Pext_send_data); |
1319: Pext_send_data = hypre_CTAlloc(HYPRE_Real, Pext_send_size); |
1320: } |
1321: old_Pext_send_size = Pext_send_size; |
1322: |
1323: cnt_offd = 0; |
1324: for (i=0; i < num_sends; i++) |
1325: { |
1326: for (j=send_map_start[i]; j < send_map_start[i+1]; j++) |
1327: { |
1328: j1 = send_map_elmt[j]; |
1329: if (assigned[j1] == pass-1) |
1330: { |
1331: j_start = P_diag_i[j1]; |
1332: j_end = P_diag_i[j1+1]; |
1333: for (k=j_start; k < j_end; k++) |
1334: { Pext_send_data[cnt_offd++] = P_diag_data[k]; } |
1335: j_start = P_offd_i[j1]; |
1336: j_end = P_offd_i[j1+1]; |
1337: for (k=j_start; k < j_end; k++) |
1338: { Pext_send_data[cnt_offd++] = P_offd_data[k]; } |
1339: } |
1340: } |
1341: } |
1342: |
1343: hypre_ParCSRCommPkgNumSends(tmp_comm_pkg) = num_sends; |
1344: hypre_ParCSRCommPkgSendMapStarts(tmp_comm_pkg) = |
1345: Pext_send_map_start[pass]; |
1346: hypre_ParCSRCommPkgNumRecvs(tmp_comm_pkg) = num_recvs; |
1347: hypre_ParCSRCommPkgRecvVecStarts(tmp_comm_pkg) = |
1348: Pext_recv_vec_start[pass]; |
1349: |
1350: Pext_recv_size = Pext_recv_vec_start[pass][num_recvs]; |
1351: |
1352: if (Pext_recv_size > old_Pext_recv_size) |
1353: { |
1354: hypre_TFree(Pext_data); |
1355: Pext_data = hypre_CTAlloc(HYPRE_Real, Pext_recv_size); |
1356: } |
1357: old_Pext_recv_size = Pext_recv_size; |
1358: |
1359: comm_handle = hypre_ParCSRCommHandleCreate (1, tmp_comm_pkg, |
1360: Pext_send_data, Pext_data); |
1361: hypre_ParCSRCommHandleDestroy(comm_handle); |
1362: |
1363: hypre_TFree(Pext_send_map_start[pass]); |
1364: hypre_TFree(Pext_recv_vec_start[pass]); |
1365: } |
1366: |
1367: pass_length = pass_pointer[pass+1]-pass_pointer[pass]; |
1368: #ifdef HYPRE_USING_OPENMP |
1369: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,P_marker,P_marker_offd,i,i1,sum_C_neg,sum_C_pos,sum_N_neg,sum_N_pos,j_start,j_end,cnt,j,k1,cnt_offd,j1,k,alfa,beta,diagonal,C_array,C_array_offd) |
[...] |
1562: hypre_TFree(P_diag_pass[pass]); |
1563: if (num_procs > 1) |
1564: { |
1565: hypre_TFree(P_offd_pass[pass]); |
1566: hypre_TFree(Pext_pass[pass]); |
[...] |
1575: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa) |
[...] |
1669: if (n_coarse) hypre_TFree(C_array); |
1670: hypre_TFree(C_array_offd); |
1671: hypre_TFree(P_diag_pass[1]); |
1672: if (num_procs > 1) hypre_TFree(P_offd_pass[1]); |
1673: |
1674: for (pass = 2; pass < num_passes; pass++) |
1675: { |
1676: |
1677: if (num_procs > 1) |
1678: { |
1679: Pext_send_size = Pext_send_map_start[pass][num_sends]; |
1680: if (Pext_send_size > old_Pext_send_size) |
1681: { |
1682: hypre_TFree(Pext_send_data); |
1683: Pext_send_data = hypre_CTAlloc(HYPRE_Real, Pext_send_size); |
1684: } |
1685: old_Pext_send_size = Pext_send_size; |
1686: |
1687: cnt_offd = 0; |
1688: for (i=0; i < num_sends; i++) |
1689: { |
1690: for (j=send_map_start[i]; j < send_map_start[i+1]; j++) |
1691: { |
1692: j1 = send_map_elmt[j]; |
1693: if (assigned[j1] == pass-1) |
1694: { |
1695: j_start = P_diag_i[j1]; |
1696: j_end = P_diag_i[j1+1]; |
1697: for (k=j_start; k < j_end; k++) |
1698: { |
1699: Pext_send_data[cnt_offd++] = P_diag_data[k]; |
1700: } |
1701: j_start = P_offd_i[j1]; |
1702: j_end = P_offd_i[j1+1]; |
1703: for (k=j_start; k < j_end; k++) |
1704: { |
1705: Pext_send_data[cnt_offd++] = P_offd_data[k]; |
[...] |
1711: hypre_ParCSRCommPkgNumSends(tmp_comm_pkg) = num_sends; |
1712: hypre_ParCSRCommPkgSendMapStarts(tmp_comm_pkg) = |
1713: Pext_send_map_start[pass]; |
1714: hypre_ParCSRCommPkgNumRecvs(tmp_comm_pkg) = num_recvs; |
1715: hypre_ParCSRCommPkgRecvVecStarts(tmp_comm_pkg) = |
1716: Pext_recv_vec_start[pass]; |
1717: |
1718: Pext_recv_size = Pext_recv_vec_start[pass][num_recvs]; |
1719: |
1720: if (Pext_recv_size > old_Pext_recv_size) |
1721: { |
1722: hypre_TFree(Pext_data); |
1723: Pext_data = hypre_CTAlloc(HYPRE_Real, Pext_recv_size); |
1724: } |
1725: old_Pext_recv_size = Pext_recv_size; |
1726: |
1727: comm_handle = hypre_ParCSRCommHandleCreate (1, tmp_comm_pkg, |
1728: Pext_send_data, Pext_data); |
1729: hypre_ParCSRCommHandleDestroy(comm_handle); |
1730: |
1731: hypre_TFree(Pext_send_map_start[pass]); |
1732: hypre_TFree(Pext_recv_vec_start[pass]); |
1733: } |
1734: |
1735: pass_length = pass_pointer[pass+1]-pass_pointer[pass]; |
1736: #ifdef HYPRE_USING_OPENMP |
1737: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa,tmp_array,tmp_array_offd) |
[...] |
1884: hypre_TFree(P_diag_pass[pass]); |
1885: if (num_procs > 1) |
1886: { |
1887: hypre_TFree(P_offd_pass[pass]); |
1888: hypre_TFree(Pext_pass[pass]); |
1889: } |
1890: } |
1891: } |
1892: |
1893: hypre_TFree(CF_marker_offd); |
1894: hypre_TFree(Pext_send_map_start); |
1895: hypre_TFree(Pext_recv_vec_start); |
1896: hypre_TFree(dof_func_offd); |
1897: hypre_TFree(Pext_send_data); |
1898: hypre_TFree(Pext_data); |
1899: hypre_TFree(P_diag_pass); |
1900: hypre_TFree(P_offd_pass); |
1901: hypre_TFree(Pext_pass); |
1902: hypre_TFree(P_diag_start); |
1903: hypre_TFree(P_offd_start); |
1904: hypre_TFree(Pext_start); |
1905: hypre_TFree(Pext_i); |
1906: hypre_TFree(fine_to_coarse); |
1907: hypre_TFree(assigned); |
1908: hypre_TFree(assigned_offd); |
1909: hypre_TFree(pass_pointer); |
1910: hypre_TFree(pass_array); |
1911: hypre_TFree(map_S_to_new); |
1912: hypre_TFree(map_A_to_S); |
1913: if (num_procs > 1) hypre_TFree(tmp_comm_pkg); |
1914: |
1915: P = hypre_ParCSRMatrixCreate(comm, |
1916: hypre_ParCSRMatrixGlobalNumRows(A), |
1917: total_global_cpts, |
1918: hypre_ParCSRMatrixColStarts(A), |
1919: num_cpts_global, |
1920: 0, |
1921: P_diag_i[n_fine], |
1922: P_offd_i[n_fine]); |
1923: P_diag = hypre_ParCSRMatrixDiag(P); |
1924: hypre_CSRMatrixData(P_diag) = P_diag_data; |
1925: hypre_CSRMatrixI(P_diag) = P_diag_i; |
1926: hypre_CSRMatrixJ(P_diag) = P_diag_j; |
1927: P_offd = hypre_ParCSRMatrixOffd(P); |
1928: hypre_CSRMatrixData(P_offd) = P_offd_data; |
1929: hypre_CSRMatrixI(P_offd) = P_offd_i; |
1930: hypre_CSRMatrixJ(P_offd) = P_offd_j; |
1931: hypre_ParCSRMatrixOwnsRowStarts(P) = 0; |
1932: |
1933: /* Compress P, removing coefficients smaller than trunc_factor * Max |
1934: and/or keep yat most <P_max_elmts> per row absolutely maximal coefficients */ |
1935: |
1936: if (trunc_factor != 0.0 || P_max_elmts != 0) |
1937: { |
1938: hypre_BoomerAMGInterpTruncation(P, trunc_factor, P_max_elmts); |
1939: P_diag_data = hypre_CSRMatrixData(P_diag); |
1940: P_diag_i = hypre_CSRMatrixI(P_diag); |
1941: P_diag_j = hypre_CSRMatrixJ(P_diag); |
1942: P_offd_data = hypre_CSRMatrixData(P_offd); |
1943: P_offd_i = hypre_CSRMatrixI(P_offd); |
1944: P_offd_j = hypre_CSRMatrixJ(P_offd); |
1945: } |
1946: P_offd_size = P_offd_i[n_fine]; |
1947: |
1948: num_cols_offd_P = 0; |
1949: if (P_offd_size) |
1950: { |
1951: if (new_num_cols_offd > num_cols_offd) |
1952: { P_marker_offd = hypre_CTAlloc(HYPRE_Int,new_num_cols_offd); } |
1953: else |
1954: { P_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); } |
1955: #ifdef HYPRE_USING_OPENMP |
1956: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE |
1957: #endif |
1958: for (i=0; i < new_num_cols_offd; i++) |
1959: { P_marker_offd[i] = 0; } |
1960: |
1961: num_cols_offd_P = 0; |
1962: for (i=0; i < P_offd_size; i++) |
1963: { |
1964: index = P_offd_j[i]; |
1965: if (!P_marker_offd[index]) |
1966: { |
1967: num_cols_offd_P++; |
1968: P_marker_offd[index] = 1; |
1969: } |
1970: } |
1971: |
1972: col_map_offd_P = hypre_CTAlloc(HYPRE_Int,num_cols_offd_P); |
1973: permute = hypre_CTAlloc(HYPRE_Int, new_counter[num_passes-1]); |
1974: |
1975: #ifdef HYPRE_USING_OPENMP |
1976: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE |
[...] |
1982: for (i=0; i < num_passes-1; i++) |
1983: { |
1984: for (j=new_counter[i]; j < new_counter[i+1]; j++) |
1985: { |
1986: if (P_marker_offd[j]) |
1987: { |
1988: col_map_offd_P[cnt] = new_elmts[i][j-new_counter[i]]; |
1989: permute[j] = col_map_offd_P[cnt++]; |
1990: } |
1991: } |
1992: } |
1993: |
1994: hypre_qsort0(col_map_offd_P,0,num_cols_offd_P-1); |
1995: |
1996: #ifdef HYPRE_USING_OPENMP |
1997: #pragma omp parallel for private(i,k1) HYPRE_SMP_SCHEDULE |
[...] |
2007: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE |
2008: #endif |
2009: for (i=0; i < P_offd_size; i++) |
2010: { P_offd_j[i] = permute[P_offd_j[i]]; } |
2011: |
2012: hypre_TFree(P_marker_offd); |
2013: } |
2014: if (num_procs > 1) |
2015: { |
2016: for (i=0; i < num_passes-1; i++) |
2017: hypre_TFree(new_elmts[i]); |
2018: } |
2019: hypre_TFree(permute); |
2020: hypre_TFree(new_elmts); |
2021: hypre_TFree(new_counter); |
2022: |
2023: if (num_cols_offd_P) |
2024: { |
2025: hypre_ParCSRMatrixColMapOffd(P) = col_map_offd_P; |
2026: hypre_CSRMatrixNumCols(P_offd) = num_cols_offd_P; |
2027: } |
2028: |
2029: if (n_SF) |
2030: { |
2031: #ifdef HYPRE_USING_OPENMP |
2032: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE |
[...] |
2038: if (num_procs > 1) |
2039: { |
2040: hypre_MatvecCommPkgCreate(P); |
2041: } |
2042: |
2043: *P_ptr = P; |
[...] |
2060: return(0); |
0x4302e0 STR D8, [SP, #400]! |
0x4302e4 STP X29, X30, [SP, #16] |
0x4302e8 STP X28, X27, [SP, #32] |
0x4302ec STP X26, X25, [SP, #48] |
0x4302f0 STP X24, X23, [SP, #64] |
0x4302f4 STP X22, X21, [SP, #80] |
0x4302f8 STP X20, X19, [SP, #96] |
0x4302fc ADD X29, SP, #16 |
0x430300 SUB SP, SP, #1008 |
0x430304 LDP X22, X23, [X0, #56] |
0x430308 STUR X1, [X29, #504] |
0x43030c STP X5, X4, [X29, #984] |
0x430310 LDR X10, [X0] |
0x430314 MOVZ W1, #8 |
0x430318 FMOV D8, D0 |
0x43031c LDR X24, [X0, #88] |
0x430320 LDR X26, [X2, #88] |
0x430324 STP X7, X0, [SP, #304] |
0x430328 MOVZ W0, #1 |
0x43032c STR X3, [SP, #320] |
0x430330 LDR X8, [X22, #48] |
0x430334 LDR X21, [X23, #24] |
0x430338 STUR X8, [X29, #464] |
0x43033c LDP X8, X9, [X22] |
0x430340 STP XZR, X9, [X29, #952] |
0x430344 STUR X8, [X29, #456] |
0x430348 LDR X8, [X23] |
0x43034c STP XZR, X8, [X29, #936] |
0x430350 LDP X8, X25, [X2, #56] |
0x430354 LDP X9, X8, [X8] |
0x430358 LDR X28, [X25, #24] |
0x43035c STP X8, X9, [X29, #920] |
0x430360 LDR X9, [X2, #112] |
0x430364 LDR X8, [X25] |
0x430368 STUR XZR, [X29, #392] |
0x43036c STUR XZR, [X29, #352] |
0x430370 STP XZR, XZR, [X29, #840] |
0x430374 STP XZR, XZR, [X29, #808] |
0x430378 STP XZR, XZR, [X29, #792] |
0x43037c STUR XZR, [X29, #272] |
0x430380 STUR XZR, [X29, #256] |
0x430384 STR XZR, [SP, #760] |
0x430388 STR XZR, [SP, #752] |
0x43038c STR XZR, [SP, #736] |
0x430390 STR XZR, [SP, #720] |
0x430394 STR XZR, [SP, #712] |
0x430398 STR XZR, [SP, #704] |
0x43039c STR XZR, [SP, #696] |
0x4303a0 STR XZR, [SP, #688] |
0x4303a4 STR XZR, [SP, #680] |
0x4303a8 STR XZR, [SP, #672] |
0x4303ac STR XZR, [SP, #664] |
0x4303b0 STR XZR, [SP, #624] |
0x4303b4 STR XZR, [SP, #616] |
0x4303b8 STR XZR, [SP, #608] |
0x4303bc STR XZR, [SP, #600] |
0x4303c0 STR XZR, [SP, #592] |
0x4303c4 STR XZR, [SP, #584] |
0x4303c8 STR XZR, [SP, #576] |
0x4303cc STR XZR, [SP, #568] |
0x4303d0 STR XZR, [SP, #480] |
0x4303d4 STP X9, X10, [SP, #376] |
0x4303d8 STUR X8, [X29, #400] |
0x4303dc MOVN X8, #0 |
0x4303e0 STP X8, XZR, [SP, #488] |
0x4303e4 BL 4a2570 |
0x4303e8 ORR X19, XZR, X0 |
0x4303ec STR X0, [SP, #456] |
0x4303f0 BL 4a46e0 |
0x4303f4 MOVZ W1, #8 |
0x4303f8 STR X0, [X19] |
0x4303fc BL 4a2570 |
0x430400 STR X0, [SP, #448] |
0x430404 ORR X20, XZR, X0 |
0x430408 MOVZ W1, #8 |
0x43040c LDR X0, [X19] |
0x430410 BL 4a2570 |
0x430414 STR X0, [SP, #440] |
0x430418 STR XZR, [SP, #560] |
0x43041c LDR X8, [X19] |
0x430420 CMP X8, #1 |
0x430424 B.LT 430450 |
0x430428 ORR X8, XZR, XZR |
(1601) 0x43042c STR XZR, [X0, X8,LSL #3] |
(1601) 0x430430 LDR X8, [SP, #560] |
(1601) 0x430434 STR XZR, [X20, X8,LSL #3] |
(1601) 0x430438 LDR X8, [SP, #560] |
(1601) 0x43043c ADD X8, X8, #1 |
(1601) 0x430440 STR X8, [SP, #560] |
(1601) 0x430444 LDR X9, [X19] |
(1601) 0x430448 CMP X8, X9 |
(1601) 0x43044c B.LT 43042c |
0x430450 LDR X19, [SP, #384] |
0x430454 ADD X1, SP, #528 |
0x430458 ORR X0, XZR, X19 |
0x43045c BL 4a3b70 |
0x430460 ORR X0, XZR, X19 |
0x430464 ADD X1, SP, #536 |
0x430468 BL 4a3ba0 |
0x43046c LDR X9, [SP, #528] |
0x430470 LDR X8, [SP, #536] |
0x430474 SUB X3, X9, #1 |
0x430478 CMP X8, X3 |
0x43047c B.NE 43048c |
0x430480 LDR X8, [SP, #320] |
0x430484 LDR X8, [X8, #8] |
0x430488 STR X8, [SP, #520] |
0x43048c LDR X8, [SP, #320] |
0x430490 ADRP X2, |
0x430494 ADD X0, SP, #520 |
0x430498 MOVZ W1, #1 |
0x43049c LDR X27, [X8] |
0x4304a0 LDR X2, [X2, #4000] |
0x4304a4 LDR X4, [SP, #384] |
0x4304a8 BL 4a4170 |
0x4304ac LDR X8, [SP, #376] |
0x4304b0 CBZ X8, 430584 |
0x4304b4 LDR X8, [X29, #104] |
0x4304b8 CMP X8, #0 |
0x4304bc CSEL X8, X21, X28, #0 |
0x4304c0 CSEL X20, X24, X26, #0 |
0x4304c4 STUR X8, [X29, #384] |
0x4304c8 CBZ X21, 4304dc |
0x4304cc LDR X9, [X23, #48] |
0x4304d0 STUR X9, [X29, #440] |
0x4304d4 LDR X9, [X23, #8] |
0x4304d8 STUR X9, [X29, #424] |
0x4304dc CBZ X8, 4304e8 |
0x4304e0 LDR X8, [X25, #8] |
0x4304e4 STUR X8, [X29, #392] |
0x4304e8 LDR X0, [X22, #16] |
0x4304ec STR X0, [SP, #632] |
0x4304f0 CBZ X0, 430500 |
0x4304f4 MOVZ W1, #8 |
0x4304f8 BL 4a2570 |
0x4304fc STR X0, [SP, #592] |
0x430500 ADRP X0, |
0x430504 ADD X0, X0, #208 |
0x430508 ADRP X2, 432508 |
0x43050c ADD X2, X2, #3536 |
0x430510 STR XZR, [SP, #624] |
0x430514 STR XZR, [SP, #608] |
0x430518 ADD X3, SP, #632 |
0x43051c SUB X4, X29, #8 |
0x430520 ADD X5, SP, #624 |
0x430524 ADD X6, SP, #608 |
0x430528 MOVZ W1, #4 |
0x43052c BL 40f670 |
0x430530 LDR X9, [SP, #624] |
0x430534 LDR X10, [SP, #608] |
0x430538 LDR X8, [SP, #632] |
0x43053c ADD X9, X10, X9 |
0x430540 SUBS X28, X8, X9 |
0x430544 B.EQ 430558 |
0x430548 ORR X0, XZR, X28 |
0x43054c MOVZ W1, #8 |
0x430550 BL 4a2570 |
0x430554 STR X0, [SP, #760] |
0x430558 MOVZ W0, #11 |
0x43055c MOVZ W1, #8 |
0x430560 BL 4a2570 |
0x430564 STR X0, [SP, #752] |
0x430568 LDR X0, [SP, #632] |
0x43056c CBZ X0, 4305c8 |
0x430570 MOVZ W1, #8 |
0x430574 BL 4a2570 |
0x430578 LDR X8, [SP, #632] |
0x43057c STR X0, [SP, #584] |
0x430580 B 4305cc |
0x430584 LDR X8, [SP, #312] |
0x430588 LDR X8, [X8, #112] |
0x43058c STR X8, [SP, #376] |
0x430590 CBNZ X8, 4305a8 |
0x430594 LDR X19, [SP, #312] |
0x430598 ORR X0, XZR, X19 |
0x43059c BL 47d700 |
0x4305a0 LDR X8, [X19, #112] |
0x4305a4 STR X8, [SP, #376] |
0x4305a8 ORR X8, XZR, XZR |
0x4305ac STR XZR, [X29, #104] |
0x4305b0 CMP X8, #0 |
0x4305b4 CSEL X8, X21, X28, #0 |
0x4305b8 CSEL X20, X24, X26, #0 |
0x4305bc STUR X8, [X29, #384] |
0x4305c0 CBNZ X21, 4304cc |
0x4305c4 B 4304dc |
0x4305c8 ORR X8, XZR, XZR |
0x4305cc ADD X0, X8, #1 |
0x4305d0 MOVZ W1, #8 |
0x4305d4 BL 4a2570 |
0x4305d8 LDR X8, [SP, #632] |
0x4305dc STUR X0, [X29, #368] |
0x4305e0 MOVZ W1, #8 |
0x4305e4 ADD X0, X8, #1 |
0x4305e8 BL 4a2570 |
0x4305ec STUR X0, [X29, #344] |
0x4305f0 LDR X0, [SP, #624] |
0x4305f4 CBZ X0, 430604 |
0x4305f8 MOVZ W1, #8 |
0x4305fc BL 4a2570 |
0x430600 STUR X0, [X29, #264] |
0x430604 LDUR X0, [X29, #384] |
0x430608 CBZ X0, 430634 |
0x43060c MOVZ W1, #8 |
0x430610 BL 4a2570 |
0x430614 LDUR X8, [X29, #480] |
0x430618 STUR X0, [X29, #288] |
0x43061c CMP X8, #2 |
0x430620 B.LT 430634 |
0x430624 LDUR X0, [X29, #384] |
0x430628 MOVZ W1, #8 |
0x43062c BL 4a2570 |
0x430630 STUR X0, [X29, #280] |
0x430634 LDR X8, [SP, #528] |
0x430638 CMP X8, #1 |
0x43063c B.LE 430690 |
0x430640 LDR X11, [SP, #376] |
0x430644 LDP X8, X9, [X11, #8] |
0x430648 STR X9, [SP, #336] |
0x43064c LDP X9, X10, [X11, #24] |
0x430650 STUR X10, [X29, #312] |
0x430654 LDR X10, [X11, #40] |
0x430658 STP X9, X8, [X29, #832] |
0x43065c LDR X0, [X9, X8,LSL #3] |
0x430660 STR X10, [SP, #416] |
0x430664 LDP X10, X19, [X11, #48] |
0x430668 STR X10, [SP, #328] |
0x43066c CBZ X0, 4306ac |
0x430670 MOVZ W1, #8 |
0x430674 BL 4a2570 |
0x430678 ORR X25, XZR, X0 |
0x43067c LDUR X13, [X29, #328] |
0x430680 STR XZR, [SP, #560] |
0x430684 CMP X13, #1 |
0x430688 B.GE 4306c0 |
0x43068c B 430730 |
0x430690 STR XZR, [SP, #416] |
0x430694 ORR X25, XZR, XZR |
0x430698 LDUR X13, [X29, #328] |
0x43069c STR XZR, [SP, #560] |
0x4306a0 CMP X13, #1 |
0x4306a4 B.GE 4306c0 |
0x4306a8 B 430730 |
0x4306ac ORR X25, XZR, XZR |
0x4306b0 LDUR X13, [X29, #328] |
0x4306b4 STR XZR, [SP, #560] |
0x4306b8 CMP X13, #1 |
0x4306bc B.LT 430730 |
0x4306c0 LDP X11, X8, [X29, #824] |
0x4306c4 LDUR X9, [X29, #504] |
0x4306c8 ORR X10, XZR, XZR |
0x4306cc ORR X12, XZR, XZR |
0x4306d0 B 4306ec |
0x4306d4 HINT #0 |
0x4306d8 HINT #0 |
0x4306dc HINT #0 |
(1599) 0x4306e0 CMP X12, X13 |
(1599) 0x4306e4 STR X12, [SP, #560] |
(1599) 0x4306e8 B.GE 430730 |
(1599) 0x4306ec LDR X14, [X8, X12,LSL #3] |
(1599) 0x4306f0 ADD X12, X12, #1 |
(1599) 0x4306f4 LDR X15, [X8, X12,LSL #3] |
(1599) 0x4306f8 CMP X14, X15 |
(1599) 0x4306fc B.GE 4306e0 |
(1600) 0x430700 LDR X12, [X11, X14,LSL #3] |
(1600) 0x430704 ADD X14, X14, #1 |
(1600) 0x430708 LDR X12, [X9, X12,LSL #3] |
(1600) 0x43070c STR X12, [X25, X10,LSL #3] |
(1600) 0x430710 ADD X10, X10, #1 |
(1600) 0x430714 LDR X12, [SP, #560] |
(1600) 0x430718 ADD X12, X12, #1 |
(1600) 0x43071c LDR X13, [X8, X12,LSL #3] |
(1600) 0x430720 CMP X14, X13 |
(1600) 0x430724 B.LT 430700 |
(1599) 0x430728 LDUR X13, [X29, #328] |
(1599) 0x43072c B 4306e0 |
0x430730 LDR X8, [SP, #528] |
0x430734 CMP X8, #1 |
0x430738 B.LE 430754 |
0x43073c LDUR X3, [X29, #288] |
0x430740 LDR X1, [SP, #376] |
0x430744 ORR X2, XZR, X25 |
0x430748 MOVZ W0, #11 |
0x43074c BL 47cbc0 |
0x430750 BL 47cfa0 |
0x430754 LDUR X8, [X29, #480] |
0x430758 CMP X8, #2 |
0x43075c B.LT 4307f8 |
0x430760 LDUR X13, [X29, #328] |
0x430764 STR XZR, [SP, #560] |
0x430768 CMP X13, #1 |
0x43076c B.LT 4307d4 |
0x430770 LDP X11, X8, [X29, #824] |
0x430774 LDUR X9, [X29, #472] |
0x430778 ORR X10, XZR, XZR |
0x43077c ORR X12, XZR, XZR |
0x430780 B 430790 |
(1597) 0x430784 CMP X12, X13 |
(1597) 0x430788 STR X12, [SP, #560] |
(1597) 0x43078c B.GE 4307d4 |
(1597) 0x430790 LDR X14, [X8, X12,LSL #3] |
(1597) 0x430794 ADD X12, X12, #1 |
(1597) 0x430798 LDR X15, [X8, X12,LSL #3] |
(1597) 0x43079c CMP X14, X15 |
(1597) 0x4307a0 B.GE 430784 |
(1598) 0x4307a4 LDR X12, [X11, X14,LSL #3] |
(1598) 0x4307a8 ADD X14, X14, #1 |
(1598) 0x4307ac LDR X12, [X9, X12,LSL #3] |
(1598) 0x4307b0 STR X12, [X25, X10,LSL #3] |
(1598) 0x4307b4 ADD X10, X10, #1 |
(1598) 0x4307b8 LDR X12, [SP, #560] |
(1598) 0x4307bc ADD X12, X12, #1 |
(1598) 0x4307c0 LDR X13, [X8, X12,LSL #3] |
(1598) 0x4307c4 CMP X14, X13 |
(1598) 0x4307c8 B.LT 4307a4 |
(1597) 0x4307cc LDUR X13, [X29, #328] |
(1597) 0x4307d0 B 430784 |
0x4307d4 LDR X8, [SP, #528] |
0x4307d8 CMP X8, #1 |
0x4307dc B.LE 4307f8 |
0x4307e0 LDUR X3, [X29, #280] |
0x4307e4 LDR X1, [SP, #376] |
0x4307e8 ORR X2, XZR, X25 |
0x4307ec MOVZ W0, #11 |
0x4307f0 BL 47cbc0 |
0x4307f4 BL 47cfa0 |
0x4307f8 ADRP X0, |
0x4307fc ADD X0, X0, #304 |
0x430800 ADRP X2, 432800 |
0x430804 ADD X2, X2, #4048 |
0x430808 STR X19, [SP, #424] |
0x43080c STR XZR, [SP, #616] |
0x430810 STR XZR, [SP, #600] |
0x430814 SUB X3, X29, #128 |
0x430818 SUB X4, X29, #224 |
0x43081c ADD X5, SP, #616 |
0x430820 ADD X6, SP, #600 |
0x430824 MOVZ W1, #4 |
0x430828 BL 40f670 |
0x43082c LDUR X0, [X29, #384] |
0x430830 CBZ X0, 430874 |
0x430834 MOVZ W1, #8 |
0x430838 BL 4a2570 |
0x43083c STR X0, [SP, #576] |
0x430840 LDUR X0, [X29, #384] |
0x430844 MOVZ W1, #8 |
0x430848 BL 4a2570 |
0x43084c STR X0, [SP, #688] |
0x430850 LDUR X0, [X29, #384] |
0x430854 MOVZ W1, #8 |
0x430858 BL 4a2570 |
0x43085c ORR X19, XZR, X0 |
0x430860 LDR X0, [SP, #616] |
0x430864 MOVZ W1, #8 |
0x430868 BL 4a2570 |
0x43086c ORR X26, XZR, X0 |
0x430870 B 43087c |
0x430874 ORR X19, XZR, XZR |
0x430878 ORR X26, XZR, XZR |
0x43087c LDUR X12, [X29, #368] |
0x430880 SUB X23, X28, #1 |
0x430884 STR XZR, [X12] |
0x430888 LDUR X13, [X29, #344] |
0x43088c STR XZR, [X13] |
0x430890 STR XZR, [SP, #560] |
0x430894 LDR X8, [SP, #632] |
0x430898 CMP X8, #1 |
0x43089c B.LT 430974 |
0x4308a0 LDUR X8, [X29, #504] |
0x4308a4 LDR X9, [SP, #760] |
0x4308a8 LDR X10, [SP, #584] |
0x4308ac ORR X11, XZR, XZR |
0x4308b0 ORR X0, XZR, XZR |
0x4308b4 ORR X18, XZR, X23 |
0x4308b8 LDR X15, [SP, #592] |
0x4308bc LDUR X17, [X29, #264] |
0x4308c0 ADD X12, X12, #8 |
0x4308c4 ADD X13, X13, #8 |
0x4308c8 MOVN X14, #0 |
0x4308cc MOVZ W16, #1 |
0x4308d0 B 430920 |
0x4308d4 HINT #0 |
0x4308d8 HINT #0 |
0x4308dc HINT #0 |
(1594) 0x4308e0 STR X0, [X9, X18,LSL #3] |
(1594) 0x4308e4 SUB X18, X18, #1 |
(1594) 0x4308e8 LDR X0, [SP, #560] |
(1595) 0x4308ec STR XZR, [X12, X0,LSL #3] |
(1595) 0x4308f0 LDR X0, [SP, #560] |
(1595) 0x4308f4 STR XZR, [X13, X0,LSL #3] |
(1595) 0x4308f8 LDR X0, [SP, #560] |
(1595) 0x4308fc STR X14, [X10, X0,LSL #3] |
(1595) 0x430900 LDR X0, [SP, #560] |
(1595) 0x430904 STR X14, [X15, X0,LSL #3] |
(1595) 0x430908 LDR X0, [SP, #560] |
(1595) 0x43090c LDR X1, [SP, #632] |
(1595) 0x430910 ADD X0, X0, #1 |
(1595) 0x430914 CMP X0, X1 |
(1595) 0x430918 STR X0, [SP, #560] |
(1595) 0x43091c B.GE 430974 |
(1596) 0x430920 LDR X1, [X8, X0,LSL #3] |
(1596) 0x430924 CMN X1, #1 |
(1596) 0x430928 B.EQ 4308e0 |
(1596) 0x43092c CMP X1, #1 |
(1596) 0x430930 B.NE 4308ec |
(1596) 0x430934 STR X11, [X15, X0,LSL #3] |
(1596) 0x430938 LDR X0, [SP, #560] |
(1596) 0x43093c STR X0, [X17, X11,LSL #3] |
(1596) 0x430940 ADD X11, X11, #1 |
(1596) 0x430944 LDR X0, [SP, #560] |
(1596) 0x430948 STR XZR, [X10, X0,LSL #3] |
(1596) 0x43094c LDR X0, [SP, #560] |
(1596) 0x430950 STR X16, [X12, X0,LSL #3] |
(1596) 0x430954 LDR X0, [SP, #560] |
(1596) 0x430958 STR XZR, [X13, X0,LSL #3] |
(1596) 0x43095c LDR X0, [SP, #560] |
(1596) 0x430960 LDR X1, [SP, #632] |
(1596) 0x430964 ADD X0, X0, #1 |
(1596) 0x430968 CMP X0, X1 |
(1596) 0x43096c STR X0, [SP, #560] |
(1596) 0x430970 B.LT 430920 |
0x430974 LDUR X13, [X29, #328] |
0x430978 STR XZR, [SP, #560] |
0x43097c CMP X13, #1 |
0x430980 B.LT 4309fc |
0x430984 LDP X11, X9, [X29, #824] |
0x430988 LDR X10, [SP, #592] |
0x43098c ORR X8, XZR, XZR |
0x430990 ORR X12, XZR, XZR |
0x430994 B 4309ac |
0x430998 HINT #0 |
0x43099c HINT #0 |
(1592) 0x4309a0 CMP X12, X13 |
(1592) 0x4309a4 STR X12, [SP, #560] |
(1592) 0x4309a8 B.GE 4309fc |
(1592) 0x4309ac LDR X14, [X9, X12,LSL #3] |
(1592) 0x4309b0 ADD X12, X12, #1 |
(1592) 0x4309b4 LDR X15, [X9, X12,LSL #3] |
(1592) 0x4309b8 CMP X14, X15 |
(1592) 0x4309bc B.GE 4309a0 |
(1593) 0x4309c0 LDR X12, [X11, X14,LSL #3] |
(1593) 0x4309c4 ADD X14, X14, #1 |
(1593) 0x4309c8 LDR X12, [X10, X12,LSL #3] |
(1593) 0x4309cc CMP X12, #0 |
(1593) 0x4309d0 CSEL X13, XZR, X27, #11 |
(1593) 0x4309d4 ADD X12, X13, X12 |
(1593) 0x4309d8 STR X12, [X25, X8,LSL #3] |
(1593) 0x4309dc ADD X8, X8, #1 |
(1593) 0x4309e0 LDR X12, [SP, #560] |
(1593) 0x4309e4 ADD X12, X12, #1 |
(1593) 0x4309e8 LDR X13, [X9, X12,LSL #3] |
(1593) 0x4309ec CMP X14, X13 |
(1593) 0x4309f0 B.LT 4309c0 |
(1592) 0x4309f4 LDUR X13, [X29, #328] |
(1592) 0x4309f8 B 4309a0 |
0x4309fc LDR X8, [SP, #528] |
0x430a00 CMP X8, #1 |
0x430a04 B.LE 430a20 |
0x430a08 LDR X1, [SP, #376] |
0x430a0c ORR X2, XZR, X25 |
0x430a10 ORR X3, XZR, X19 |
0x430a14 MOVZ W0, #11 |
0x430a18 BL 47cbc0 |
0x430a1c BL 47cfa0 |
0x430a20 LDR X8, [SP, #416] |
0x430a24 MOVZ W1, #8 |
0x430a28 ADD X0, X8, #1 |
0x430a2c STR X0, [SP, #344] |
0x430a30 BL 4a2570 |
0x430a34 ORR X22, XZR, X0 |
0x430a38 LDR X0, [SP, #616] |
0x430a3c CBZ X0, 430a4c |
0x430a40 MOVZ W1, #8 |
0x430a44 BL 4a2570 |
0x430a48 STUR X0, [X29, #256] |
0x430a4c LDR X8, [SP, #416] |
0x430a50 STR XZR, [X22] |
0x430a54 CMP X8, #1 |
0x430a58 B.LT 430b1c |
0x430a5c LDUR X9, [X29, #288] |
0x430a60 ORR X8, XZR, XZR |
0x430a64 ORR X10, XZR, XZR |
0x430a68 MOVN X11, #0 |
0x430a6c B 430a90 |
0x430a70 HINT #0 |
0x430a74 HINT #0 |
0x430a78 HINT #0 |
0x430a7c HINT #0 |
(1589) 0x430a80 LDR X12, [SP, #416] |
(1589) 0x430a84 STR X10, [X22, X8,LSL #3] |
(1589) 0x430a88 CMP X8, X12 |
(1589) 0x430a8c B.EQ 430b1c |
(1589) 0x430a90 LDR X12, [SP, #424] |
(1589) 0x430a94 LDR X15, [X12, X8,LSL #3] |
(1589) 0x430a98 ADD X8, X8, #1 |
(1589) 0x430a9c STR X15, [SP, #560] |
(1589) 0x430aa0 LDR X12, [X12, X8,LSL #3] |
(1589) 0x430aa4 CMP X15, X12 |
(1589) 0x430aa8 B.GE 430a80 |
(1591) 0x430aac LDR X12, [SP, #576] |
(1591) 0x430ab0 LDR X13, [SP, #688] |
(1591) 0x430ab4 LDUR X14, [X29, #256] |
(1591) 0x430ab8 B 430ae8 |
0x430abc HINT #0 |
(1590) 0x430ac0 STR X11, [X12, X15,LSL #3] |
(1590) 0x430ac4 LDR X15, [SP, #560] |
(1590) 0x430ac8 STR X11, [X13, X15,LSL #3] |
(1591) 0x430acc LDR X15, [SP, #560] |
(1591) 0x430ad0 LDR X16, [SP, #424] |
(1591) 0x430ad4 ADD X15, X15, #1 |
(1591) 0x430ad8 STR X15, [SP, #560] |
(1591) 0x430adc LDR X16, [X16, X8,LSL #3] |
(1591) 0x430ae0 CMP X15, X16 |
(1591) 0x430ae4 B.GE 430a80 |
(1591) 0x430ae8 LDR X16, [X9, X15,LSL #3] |
(1591) 0x430aec CMP X16, #1 |
(1591) 0x430af0 B.NE 430ac0 |
(1591) 0x430af4 STR X10, [X13, X15,LSL #3] |
(1591) 0x430af8 LDR X15, [SP, #560] |
(1591) 0x430afc STR X15, [X14, X10,LSL #3] |
(1591) 0x430b00 LDR X15, [SP, #560] |
(1591) 0x430b04 LDR X15, [X19, X15,LSL #3] |
(1591) 0x430b08 STR X15, [X26, X10,LSL #3] |
(1591) 0x430b0c ADD X10, X10, #1 |
(1591) 0x430b10 LDR X15, [SP, #560] |
(1591) 0x430b14 STR XZR, [X12, X15,LSL #3] |
(1591) 0x430b18 B 430acc |
0x430b1c ORR X0, XZR, X19 |
0x430b20 BL 4a2670 |
0x430b24 LDR X8, [X29, #104] |
0x430b28 CBZ X8, 430bb4 |
0x430b2c ORR X0, XZR, X21 |
0x430b30 MOVZ W1, #8 |
0x430b34 BL 4a2570 |
0x430b38 CMP X21, #1 |
0x430b3c STR X0, [SP, #680] |
0x430b40 STR XZR, [SP, #560] |
0x430b44 B.LT 430bb4 |
0x430b48 ORR X8, XZR, XZR |
0x430b4c ORR X9, XZR, XZR |
0x430b50 B 430b8c |
0x430b54 HINT #0 |
0x430b58 HINT #0 |
0x430b5c HINT #0 |
(1587) 0x430b60 LDR X10, [X24, X9,LSL #3] |
(1587) 0x430b64 LDR X11, [X20, X8,LSL #3] |
(1587) 0x430b68 CMP X10, X11 |
(1587) 0x430b6c CSINV X10, X8, XZR, #0 |
(1587) 0x430b70 CSINC X8, X8, X8, #1 |
(1587) 0x430b74 STR X10, [X0, X9,LSL #3] |
(1587) 0x430b78 LDR X9, [SP, #560] |
(1587) 0x430b7c ADD X9, X9, #1 |
(1587) 0x430b80 CMP X9, X21 |
(1587) 0x430b84 STR X9, [SP, #560] |
(1587) 0x430b88 B.GE 430bb4 |
(1588) 0x430b8c LDUR X10, [X29, #384] |
(1588) 0x430b90 CMP X8, X10 |
(1588) 0x430b94 B.LT 430b60 |
(1588) 0x430b98 MOVN X10, #0 |
(1588) 0x430b9c STR X10, [X0, X9,LSL #3] |
(1588) 0x430ba0 LDR X9, [SP, #560] |
(1588) 0x430ba4 ADD X9, X9, #1 |
(1588) 0x430ba8 CMP X9, X21 |
(1588) 0x430bac STR X9, [SP, #560] |
(1588) 0x430bb0 B.LT 430b8c |
0x430bb4 LDR X8, [SP, #752] |
0x430bb8 STR X22, [SP, #296] |
0x430bbc ORR X22, XZR, X23 |
0x430bc0 CMP X28, #1 |
0x430bc4 STP XZR, XZR, [X8] |
0x430bc8 STR XZR, [SP, #512] |
0x430bcc LDR X9, [SP, #624] |
0x430bd0 STR X23, [SP, #560] |
0x430bd4 STR X9, [SP, #656] |
0x430bd8 B.LT 430d0c |
0x430bdc LDR X9, [SP, #760] |
0x430be0 LDP X11, X10, [X29, #920] |
0x430be4 LDUR X12, [X29, #504] |
0x430be8 ORR X19, XZR, XZR |
0x430bec ORR X23, XZR, XZR |
0x430bf0 ORR X20, XZR, XZR |
0x430bf4 LDP X14, X13, [X29, #904] |
0x430bf8 LDUR X15, [X29, #288] |
0x430bfc LDR X17, [SP, #584] |
0x430c00 ORR X18, XZR, X22 |
0x430c04 MOVZ W16, #1 |
0x430c08 B 430c20 |
(1584) 0x430c0c LDR X0, [SP, #560] |
(1584) 0x430c10 SUB X18, X0, #1 |
(1584) 0x430c14 CMP X0, X23 |
(1584) 0x430c18 STR X18, [SP, #560] |
(1584) 0x430c1c B.LE 430d18 |
(1584) 0x430c20 LDR X18, [X9, X18,LSL #3] |
(1584) 0x430c24 ADD X0, X18, #1 |
(1584) 0x430c28 LDR X1, [X10, X18,LSL #3] |
(1584) 0x430c2c LDR X3, [X10, X0,LSL #3] |
(1584) 0x430c30 CMP X1, X3 |
(1584) 0x430c34 B.GE 430c80 |
(1584) 0x430c38 LDUR X2, [X29, #368] |
(1584) 0x430c3c LDR X4, [SP, #584] |
(1584) 0x430c40 B 430c50 |
(1586) 0x430c44 ADD X1, X1, #1 |
(1586) 0x430c48 CMP X1, X3 |
(1586) 0x430c4c B.GE 430c80 |
(1586) 0x430c50 LDR X5, [X11, X1,LSL #3] |
(1586) 0x430c54 LDR X5, [X12, X5,LSL #3] |
(1586) 0x430c58 CMP X5, #1 |
(1586) 0x430c5c B.NE 430c44 |
(1586) 0x430c60 LDR X3, [X2, X0,LSL #3] |
(1586) 0x430c64 ADD X20, X20, #1 |
(1586) 0x430c68 ADD X3, X3, #1 |
(1586) 0x430c6c STR X3, [X2, X0,LSL #3] |
(1586) 0x430c70 STR X16, [X4, X18,LSL #3] |
(1586) 0x430c74 LDR X3, [X10, X0,LSL #3] |
(1586) 0x430c78 B 430c44 |
0x430c7c HINT #0 |
(1584) 0x430c80 LDR X1, [X13, X18,LSL #3] |
(1584) 0x430c84 LDR X4, [X13, X0,LSL #3] |
(1584) 0x430c88 CMP X1, X4 |
(1584) 0x430c8c B.GE 430ce0 |
(1584) 0x430c90 LDUR X2, [X29, #344] |
(1584) 0x430c94 LDR X3, [SP, #584] |
(1584) 0x430c98 B 430cac |
0x430c9c HINT #0 |
(1585) 0x430ca0 ADD X1, X1, #1 |
(1585) 0x430ca4 CMP X1, X4 |
(1585) 0x430ca8 B.GE 430ce0 |
(1585) 0x430cac LDR X5, [X14, X1,LSL #3] |
(1585) 0x430cb0 LDR X5, [X15, X5,LSL #3] |
(1585) 0x430cb4 CMP X5, #1 |
(1585) 0x430cb8 B.NE 430ca0 |
(1585) 0x430cbc LDR X4, [X2, X0,LSL #3] |
(1585) 0x430cc0 ADD X19, X19, #1 |
(1585) 0x430cc4 ADD X4, X4, #1 |
(1585) 0x430cc8 STR X4, [X2, X0,LSL #3] |
(1585) 0x430ccc STR X16, [X3, X18,LSL #3] |
(1585) 0x430cd0 LDR X4, [X13, X0,LSL #3] |
(1585) 0x430cd4 B 430ca0 |
0x430cd8 HINT #0 |
0x430cdc HINT #0 |
(1584) 0x430ce0 LDR X0, [X17, X18,LSL #3] |
(1584) 0x430ce4 CMP X0, #1 |
(1584) 0x430ce8 B.NE 430c0c |
(1584) 0x430cec LDR X1, [SP, #560] |
(1584) 0x430cf0 LDR X0, [X9, X23,LSL #3] |
(1584) 0x430cf4 ADD X2, X1, #1 |
(1584) 0x430cf8 STR X2, [SP, #560] |
(1584) 0x430cfc STR X0, [X9, X1,LSL #3] |
(1584) 0x430d00 STR X18, [X9, X23,LSL #3] |
(1584) 0x430d04 ADD X23, X23, #1 |
(1584) 0x430d08 B 430c0c |
0x430d0c ORR X20, XZR, XZR |
0x430d10 ORR X23, XZR, XZR |
0x430d14 ORR X19, XZR, XZR |
0x430d18 LDUR X13, [X29, #328] |
0x430d1c STR X23, [X8, #16] |
0x430d20 STR XZR, [SP, #560] |
0x430d24 CMP X13, #1 |
0x430d28 B.LT 430d90 |
0x430d2c LDP X11, X8, [X29, #824] |
0x430d30 LDR X9, [SP, #584] |
0x430d34 ORR X10, XZR, XZR |
0x430d38 ORR X12, XZR, XZR |
0x430d3c B 430d4c |
(1582) 0x430d40 CMP X12, X13 |
(1582) 0x430d44 STR X12, [SP, #560] |
(1582) 0x430d48 B.GE 430d90 |
(1582) 0x430d4c LDR X14, [X8, X12,LSL #3] |
(1582) 0x430d50 ADD X12, X12, #1 |
(1582) 0x430d54 LDR X15, [X8, X12,LSL #3] |
(1582) 0x430d58 CMP X14, X15 |
(1582) 0x430d5c B.GE 430d40 |
(1583) 0x430d60 LDR X12, [X11, X14,LSL #3] |
(1583) 0x430d64 ADD X14, X14, #1 |
(1583) 0x430d68 LDR X12, [X9, X12,LSL #3] |
(1583) 0x430d6c STR X12, [X25, X10,LSL #3] |
(1583) 0x430d70 ADD X10, X10, #1 |
(1583) 0x430d74 LDR X12, [SP, #560] |
(1583) 0x430d78 ADD X12, X12, #1 |
(1583) 0x430d7c LDR X13, [X8, X12,LSL #3] |
(1583) 0x430d80 CMP X14, X13 |
(1583) 0x430d84 B.LT 430d60 |
(1582) 0x430d88 LDUR X13, [X29, #328] |
(1582) 0x430d8c B 430d40 |
0x430d90 LDR X8, [SP, #528] |
0x430d94 CMP X8, #1 |
0x430d98 B.LE 430db4 |
0x430d9c LDR X3, [SP, #576] |
0x430da0 LDR X1, [SP, #376] |
0x430da4 ORR X2, XZR, X25 |
0x430da8 MOVZ W0, #11 |
0x430dac BL 47cbc0 |
0x430db0 BL 47cfa0 |
0x430db4 MOVZ W8, #2 |
0x430db8 ADRP X3, |
0x430dbc ADRP X4, |
0x430dc0 ADD X0, SP, #544 |
0x430dc4 STR X8, [SP, #648] |
0x430dc8 SUB X8, X28, X23 |
0x430dcc ADD X1, SP, #552 |
0x430dd0 MOVZ W2, #1 |
0x430dd4 STR X8, [SP, #544] |
0x430dd8 LDR X3, [X3, #4000] |
0x430ddc LDR X4, [X4, #4032] |
0x430de0 LDR X5, [SP, #384] |
0x430de4 BL 4a43b0 |
0x430de8 LDR X8, [SP, #552] |
0x430dec CBZ X8, 430ff8 |
0x430df0 LDR X8, [SP, #648] |
0x430df4 CMP X8, #9 |
0x430df8 B.GT 430ff8 |
0x430dfc ADRP X21, |
0x430e00 ADRP X24, |
0x430e04 LDR X21, [X21, #4000] |
0x430e08 LDR X24, [X24, #4032] |
(1576) 0x430e0c CMP X28, X23 |
(1576) 0x430e10 STR X22, [SP, #560] |
(1576) 0x430e14 B.LE 430f04 |
(1576) 0x430e18 LDR X8, [SP, #760] |
(1576) 0x430e1c LDP X10, X9, [X29, #920] |
(1576) 0x430e20 LDR X11, [SP, #584] |
(1576) 0x430e24 ORR X15, XZR, X22 |
(1576) 0x430e28 LDP X13, X12, [X29, #904] |
(1576) 0x430e2c LDR X14, [SP, #576] |
(1576) 0x430e30 B 430e74 |
0x430e34 HINT #0 |
0x430e38 HINT #0 |
0x430e3c HINT #0 |
(1579) 0x430e40 LDR X17, [X8, X23,LSL #3] |
(1579) 0x430e44 ADD X18, X15, #1 |
(1579) 0x430e48 STR X18, [SP, #560] |
(1579) 0x430e4c STR X17, [X8, X15,LSL #3] |
(1579) 0x430e50 STR X16, [X8, X23,LSL #3] |
(1579) 0x430e54 ADD X23, X23, #1 |
(1579) 0x430e58 LDR X15, [SP, #648] |
(1579) 0x430e5c STR X15, [X11, X16,LSL #3] |
(1579) 0x430e60 LDR X15, [SP, #560] |
(1579) 0x430e64 CMP X15, X23 |
(1579) 0x430e68 SUB X15, X15, #1 |
(1579) 0x430e6c STR X15, [SP, #560] |
(1579) 0x430e70 B.LE 430f00 |
(1579) 0x430e74 LDR X16, [X8, X15,LSL #3] |
(1579) 0x430e78 ADD X17, X16, #1 |
(1579) 0x430e7c LDR X1, [X9, X16,LSL #3] |
(1579) 0x430e80 LDR X0, [X9, X17,LSL #3] |
(1579) 0x430e84 CMP X1, X0 |
(1579) 0x430e88 B.GE 430ebc |
(1579) 0x430e8c LDR X18, [SP, #648] |
(1579) 0x430e90 SUB X0, X0, X1 |
(1579) 0x430e94 ADD X1, X10, X1,LSL #3 |
(1579) 0x430e98 SUB X18, X18, #1 |
(1579) 0x430e9c HINT #0 |
(1581) 0x430ea0 LDR X2, [X1] |
(1581) 0x430ea4 LDR X2, [X11, X2,LSL #3] |
(1581) 0x430ea8 CMP X2, X18 |
(1581) 0x430eac B.EQ 430e40 |
(1581) 0x430eb0 SUBS X0, X0, #1 |
(1581) 0x430eb4 ADD X1, X1, #8 |
(1581) 0x430eb8 B.NE 430ea0 |
(1579) 0x430ebc LDR X0, [X12, X16,LSL #3] |
(1579) 0x430ec0 LDR X18, [X12, X17,LSL #3] |
(1579) 0x430ec4 CMP X0, X18 |
(1579) 0x430ec8 B.GE 430e64 |
(1579) 0x430ecc LDR X17, [SP, #648] |
(1579) 0x430ed0 SUB X18, X18, X0 |
(1579) 0x430ed4 ADD X0, X13, X0,LSL #3 |
(1579) 0x430ed8 SUB X17, X17, #1 |
(1579) 0x430edc HINT #0 |
(1580) 0x430ee0 LDR X1, [X0] |
(1580) 0x430ee4 LDR X1, [X14, X1,LSL #3] |
(1580) 0x430ee8 CMP X1, X17 |
(1580) 0x430eec B.EQ 430e40 |
(1580) 0x430ef0 SUBS X18, X18, #1 |
(1580) 0x430ef4 ADD X0, X0, #8 |
(1580) 0x430ef8 B.NE 430ee0 |
(1579) 0x430efc B 430e64 |
(1576) 0x430f00 LDR X8, [SP, #648] |
(1576) 0x430f04 LDR X9, [SP, #752] |
(1576) 0x430f08 LDR X5, [SP, #384] |
(1576) 0x430f0c ADD X8, X8, #1 |
(1576) 0x430f10 ORR X3, XZR, X21 |
(1576) 0x430f14 ORR X4, XZR, X24 |
(1576) 0x430f18 ADD X0, SP, #544 |
(1576) 0x430f1c ADD X1, SP, #552 |
(1576) 0x430f20 STR X8, [SP, #648] |
(1576) 0x430f24 MOVZ W2, #1 |
(1576) 0x430f28 STR X23, [X9, X8,LSL #3] |
(1576) 0x430f2c SUB X8, X28, X23 |
(1576) 0x430f30 STR X8, [SP, #544] |
(1576) 0x430f34 BL 4a43b0 |
(1576) 0x430f38 LDUR X13, [X29, #328] |
(1576) 0x430f3c STR XZR, [SP, #560] |
(1576) 0x430f40 CMP X13, #1 |
(1576) 0x430f44 B.LT 430fc0 |
(1576) 0x430f48 LDP X11, X8, [X29, #824] |
(1576) 0x430f4c LDR X9, [SP, #584] |
(1576) 0x430f50 ORR X10, XZR, XZR |
(1576) 0x430f54 ORR X12, XZR, XZR |
(1576) 0x430f58 B 430f6c |
0x430f5c HINT #0 |
(1577) 0x430f60 CMP X12, X13 |
(1577) 0x430f64 STR X12, [SP, #560] |
(1577) 0x430f68 B.GE 430fc0 |
(1577) 0x430f6c LDR X14, [X8, X12,LSL #3] |
(1577) 0x430f70 ADD X12, X12, #1 |
(1577) 0x430f74 LDR X15, [X8, X12,LSL #3] |
(1577) 0x430f78 CMP X14, X15 |
(1577) 0x430f7c B.GE 430f60 |
(1578) 0x430f80 LDR X12, [X11, X14,LSL #3] |
(1578) 0x430f84 ADD X14, X14, #1 |
(1578) 0x430f88 LDR X12, [X9, X12,LSL #3] |
(1578) 0x430f8c STR X12, [X25, X10,LSL #3] |
(1578) 0x430f90 ADD X10, X10, #1 |
(1578) 0x430f94 LDR X12, [SP, #560] |
(1578) 0x430f98 ADD X12, X12, #1 |
(1578) 0x430f9c LDR X13, [X8, X12,LSL #3] |
(1578) 0x430fa0 CMP X14, X13 |
(1578) 0x430fa4 B.LT 430f80 |
(1577) 0x430fa8 LDUR X13, [X29, #328] |
(1577) 0x430fac B 430f60 |
0x430fb0 HINT #0 |
0x430fb4 HINT #0 |
0x430fb8 HINT #0 |
0x430fbc HINT #0 |
(1576) 0x430fc0 LDR X8, [SP, #528] |
(1576) 0x430fc4 CMP X8, #1 |
(1576) 0x430fc8 B.LE 430fe4 |
(1576) 0x430fcc LDR X3, [SP, #576] |
(1576) 0x430fd0 LDR X1, [SP, #376] |
(1576) 0x430fd4 ORR X2, XZR, X25 |
(1576) 0x430fd8 MOVZ W0, #11 |
(1576) 0x430fdc BL 47cbc0 |
(1576) 0x430fe0 BL 47cfa0 |
(1576) 0x430fe4 LDR X8, [SP, #552] |
(1576) 0x430fe8 CBZ X8, 430ff8 |
(1576) 0x430fec LDR X8, [SP, #648] |
(1576) 0x430ff0 CMP X8, #10 |
(1576) 0x430ff4 B.LT 430e0c |
0x430ff8 ORR X0, XZR, X25 |
0x430ffc BL 4a2670 |
0x431000 LDR X21, [SP, #648] |
0x431004 MOVZ W1, #8 |
0x431008 ORR X0, XZR, X21 |
0x43100c STR X21, [SP, #640] |
0x431010 BL 4a2570 |
0x431014 STR X0, [SP, #728] |
0x431018 ORR X0, XZR, X20 |
0x43101c MOVZ W1, #8 |
0x431020 BL 4a2570 |
0x431024 LDR X8, [SP, #728] |
0x431028 MOVZ W1, #8 |
0x43102c STR X0, [X8, #8] |
0x431030 LDR X0, [SP, #632] |
0x431034 BL 4a2570 |
0x431038 STR X0, [SP, #744] |
0x43103c LDR X0, [SP, #632] |
0x431040 MOVZ W1, #8 |
0x431044 BL 4a2570 |
0x431048 LDR X8, [SP, #528] |
0x43104c STR X0, [SP, #736] |
0x431050 CMP X8, #2 |
0x431054 B.LT 431084 |
0x431058 ORR X0, XZR, X21 |
0x43105c MOVZ W1, #8 |
0x431060 BL 4a2570 |
0x431064 STR X0, [SP, #720] |
0x431068 CBZ X19, 432c2c |
0x43106c ORR X0, XZR, X19 |
0x431070 MOVZ W1, #8 |
0x431074 BL 4a2570 |
0x431078 ORR X8, XZR, X0 |
0x43107c LDR X0, [SP, #720] |
0x431080 B 432c30 |
0x431084 ORR X30, XZR, XZR |
0x431088 LDR X9, [SP, #752] |
0x43108c LDR X21, [SP, #424] |
0x431090 LDP X1, X8, [X9, #8] |
0x431094 CMP X1, X8 |
0x431098 STR X1, [SP, #560] |
0x43109c B.LT 432c84 |
(1540) 0x4310a0 ORR X10, XZR, XZR |
(1540) 0x4310a4 ORR X8, XZR, XZR |
(1540) 0x4310a8 LDR X9, [SP, #656] |
(1540) 0x4310ac STR X30, [SP, #432] |
(1540) 0x4310b0 ADD X9, X9, X10 |
(1540) 0x4310b4 STR X9, [SP, #656] |
(1540) 0x4310b8 LDR X9, [SP, #512] |
(1540) 0x4310bc ADD X8, X9, X8 |
(1540) 0x4310c0 STR X8, [SP, #512] |
(1540) 0x4310c4 LDR X8, [SP, #528] |
(1540) 0x4310c8 CMP X8, #1 |
(1540) 0x4310cc B.LE 4318ec |
(1540) 0x4310d0 MOVZ W0, #1 |
(1540) 0x4310d4 MOVZ W1, #112 |
(1540) 0x4310d8 BL 4a2570 |
(1540) 0x4310dc LDR X19, [SP, #640] |
(1540) 0x4310e0 STR X0, [SP, #392] |
(1540) 0x4310e4 MOVZ W1, #8 |
(1540) 0x4310e8 ORR X0, XZR, X19 |
(1540) 0x4310ec BL 4a2570 |
(1540) 0x4310f0 STR X0, [SP, #400] |
(1540) 0x4310f4 ORR X0, XZR, X19 |
(1540) 0x4310f8 MOVZ W1, #8 |
(1540) 0x4310fc BL 4a2570 |
(1540) 0x431100 STR X0, [SP, #408] |
(1540) 0x431104 ORR X0, XZR, X19 |
(1540) 0x431108 MOVZ W1, #8 |
(1540) 0x43110c BL 4a2570 |
(1540) 0x431110 LDUR X8, [X29, #384] |
(1540) 0x431114 STR X0, [SP, #712] |
(1540) 0x431118 MOVZ W1, #8 |
(1540) 0x43111c ADD X0, X8, #1 |
(1540) 0x431120 BL 4a2570 |
(1540) 0x431124 STR X0, [SP, #696] |
(1540) 0x431128 LDUR X0, [X29, #384] |
(1540) 0x43112c CBZ X0, 43113c |
(1540) 0x431130 MOVZ W1, #8 |
(1540) 0x431134 BL 4a2570 |
(1540) 0x431138 STUR X0, [X29, #304] |
(1540) 0x43113c LDP X8, X9, [X29, #832] |
(1540) 0x431140 LDR X0, [X8, X9,LSL #3] |
(1540) 0x431144 CBZ X0, 431154 |
(1540) 0x431148 MOVZ W1, #8 |
(1540) 0x43114c BL 4a2570 |
(1540) 0x431150 STUR X0, [X29, #296] |
(1540) 0x431154 ADRP X0, |
(1540) 0x431158 ADD X0, X0, #376 |
(1540) 0x43115c ADRP X2, 43315c |
(1540) 0x431160 ADD X2, X2, #416 |
(1540) 0x431164 SUB X3, X29, #128 |
(1540) 0x431168 ADD X4, SP, #696 |
(1540) 0x43116c MOVZ W1, #2 |
(1540) 0x431170 BL 40f670 |
(1540) 0x431174 ADRP X0, |
(1540) 0x431178 ADD X0, X0, #448 |
(1540) 0x43117c ADRP X2, 43317c |
(1540) 0x431180 ADD X2, X2, #672 |
(1540) 0x431184 SUB X3, X29, #192 |
(1540) 0x431188 SUB X4, X29, #184 |
(1540) 0x43118c SUB X5, X29, #216 |
(1540) 0x431190 MOVZ W1, #3 |
(1540) 0x431194 BL 40f670 |
(1540) 0x431198 LDR X30, [SP, #432] |
(1540) 0x43119c MOVZ W8, #2 |
(1540) 0x4311a0 CMP X19, #3 |
(1540) 0x4311a4 STR X8, [SP, #648] |
(1540) 0x4311a8 B.GE 431904 |
(1540) 0x4311ac ORR X20, XZR, XZR |
(1540) 0x4311b0 ORR X25, XZR, XZR |
(1540) 0x4311b4 ORR X0, XZR, X25 |
(1540) 0x4311b8 BL 4a2670 |
(1540) 0x4311bc LDUR X0, [X29, #296] |
(1540) 0x4311c0 BL 4a2670 |
(1540) 0x4311c4 ORR X0, XZR, X20 |
(1540) 0x4311c8 STUR XZR, [X29, #296] |
(1540) 0x4311cc BL 4a2670 |
(1540) 0x4311d0 LDR X0, [SP, #296] |
(1540) 0x4311d4 BL 4a2670 |
(1540) 0x4311d8 LDR X0, [SP, #448] |
(1540) 0x4311dc BL 4a2670 |
(1540) 0x4311e0 LDR X0, [SP, #440] |
(1540) 0x4311e4 STR XZR, [SP, #448] |
(1540) 0x4311e8 BL 4a2670 |
(1540) 0x4311ec LDR X0, [SP, #456] |
(1540) 0x4311f0 STR XZR, [SP, #440] |
(1540) 0x4311f4 BL 4a2670 |
(1540) 0x4311f8 LDR X0, [SP, #656] |
(1540) 0x4311fc MOVZ W1, #8 |
(1540) 0x431200 STR XZR, [SP, #456] |
(1540) 0x431204 BL 4a2570 |
(1540) 0x431208 STUR X0, [X29, #360] |
(1540) 0x43120c LDR X0, [SP, #656] |
(1540) 0x431210 MOVZ W1, #8 |
(1540) 0x431214 BL 4a2570 |
(1540) 0x431218 STUR X0, [X29, #376] |
(1540) 0x43121c LDR X0, [SP, #512] |
(1540) 0x431220 CBZ X0, 431240 |
(1540) 0x431224 MOVZ W1, #8 |
(1540) 0x431228 BL 4a2570 |
(1540) 0x43122c STUR X0, [X29, #336] |
(1540) 0x431230 LDR X0, [SP, #512] |
(1540) 0x431234 MOVZ W1, #8 |
(1540) 0x431238 BL 4a2570 |
(1540) 0x43123c STUR X0, [X29, #352] |
(1540) 0x431240 LDR X8, [SP, #632] |
(1540) 0x431244 LDR X25, [X29, #96] |
(1540) 0x431248 STR XZR, [SP, #560] |
(1540) 0x43124c CMP X8, #1 |
(1540) 0x431250 B.LT 4312a4 |
(1540) 0x431254 LDUR X8, [X29, #368] |
(1540) 0x431258 LDUR X9, [X29, #344] |
(1540) 0x43125c ORR X12, XZR, XZR |
(1540) 0x431260 ADD X10, X8, #8 |
(1540) 0x431264 ADD X11, X9, #8 |
(1562) 0x431268 LDR X13, [X8, X12,LSL #3] |
(1562) 0x43126c LDR X14, [X10, X12,LSL #3] |
(1562) 0x431270 ADD X13, X14, X13 |
(1562) 0x431274 STR X13, [X10, X12,LSL #3] |
(1562) 0x431278 LDR X12, [SP, #560] |
(1562) 0x43127c LDR X13, [X9, X12,LSL #3] |
(1562) 0x431280 LDR X14, [X11, X12,LSL #3] |
(1562) 0x431284 ADD X13, X14, X13 |
(1562) 0x431288 STR X13, [X11, X12,LSL #3] |
(1562) 0x43128c LDR X12, [SP, #560] |
(1562) 0x431290 LDR X13, [SP, #632] |
(1562) 0x431294 ADD X12, X12, #1 |
(1562) 0x431298 CMP X12, X13 |
(1562) 0x43129c STR X12, [SP, #560] |
(1562) 0x4312a0 B.LT 431268 |
(1540) 0x4312a4 SUB X21, X29, #136 |
(1540) 0x4312a8 ADRP X0, |
(1540) 0x4312ac ADD X0, X0, #712 |
(1540) 0x4312b0 ADRP X2, 4332b0 |
(1540) 0x4312b4 ADD X2, X2, #4000 |
(1540) 0x4312b8 STR X21, [SP] |
(1540) 0x4312bc ADD X3, SP, #624 |
(1540) 0x4312c0 SUB X4, X29, #248 |
(1540) 0x4312c4 SUB X5, X29, #152 |
(1540) 0x4312c8 SUB X6, X29, #144 |
(1540) 0x4312cc ADD X7, SP, #592 |
(1540) 0x4312d0 MOVZ W1, #6 |
(1540) 0x4312d4 SUB X20, X29, #248 |
(1540) 0x4312d8 SUB X22, X29, #152 |
(1540) 0x4312dc SUB X19, X29, #144 |
(1540) 0x4312e0 ADD X24, SP, #592 |
(1540) 0x4312e4 BL 40f670 |
(1540) 0x4312e8 LDR X8, [SP, #752] |
(1540) 0x4312ec LDP X8, X9, [X8, #8] |
(1540) 0x4312f0 SUB X8, X9, X8 |
(1540) 0x4312f4 SUB X9, X29, #176 |
(1540) 0x4312f8 STR X8, [SP, #464] |
(1540) 0x4312fc ADD X8, SP, #688 |
(1540) 0x431300 CBZ X25, 43216c |
(1540) 0x431304 STP X9, X8, [SP, #200] |
(1540) 0x431308 SUB X8, X29, #160 |
(1540) 0x43130c SUB X10, X29, #72 |
(1540) 0x431310 SUB X11, X29, #232 |
(1540) 0x431314 SUB X9, X29, #88 |
(1540) 0x431318 STP X21, X22, [SP, #80] |
(1540) 0x43131c STP X10, X8, [SP, #184] |
(1540) 0x431320 SUB X8, X29, #224 |
(1540) 0x431324 STR X9, [SP, #160] |
(1540) 0x431328 ADD X9, X29, #104 |
(1540) 0x43132c SUB X10, X29, #32 |
(1540) 0x431330 ADD X12, SP, #728 |
(1540) 0x431334 ADRP X0, |
(1540) 0x431338 ADD X0, X0, #736 |
(1540) 0x43133c STP X12, X20, [SP, #16] |
(1540) 0x431340 STP X8, X11, [SP, #168] |
(1540) 0x431344 ADD X8, SP, #680 |
(1540) 0x431348 SUB X11, X29, #56 |
(1540) 0x43134c ADRP X2, 43434c |
(1540) 0x431350 ADD X2, X2, #272 |
(1540) 0x431354 STP X9, X8, [SP, #144] |
(1540) 0x431358 SUB X8, X29, #80 |
(1540) 0x43135c SUB X9, X29, #256 |
(1540) 0x431360 STP X9, X8, [SP, #128] |
(1540) 0x431364 ADD X8, SP, #720 |
(1540) 0x431368 SUB X9, X29, #168 |
(1540) 0x43136c ADD X3, SP, #632 |
(1540) 0x431370 SUB X4, X29, #128 |
(1540) 0x431374 STP X9, X8, [SP, #112] |
(1540) 0x431378 ADD X8, SP, #736 |
(1540) 0x43137c SUB X9, X29, #40 |
(1540) 0x431380 ADD X5, SP, #752 |
(1540) 0x431384 ADD X6, SP, #464 |
(1540) 0x431388 STP X24, X8, [SP, #96] |
(1540) 0x43138c SUB X8, X29, #48 |
(1540) 0x431390 ADD X7, SP, #760 |
(1540) 0x431394 MOVZ W1, #32 |
(1540) 0x431398 STP X9, X8, [SP, #64] |
(1540) 0x43139c SUB X8, X29, #8 |
(1540) 0x4313a0 SUB X9, X29, #64 |
(1540) 0x4313a4 STP X8, X10, [SP, #48] |
(1540) 0x4313a8 ADD X8, SP, #744 |
(1540) 0x4313ac STP X11, X9, [SP, #32] |
(1540) 0x4313b0 STP X8, X19, [SP] |
(1540) 0x4313b4 BL 40f670 |
(1540) 0x4313b8 LDR X8, [SP, #624] |
(1540) 0x4313bc CBZ X8, 4313cc |
(1540) 0x4313c0 LDUR X0, [X29, #264] |
(1540) 0x4313c4 BL 4a2670 |
(1540) 0x4313c8 STUR XZR, [X29, #264] |
(1540) 0x4313cc LDUR X0, [X29, #256] |
(1540) 0x4313d0 BL 4a2670 |
(1540) 0x4313d4 LDR X8, [SP, #728] |
(1540) 0x4313d8 STUR XZR, [X29, #256] |
(1540) 0x4313dc LDR X0, [X8, #8] |
(1540) 0x4313e0 BL 4a2670 |
(1540) 0x4313e4 LDR X8, [SP, #728] |
(1540) 0x4313e8 STR XZR, [X8, #8] |
(1540) 0x4313ec LDR X8, [SP, #528] |
(1540) 0x4313f0 CMP X8, #2 |
(1540) 0x4313f4 B.LT 43140c |
(1540) 0x4313f8 LDR X8, [SP, #720] |
(1540) 0x4313fc LDR X0, [X8, #8] |
(1540) 0x431400 BL 4a2670 |
(1540) 0x431404 LDR X8, [SP, #720] |
(1540) 0x431408 STR XZR, [X8, #8] |
(1540) 0x43140c LDR X24, [SP, #640] |
(1540) 0x431410 MOVZ W8, #2 |
(1540) 0x431414 STR X8, [SP, #648] |
(1540) 0x431418 CMP X24, #2 |
(1540) 0x43141c B.LE 43274c |
(1540) 0x431420 ORR X25, XZR, XZR |
(1540) 0x431424 ORR X27, XZR, XZR |
(1540) 0x431428 MOVZ W8, #2 |
(1540) 0x43142c SUB X23, X29, #232 |
(1540) 0x431430 ADD X26, SP, #752 |
(1540) 0x431434 ORR X19, XZR, XZR |
(1540) 0x431438 ADRP X20, |
(1540) 0x43143c ADD X20, X20, #760 |
(1540) 0x431440 ADRP X21, 434440 |
(1540) 0x431444 ADD X21, X21, #2448 |
(1540) 0x431448 B 43145c |
(1555) 0x43144c ADD X8, X8, #1 |
(1555) 0x431450 CMP X8, X24 |
(1555) 0x431454 STR X8, [SP, #648] |
(1555) 0x431458 B.GE 432750 |
(1555) 0x43145c LDR X9, [SP, #528] |
(1555) 0x431460 CMP X9, #2 |
(1555) 0x431464 B.LT 431740 |
(1555) 0x431468 LDR X9, [SP, #400] |
(1555) 0x43146c LDR X9, [X9, X8,LSL #3] |
(1555) 0x431470 LDUR X8, [X29, #328] |
(1555) 0x431474 LDR X9, [X9, X8,LSL #3] |
(1555) 0x431478 CMP X9, X27 |
(1555) 0x43147c STR X9, [SP, #504] |
(1555) 0x431480 B.LE 4314c0 |
(1555) 0x431484 ORR X0, XZR, X19 |
(1555) 0x431488 BL 4a2670 |
(1555) 0x43148c LDR X0, [SP, #504] |
(1555) 0x431490 MOVZ W1, #8 |
(1555) 0x431494 BL 4a2570 |
(1555) 0x431498 LDR X27, [SP, #504] |
(1555) 0x43149c LDUR X8, [X29, #328] |
(1555) 0x4314a0 ORR X19, XZR, X0 |
(1555) 0x4314a4 CMP X8, #1 |
(1555) 0x4314a8 STR XZR, [SP, #560] |
(1555) 0x4314ac B.GE 4314d0 |
(1555) 0x4314b0 B 4316a4 |
0x4314b4 HINT #0 |
0x4314b8 HINT #0 |
0x4314bc HINT #0 |
(1555) 0x4314c0 ORR X27, XZR, X9 |
(1555) 0x4314c4 CMP X8, #1 |
(1555) 0x4314c8 STR XZR, [SP, #560] |
(1555) 0x4314cc B.LT 4316a4 |
(1555) 0x4314d0 LDR X13, [SP, #648] |
(1555) 0x4314d4 LDP X11, X10, [X29, #824] |
(1555) 0x4314d8 LDR X12, [SP, #584] |
(1555) 0x4314dc ORR X15, XZR, XZR |
(1555) 0x4314e0 ORR X9, XZR, XZR |
(1555) 0x4314e4 ADD X14, X19, #16 |
(1555) 0x4314e8 SUB X13, X13, #1 |
(1555) 0x4314ec B 43150c |
0x4314f0 HINT #0 |
0x4314f4 HINT #0 |
0x4314f8 HINT #0 |
0x4314fc HINT #0 |
(1556) 0x431500 CMP X9, X8 |
(1556) 0x431504 STR X9, [SP, #560] |
(1556) 0x431508 B.EQ 4316a4 |
(1556) 0x43150c LDR X16, [X10, X9,LSL #3] |
(1556) 0x431510 ADD X9, X9, #1 |
(1556) 0x431514 LDR X17, [X10, X9,LSL #3] |
(1556) 0x431518 CMP X16, X17 |
(1556) 0x43151c B.GE 431500 |
(1556) 0x431520 LDP X18, X0, [X29, #880] |
(1556) 0x431524 LDP X1, X2, [X29, #856] |
(1556) 0x431528 ADD X3, X0, #16 |
(1556) 0x43152c ADD X4, X2, #16 |
(1556) 0x431530 B 43154c |
0x431534 HINT #0 |
0x431538 HINT #0 |
0x43153c HINT #0 |
(1557) 0x431540 ADD X16, X16, #1 |
(1557) 0x431544 CMP X16, X17 |
(1557) 0x431548 B.EQ 431500 |
(1557) 0x43154c LDR X5, [X11, X16,LSL #3] |
(1557) 0x431550 LDR X6, [X12, X5,LSL #3] |
(1557) 0x431554 CMP X6, X13 |
(1557) 0x431558 B.NE 431540 |
(1557) 0x43155c ADD X6, X5, #1 |
(1557) 0x431560 LDR X22, [X18, X5,LSL #3] |
(1557) 0x431564 LDR X7, [X18, X6,LSL #3] |
(1557) 0x431568 CMP X7, X22 |
(1557) 0x43156c B.LE 431600 |
(1557) 0x431570 SUB W28, W7, W22 |
(1557) 0x431574 ANDS X30, X28, #4160 |
(1557) 0x431578 B.EQ 4315ac |
(1557) 0x43157c ORR X28, XZR, X22 |
(1561) 0x431580 LDR D0, [X0, X28,LSL #3] |
(1561) 0x431584 ADD X28, X28, #1 |
(1561) 0x431588 SUBS X30, X30, #1 |
(1561) 0x43158c STR D0, [X19, X15,LSL #3] |
(1561) 0x431590 ADD X15, X15, #1 |
(1561) 0x431594 B.NE 431580 |
(1557) 0x431598 ORN X22, XZR, X22 |
(1557) 0x43159c ADD X22, X7, X22 |
(1557) 0x4315a0 CMP X22, #3 |
(1557) 0x4315a4 B.CS 4315c0 |
(1557) 0x4315a8 B 431600 |
(1557) 0x4315ac ORR X28, XZR, X22 |
(1557) 0x4315b0 ORN X22, XZR, X22 |
(1557) 0x4315b4 ADD X22, X7, X22 |
(1557) 0x4315b8 CMP X22, #3 |
(1557) 0x4315bc B.CC 431600 |
(1557) 0x4315c0 SUB X7, X7, X28 |
(1557) 0x4315c4 ADD X22, X3, X28,LSL #3 |
(1557) 0x4315c8 ADD X28, X14, X15,LSL #3 |
(1560) 0x4315cc LDUR D0, [X22, #496] |
(1560) 0x4315d0 ADD X15, X15, #4 |
(1560) 0x4315d4 SUBS X7, X7, #4 |
(1560) 0x4315d8 STUR D0, [X28, #496] |
(1560) 0x4315dc LDUR D0, [X22, #504] |
(1560) 0x4315e0 STUR D0, [X28, #504] |
(1560) 0x4315e4 LDR D0, [X22] |
(1560) 0x4315e8 STR D0, [X28] |
(1560) 0x4315ec LDR D0, [X22, #8] |
(1560) 0x4315f0 ADD X22, X22, #32 |
(1560) 0x4315f4 STR D0, [X28, #8] |
(1560) 0x4315f8 ADD X28, X28, #32 |
(1560) 0x4315fc B.NE 4315cc |
(1557) 0x431600 LDR X7, [X1, X5,LSL #3] |
(1557) 0x431604 LDR X5, [X1, X6,LSL #3] |
(1557) 0x431608 CMP X5, X7 |
(1557) 0x43160c B.LE 431540 |
(1557) 0x431610 SUB W6, W5, W7 |
(1557) 0x431614 ANDS X22, X6, #4160 |
(1557) 0x431618 B.EQ 43164c |
(1557) 0x43161c ORR X6, XZR, X7 |
(1559) 0x431620 LDR D0, [X2, X6,LSL #3] |
(1559) 0x431624 ADD X6, X6, #1 |
(1559) 0x431628 SUBS X22, X22, #1 |
(1559) 0x43162c STR D0, [X19, X15,LSL #3] |
(1559) 0x431630 ADD X15, X15, #1 |
(1559) 0x431634 B.NE 431620 |
(1557) 0x431638 ORN X7, XZR, X7 |
(1557) 0x43163c ADD X7, X5, X7 |
(1557) 0x431640 CMP X7, #3 |
(1557) 0x431644 B.CC 431540 |
(1557) 0x431648 B 431660 |
(1557) 0x43164c ORR X6, XZR, X7 |
(1557) 0x431650 ORN X7, XZR, X7 |
(1557) 0x431654 ADD X7, X5, X7 |
(1557) 0x431658 CMP X7, #3 |
(1557) 0x43165c B.CC 431540 |
(1557) 0x431660 SUB X5, X5, X6 |
(1557) 0x431664 ADD X6, X4, X6,LSL #3 |
(1557) 0x431668 ADD X7, X14, X15,LSL #3 |
(1558) 0x43166c LDUR D0, [X6, #496] |
(1558) 0x431670 ADD X15, X15, #4 |
(1558) 0x431674 SUBS X5, X5, #4 |
(1558) 0x431678 STUR D0, [X7, #496] |
(1558) 0x43167c LDUR D0, [X6, #504] |
(1558) 0x431680 STUR D0, [X7, #504] |
(1558) 0x431684 LDR D0, [X6] |
(1558) 0x431688 STR D0, [X7] |
(1558) 0x43168c LDR D0, [X6, #8] |
(1558) 0x431690 ADD X6, X6, #32 |
(1558) 0x431694 STR D0, [X7, #8] |
(1558) 0x431698 ADD X7, X7, #32 |
(1558) 0x43169c B.NE 43166c |
(1557) 0x4316a0 B 431540 |
(1555) 0x4316a4 LDP X11, X9, [SP, #392] |
(1555) 0x4316a8 LDP X12, X10, [SP, #408] |
(1555) 0x4316ac LDR X3, [SP, #568] |
(1555) 0x4316b0 STR X8, [X11, #8] |
(1555) 0x4316b4 LDR X8, [SP, #648] |
(1555) 0x4316b8 LDR X9, [X9, X8,LSL #3] |
(1555) 0x4316bc STR X10, [X11, #40] |
(1555) 0x4316c0 STR X9, [X11, #24] |
(1555) 0x4316c4 LDR X9, [X12, X8,LSL #3] |
(1555) 0x4316c8 STR X9, [X11, #56] |
(1555) 0x4316cc LDR X8, [X12, X8,LSL #3] |
(1555) 0x4316d0 LDR X22, [X8, X10,LSL #3] |
(1555) 0x4316d4 CMP X22, X25 |
(1555) 0x4316d8 B.LE 4316fc |
(1555) 0x4316dc ORR X0, XZR, X3 |
(1555) 0x4316e0 BL 4a2670 |
(1555) 0x4316e4 ORR X0, XZR, X22 |
(1555) 0x4316e8 MOVZ W1, #8 |
(1555) 0x4316ec STR XZR, [SP, #568] |
(1555) 0x4316f0 BL 4a2570 |
(1555) 0x4316f4 ORR X3, XZR, X0 |
(1555) 0x4316f8 STR X0, [SP, #568] |
(1555) 0x4316fc LDR X1, [SP, #392] |
(1555) 0x431700 ORR X2, XZR, X19 |
(1555) 0x431704 MOVZ W0, #1 |
(1555) 0x431708 BL 47cbc0 |
(1555) 0x43170c BL 47cfa0 |
(1555) 0x431710 LDR X8, [SP, #648] |
(1555) 0x431714 LDR X25, [SP, #400] |
(1555) 0x431718 LDR X0, [X25, X8,LSL #3] |
(1555) 0x43171c BL 4a2670 |
(1555) 0x431720 LDR X8, [SP, #648] |
(1555) 0x431724 STR XZR, [X25, X8,LSL #3] |
(1555) 0x431728 LDR X25, [SP, #408] |
(1555) 0x43172c LDR X0, [X25, X8,LSL #3] |
(1555) 0x431730 BL 4a2670 |
(1555) 0x431734 LDR X8, [SP, #648] |
(1555) 0x431738 STR XZR, [X25, X8,LSL #3] |
(1555) 0x43173c ORR X25, XZR, X22 |
(1555) 0x431740 LDR X9, [SP, #752] |
(1555) 0x431744 ORR X0, XZR, X20 |
(1555) 0x431748 ORR X2, XZR, X21 |
(1555) 0x43174c ADD X3, SP, #632 |
(1555) 0x431750 SUB X4, X29, #128 |
(1555) 0x431754 ADD X5, SP, #624 |
(1555) 0x431758 ADD X6, SP, #480 |
(1555) 0x43175c ADD X7, SP, #616 |
(1555) 0x431760 MOVZ W1, #42 |
(1555) 0x431764 ADD X8, X9, X8,LSL #3 |
(1555) 0x431768 LDP X8, X9, [X8] |
(1555) 0x43176c SUB X8, X9, X8 |
(1555) 0x431770 STR X8, [SP, #464] |
(1555) 0x431774 SUB X8, X29, #224 |
(1555) 0x431778 STP X8, X23, [SP, #280] |
(1555) 0x43177c ADD X8, SP, #568 |
(1555) 0x431780 STR X8, [SP, #272] |
(1555) 0x431784 SUB X8, X29, #72 |
(1555) 0x431788 STR X8, [SP, #264] |
(1555) 0x43178c ADD X8, SP, #712 |
(1555) 0x431790 STR X8, [SP, #256] |
(1555) 0x431794 ADD X8, SP, #696 |
(1555) 0x431798 STR X8, [SP, #248] |
(1555) 0x43179c SUB X8, X29, #208 |
(1555) 0x4317a0 STR X8, [SP, #240] |
(1555) 0x4317a4 SUB X8, X29, #88 |
(1555) 0x4317a8 STR X8, [SP, #232] |
(1555) 0x4317ac ADD X8, SP, #680 |
(1555) 0x4317b0 STR X8, [SP, #224] |
(1555) 0x4317b4 ADD X8, X29, #104 |
(1555) 0x4317b8 STR X8, [SP, #216] |
(1555) 0x4317bc SUB X8, X29, #80 |
(1555) 0x4317c0 STR X8, [SP, #208] |
(1555) 0x4317c4 SUB X8, X29, #40 |
(1555) 0x4317c8 STR X8, [SP, #200] |
(1555) 0x4317cc SUB X8, X29, #32 |
(1555) 0x4317d0 STR X8, [SP, #192] |
(1555) 0x4317d4 SUB X8, X29, #8 |
(1555) 0x4317d8 STR X8, [SP, #184] |
(1555) 0x4317dc SUB X8, X29, #48 |
(1555) 0x4317e0 STR X8, [SP, #176] |
(1555) 0x4317e4 SUB X8, X29, #64 |
(1555) 0x4317e8 STR X8, [SP, #168] |
(1555) 0x4317ec SUB X8, X29, #56 |
(1555) 0x4317f0 STR X8, [SP, #160] |
(1555) 0x4317f4 ADD X8, SP, #576 |
(1555) 0x4317f8 STR X8, [SP, #152] |
(1555) 0x4317fc SUB X8, X29, #120 |
(1555) 0x431800 STR X8, [SP, #144] |
(1555) 0x431804 SUB X8, X29, #112 |
(1555) 0x431808 STR X8, [SP, #136] |
(1555) 0x43180c ADD X8, SP, #584 |
(1555) 0x431810 STR X8, [SP, #128] |
(1555) 0x431814 SUB X8, X29, #104 |
(1555) 0x431818 STR X8, [SP, #120] |
(1555) 0x43181c SUB X8, X29, #96 |
(1555) 0x431820 STR X8, [SP, #112] |
(1555) 0x431824 SUB X8, X29, #176 |
(1555) 0x431828 STR X8, [SP, #104] |
(1555) 0x43182c SUB X8, X29, #160 |
(1555) 0x431830 STR X8, [SP, #96] |
(1555) 0x431834 ADD X8, SP, #720 |
(1555) 0x431838 STR X8, [SP, #88] |
(1555) 0x43183c SUB X8, X29, #168 |
(1555) 0x431840 STR X8, [SP, #80] |
(1555) 0x431844 ADD X8, SP, #736 |
(1555) 0x431848 STR X8, [SP, #72] |
(1555) 0x43184c SUB X8, X29, #152 |
(1555) 0x431850 STR X8, [SP, #64] |
(1555) 0x431854 SUB X8, X29, #136 |
(1555) 0x431858 STR X8, [SP, #56] |
(1555) 0x43185c ADD X8, SP, #728 |
(1555) 0x431860 STR X8, [SP, #48] |
(1555) 0x431864 SUB X8, X29, #144 |
(1555) 0x431868 STR X8, [SP, #40] |
(1555) 0x43186c ADD X8, SP, #744 |
(1555) 0x431870 STR X8, [SP, #32] |
(1555) 0x431874 ADD X8, SP, #760 |
(1555) 0x431878 STR X8, [SP, #24] |
(1555) 0x43187c ADD X8, SP, #464 |
(1555) 0x431880 STR X8, [SP, #16] |
(1555) 0x431884 ADD X8, SP, #648 |
(1555) 0x431888 STP X26, X8, [SP] |
(1555) 0x43188c BL 40f670 |
(1555) 0x431890 LDR X8, [SP, #728] |
(1555) 0x431894 LDR X9, [SP, #648] |
(1555) 0x431898 LDR X0, [X8, X9,LSL #3] |
(1555) 0x43189c BL 4a2670 |
(1555) 0x4318a0 LDR X9, [SP, #728] |
(1555) 0x4318a4 LDR X8, [SP, #648] |
(1555) 0x4318a8 STR XZR, [X9, X8,LSL #3] |
(1555) 0x4318ac LDR X9, [SP, #528] |
(1555) 0x4318b0 CMP X9, #2 |
(1555) 0x4318b4 B.LT 43144c |
(1555) 0x4318b8 LDR X9, [SP, #720] |
(1555) 0x4318bc LDR X0, [X9, X8,LSL #3] |
(1555) 0x4318c0 BL 4a2670 |
(1555) 0x4318c4 LDR X8, [SP, #720] |
(1555) 0x4318c8 LDR X9, [SP, #648] |
(1555) 0x4318cc STR XZR, [X8, X9,LSL #3] |
(1555) 0x4318d0 LDR X8, [SP, #712] |
(1555) 0x4318d4 LDR X0, [X8, X9,LSL #3] |
(1555) 0x4318d8 BL 4a2670 |
(1555) 0x4318dc LDR X9, [SP, #712] |
(1555) 0x4318e0 LDR X8, [SP, #648] |
(1555) 0x4318e4 STR XZR, [X9, X8,LSL #3] |
(1555) 0x4318e8 B 43144c |
(1540) 0x4318ec LDR X19, [SP, #640] |
(1540) 0x4318f0 STP XZR, XZR, [SP, #400] |
(1540) 0x4318f4 MOVZ W8, #2 |
(1540) 0x4318f8 CMP X19, #3 |
(1540) 0x4318fc STR X8, [SP, #648] |
(1540) 0x431900 B.LT 4311ac |
(1540) 0x431904 LDR X19, [SP, #400] |
(1540) 0x431908 ORR X25, XZR, XZR |
(1540) 0x43190c ORR X20, XZR, XZR |
(1540) 0x431910 SUB X22, X30, #8 |
(1540) 0x431914 SUB X23, X29, #168 |
(1540) 0x431918 SUB X26, X29, #144 |
(1540) 0x43191c STP XZR, XZR, [SP, #360] |
(1540) 0x431920 STR X22, [SP, #352] |
(1540) 0x431924 B 431a38 |
(1563) 0x431928 LDR X8, [SP, #752] |
(1563) 0x43192c LDR X9, [SP, #648] |
(1563) 0x431930 ADD X3, SP, #464 |
(1563) 0x431934 ADD X4, SP, #752 |
(1563) 0x431938 ADD X5, SP, #648 |
(1563) 0x43193c ADD X6, SP, #624 |
(1563) 0x431940 ADD X7, SP, #480 |
(1563) 0x431944 ADRP X0, |
(1563) 0x431948 ADD X0, X0, #640 |
(1563) 0x43194c MOVZ W1, #29 |
(1563) 0x431950 ADRP X2, 433950 |
(1563) 0x431954 ADD X2, X2, #1424 |
(1563) 0x431958 ADD X8, X8, X9,LSL #3 |
(1563) 0x43195c LDP X8, X9, [X8] |
(1563) 0x431960 SUB X8, X9, X8 |
(1563) 0x431964 STR X8, [SP, #464] |
(1563) 0x431968 ADD X8, SP, #528 |
(1563) 0x43196c STR X8, [SP, #184] |
(1563) 0x431970 ADD X8, SP, #512 |
(1563) 0x431974 STR X8, [SP, #176] |
(1563) 0x431978 ADD X8, SP, #656 |
(1563) 0x43197c STR X8, [SP, #168] |
(1563) 0x431980 ADD X8, SP, #448 |
(1563) 0x431984 STR X8, [SP, #160] |
(1563) 0x431988 ADD X8, SP, #440 |
(1563) 0x43198c STR X8, [SP, #152] |
(1563) 0x431990 ADD X8, SP, #456 |
(1563) 0x431994 STR X8, [SP, #144] |
(1563) 0x431998 ADD X8, SP, #712 |
(1563) 0x43199c STR X8, [SP, #136] |
(1563) 0x4319a0 ADD X8, SP, #696 |
(1563) 0x4319a4 STR X8, [SP, #128] |
(1563) 0x4319a8 SUB X8, X29, #208 |
(1563) 0x4319ac STR X8, [SP, #120] |
(1563) 0x4319b0 ADD X8, SP, #576 |
(1563) 0x4319b4 STR X8, [SP, #112] |
(1563) 0x4319b8 SUB X8, X29, #120 |
(1563) 0x4319bc STR X8, [SP, #104] |
(1563) 0x4319c0 SUB X8, X29, #112 |
(1563) 0x4319c4 STR X8, [SP, #96] |
(1563) 0x4319c8 ADD X8, SP, #720 |
(1563) 0x4319cc STP X23, X8, [SP, #80] |
(1563) 0x4319d0 ADD X8, SP, #728 |
(1563) 0x4319d4 STP X26, X8, [SP, #64] |
(1563) 0x4319d8 ADD X8, SP, #584 |
(1563) 0x4319dc STR X8, [SP, #56] |
(1563) 0x4319e0 SUB X8, X29, #104 |
(1563) 0x4319e4 STR X8, [SP, #48] |
(1563) 0x4319e8 SUB X8, X29, #96 |
(1563) 0x4319ec STR X8, [SP, #40] |
(1563) 0x4319f0 ADD X8, SP, #736 |
(1563) 0x4319f4 STR X8, [SP, #32] |
(1563) 0x4319f8 ADD X8, SP, #744 |
(1563) 0x4319fc STR X8, [SP, #24] |
(1563) 0x431a00 ADD X8, SP, #760 |
(1563) 0x431a04 STR X8, [SP, #16] |
(1563) 0x431a08 ADD X8, SP, #616 |
(1563) 0x431a0c STR X8, [SP, #8] |
(1563) 0x431a10 ADD X8, SP, #488 |
(1563) 0x431a14 STR X8, [SP] |
(1563) 0x431a18 BL 40f670 |
(1563) 0x431a1c LDR X8, [SP, #648] |
(1563) 0x431a20 LDR X9, [SP, #640] |
(1563) 0x431a24 LDR X30, [SP, #432] |
(1563) 0x431a28 ADD X8, X8, #1 |
(1563) 0x431a2c CMP X8, X9 |
(1563) 0x431a30 STR X8, [SP, #648] |
(1563) 0x431a34 B.GE 4311b4 |
(1563) 0x431a38 LDR X8, [SP, #528] |
(1563) 0x431a3c CMP X8, #1 |
(1563) 0x431a40 B.LE 431b60 |
(1563) 0x431a44 LDUR X8, [X29, #328] |
(1563) 0x431a48 MOVZ W1, #8 |
(1563) 0x431a4c ADD X0, X8, #1 |
(1563) 0x431a50 BL 4a2570 |
(1563) 0x431a54 LDR X8, [SP, #648] |
(1563) 0x431a58 MOVZ W1, #8 |
(1563) 0x431a5c STR X0, [X19, X8,LSL #3] |
(1563) 0x431a60 LDR X0, [SP, #344] |
(1563) 0x431a64 BL 4a2570 |
(1563) 0x431a68 LDR X8, [SP, #648] |
(1563) 0x431a6c LDR X9, [SP, #408] |
(1563) 0x431a70 STR X0, [X9, X8,LSL #3] |
(1563) 0x431a74 STR XZR, [SP, #504] |
(1563) 0x431a78 LDR X8, [X19, X8,LSL #3] |
(1563) 0x431a7c STR XZR, [X8] |
(1563) 0x431a80 STR XZR, [SP, #560] |
(1563) 0x431a84 LDUR X8, [X29, #328] |
(1563) 0x431a88 CMP X8, #1 |
(1563) 0x431a8c B.LT 431b08 |
(1563) 0x431a90 ADRP X26, 433a90 |
(1563) 0x431a94 ADD X26, X26, #960 |
(1563) 0x431a98 ADD X28, SP, #504 |
(1563) 0x431a9c SUB X24, X29, #168 |
(1563) 0x431aa0 SUB X23, X29, #144 |
(1575) 0x431aa4 ORR X2, XZR, X26 |
(1575) 0x431aa8 SUB X3, X29, #192 |
(1575) 0x431aac ADD X4, SP, #560 |
(1575) 0x431ab0 SUB X5, X29, #200 |
(1575) 0x431ab4 STP X24, X28, [SP, #16] |
(1575) 0x431ab8 ADD X6, SP, #584 |
(1575) 0x431abc ADD X7, SP, #648 |
(1575) 0x431ac0 SUB X8, X29, #216 |
(1575) 0x431ac4 ADRP X0, |
(1575) 0x431ac8 ADD X0, X0, #544 |
(1575) 0x431acc STP X8, X23, [SP] |
(1575) 0x431ad0 MOVZ W1, #9 |
(1575) 0x431ad4 BL 40f670 |
(1575) 0x431ad8 LDR X9, [SP, #648] |
(1575) 0x431adc LDR X10, [SP, #560] |
(1575) 0x431ae0 LDR X8, [SP, #504] |
(1575) 0x431ae4 LDR X9, [X19, X9,LSL #3] |
(1575) 0x431ae8 ADD X9, X9, X10,LSL #3 |
(1575) 0x431aec STR X8, [X9, #8] |
(1575) 0x431af0 LDR X8, [SP, #560] |
(1575) 0x431af4 LDUR X9, [X29, #328] |
(1575) 0x431af8 ADD X8, X8, #1 |
(1575) 0x431afc CMP X8, X9 |
(1575) 0x431b00 STR X8, [SP, #560] |
(1575) 0x431b04 B.LT 431aa4 |
(1563) 0x431b08 LDR X8, [SP, #696] |
(1563) 0x431b0c LDUR X2, [X29, #296] |
(1563) 0x431b10 LDR X1, [SP, #376] |
(1563) 0x431b14 MOVZ W0, #11 |
(1563) 0x431b18 ADD X3, X8, #8 |
(1563) 0x431b1c BL 47cbc0 |
(1563) 0x431b20 BL 47cfa0 |
(1563) 0x431b24 LDR X8, [SP, #504] |
(1563) 0x431b28 LDR X9, [SP, #368] |
(1563) 0x431b2c CMP X8, X9 |
(1563) 0x431b30 B.LE 431b50 |
(1563) 0x431b34 ORR X0, XZR, X20 |
(1563) 0x431b38 BL 4a2670 |
(1563) 0x431b3c LDR X0, [SP, #504] |
(1563) 0x431b40 MOVZ W1, #8 |
(1563) 0x431b44 BL 4a2570 |
(1563) 0x431b48 LDR X8, [SP, #504] |
(1563) 0x431b4c ORR X20, XZR, X0 |
(1563) 0x431b50 LDR X30, [SP, #432] |
(1563) 0x431b54 SUB X23, X29, #168 |
(1563) 0x431b58 SUB X26, X29, #144 |
(1563) 0x431b5c STR X8, [SP, #368] |
(1563) 0x431b60 LDUR X13, [X29, #328] |
(1563) 0x431b64 STR XZR, [SP, #560] |
(1563) 0x431b68 CMP X13, #1 |
(1563) 0x431b6c B.LT 431ce0 |
(1563) 0x431b70 LDP X9, X8, [X29, #824] |
(1563) 0x431b74 LDR X11, [SP, #584] |
(1563) 0x431b78 ORR X10, XZR, XZR |
(1563) 0x431b7c ORR X0, XZR, XZR |
(1563) 0x431b80 B 431b94 |
(1570) 0x431b84 LDUR X13, [X29, #328] |
(1570) 0x431b88 CMP X0, X13 |
(1570) 0x431b8c STR X0, [SP, #560] |
(1570) 0x431b90 B.GE 431ce0 |
(1570) 0x431b94 LDR X12, [X8, X0,LSL #3] |
(1570) 0x431b98 ADD X0, X0, #1 |
(1570) 0x431b9c LDR X14, [X8, X0,LSL #3] |
(1570) 0x431ba0 CMP X12, X14 |
(1570) 0x431ba4 B.GE 431b88 |
(1570) 0x431ba8 LDR X18, [SP, #728] |
(1570) 0x431bac LDR X13, [SP, #744] |
(1570) 0x431bb0 LDUR X14, [X29, #368] |
(1570) 0x431bb4 SUB X18, X18, #8 |
(1570) 0x431bb8 LDR X15, [SP, #736] |
(1570) 0x431bbc LDUR X16, [X29, #344] |
(1570) 0x431bc0 LDR X17, [SP, #720] |
(1570) 0x431bc4 B 431be0 |
(1571) 0x431bc8 LDR X0, [SP, #560] |
(1571) 0x431bcc ADD X12, X12, #1 |
(1571) 0x431bd0 ADD X0, X0, #1 |
(1571) 0x431bd4 LDR X1, [X8, X0,LSL #3] |
(1571) 0x431bd8 CMP X12, X1 |
(1571) 0x431bdc B.GE 431b84 |
(1571) 0x431be0 LDR X0, [X9, X12,LSL #3] |
(1571) 0x431be4 LDR X2, [SP, #648] |
(1571) 0x431be8 LDR X1, [X11, X0,LSL #3] |
(1571) 0x431bec SUB X2, X2, #1 |
(1571) 0x431bf0 CMP X1, X2 |
(1571) 0x431bf4 B.NE 431bc8 |
(1571) 0x431bf8 ADD X1, X0, #1 |
(1571) 0x431bfc LDR X3, [X14, X1,LSL #3] |
(1571) 0x431c00 CMP X3, #1 |
(1571) 0x431c04 B.LT 431c44 |
(1571) 0x431c08 LDR X2, [X13, X0,LSL #3] |
(1571) 0x431c0c ADD X3, X3, X2 |
(1571) 0x431c10 HINT #0 |
(1571) 0x431c14 HINT #0 |
(1571) 0x431c18 HINT #0 |
(1571) 0x431c1c HINT #0 |
(1574) 0x431c20 LDR X4, [SP, #648] |
(1574) 0x431c24 LDR X4, [X18, X4,LSL #3] |
(1574) 0x431c28 LDR X4, [X4, X2,LSL #3] |
(1574) 0x431c2c ADD X2, X2, #1 |
(1574) 0x431c30 CMP X2, X3 |
(1574) 0x431c34 ADD X4, X4, X27 |
(1574) 0x431c38 STR X4, [X20, X10,LSL #3] |
(1574) 0x431c3c ADD X10, X10, #1 |
(1574) 0x431c40 B.LT 431c20 |
(1571) 0x431c44 LDR X1, [X16, X1,LSL #3] |
(1571) 0x431c48 CMP X1, #1 |
(1571) 0x431c4c B.LT 431bc8 |
(1571) 0x431c50 LDR X0, [X15, X0,LSL #3] |
(1571) 0x431c54 ADD X1, X1, X0 |
(1571) 0x431c58 B 431c6c |
0x431c5c HINT #0 |
(1572) 0x431c60 ADD X0, X0, #1 |
(1572) 0x431c64 CMP X0, X1 |
(1572) 0x431c68 B.GE 431bc8 |
(1572) 0x431c6c LDR X2, [SP, #648] |
(1572) 0x431c70 LDR X4, [SP, #704] |
(1572) 0x431c74 ORR X5, XZR, X22 |
(1572) 0x431c78 SUB X3, X2, #1 |
(1572) 0x431c7c ADD X4, X4, #8 |
(1572) 0x431c80 LDR X2, [X17, X3,LSL #3] |
(1572) 0x431c84 CMP X3, #0 |
(1572) 0x431c88 CSEL X3, X3, XZR, #12 |
(1572) 0x431c8c LDR X2, [X2, X0,LSL #3] |
(1572) 0x431c90 HINT #0 |
(1572) 0x431c94 HINT #0 |
(1572) 0x431c98 HINT #0 |
(1572) 0x431c9c HINT #0 |
(1573) 0x431ca0 CBZ X3, 431c60 |
(1573) 0x431ca4 LDR X6, [X4], #8 |
(1573) 0x431ca8 ADD X5, X5, #8 |
(1573) 0x431cac SUB X3, X3, #1 |
(1573) 0x431cb0 CMP X2, X6 |
(1573) 0x431cb4 B.GE 431ca0 |
(1572) 0x431cb8 LDUR X3, [X4, #496] |
(1572) 0x431cbc SUB X2, X2, X3 |
(1572) 0x431cc0 LDR X3, [X5] |
(1572) 0x431cc4 LDR X2, [X3, X2,LSL #3] |
(1572) 0x431cc8 STR X2, [X20, X10,LSL #3] |
(1572) 0x431ccc ADD X10, X10, #1 |
(1572) 0x431cd0 B 431c60 |
0x431cd4 HINT #0 |
0x431cd8 HINT #0 |
0x431cdc HINT #0 |
(1563) 0x431ce0 LDR X8, [SP, #528] |
(1563) 0x431ce4 CMP X8, #1 |
(1563) 0x431ce8 B.LE 431e6c |
(1563) 0x431cec LDR X8, [SP, #648] |
(1563) 0x431cf0 LDR X9, [SP, #408] |
(1563) 0x431cf4 LDR X8, [X9, X8,LSL #3] |
(1563) 0x431cf8 STR XZR, [X8] |
(1563) 0x431cfc LDR X8, [SP, #416] |
(1563) 0x431d00 STR XZR, [SP, #560] |
(1563) 0x431d04 CMP X8, #1 |
(1563) 0x431d08 B.LT 431da8 |
(1563) 0x431d0c LDR X8, [SP, #576] |
(1563) 0x431d10 ORR X24, XZR, XZR |
(1563) 0x431d14 ORR X9, XZR, XZR |
(1563) 0x431d18 B 431d48 |
0x431d1c HINT #0 |
(1568) 0x431d20 LDR X9, [SP, #648] |
(1568) 0x431d24 LDR X10, [SP, #408] |
(1568) 0x431d28 LDR X9, [X10, X9,LSL #3] |
(1568) 0x431d2c LDR X10, [SP, #416] |
(1568) 0x431d30 STR X24, [X9, X13,LSL #3] |
(1568) 0x431d34 LDR X9, [SP, #560] |
(1568) 0x431d38 ADD X9, X9, #1 |
(1568) 0x431d3c CMP X9, X10 |
(1568) 0x431d40 STR X9, [SP, #560] |
(1568) 0x431d44 B.GE 431dac |
(1568) 0x431d48 ADD X13, X9, #1 |
(1568) 0x431d4c LDR X10, [X21, X9,LSL #3] |
(1568) 0x431d50 LDR X11, [X21, X13,LSL #3] |
(1568) 0x431d54 CMP X10, X11 |
(1568) 0x431d58 B.GE 431d20 |
(1568) 0x431d5c LDR X12, [SP, #696] |
(1568) 0x431d60 LDUR X11, [X29, #304] |
(1568) 0x431d64 ADD X12, X12, #8 |
(1568) 0x431d68 B 431d80 |
(1569) 0x431d6c ADD X13, X9, #1 |
(1569) 0x431d70 ADD X10, X10, #1 |
(1569) 0x431d74 LDR X14, [X21, X13,LSL #3] |
(1569) 0x431d78 CMP X10, X14 |
(1569) 0x431d7c B.GE 431d20 |
(1569) 0x431d80 LDR X14, [SP, #648] |
(1569) 0x431d84 LDR X13, [X8, X10,LSL #3] |
(1569) 0x431d88 SUB X14, X14, #1 |
(1569) 0x431d8c CMP X13, X14 |
(1569) 0x431d90 B.NE 431d6c |
(1569) 0x431d94 STR X24, [X11, X10,LSL #3] |
(1569) 0x431d98 LDR X9, [X12, X10,LSL #3] |
(1569) 0x431d9c ADD X24, X9, X24 |
(1569) 0x431da0 LDR X9, [SP, #560] |
(1569) 0x431da4 B 431d6c |
(1563) 0x431da8 ORR X24, XZR, XZR |
(1563) 0x431dac LDP X8, X10, [SP, #384] |
(1563) 0x431db0 LDR X11, [SP, #416] |
(1563) 0x431db4 STR X8, [X10] |
(1563) 0x431db8 LDR X8, [SP, #336] |
(1563) 0x431dbc LDUR X9, [X29, #328] |
(1563) 0x431dc0 STP X9, X8, [X10, #8] |
(1563) 0x431dc4 LDR X8, [SP, #648] |
(1563) 0x431dc8 LDR X9, [X19, X8,LSL #3] |
(1563) 0x431dcc STR X9, [X10, #24] |
(1563) 0x431dd0 LDR X9, [SP, #328] |
(1563) 0x431dd4 STP X11, X9, [X10, #40] |
(1563) 0x431dd8 LDR X9, [SP, #408] |
(1563) 0x431ddc LDR X9, [X9, X8,LSL #3] |
(1563) 0x431de0 STR X9, [X10, #56] |
(1563) 0x431de4 CBZ X24, 431e14 |
(1563) 0x431de8 ORR X0, XZR, X24 |
(1563) 0x431dec MOVZ W1, #8 |
(1563) 0x431df0 BL 4a2570 |
(1563) 0x431df4 LDR X8, [SP, #712] |
(1563) 0x431df8 LDR X9, [SP, #648] |
(1563) 0x431dfc MOVZ W1, #8 |
(1563) 0x431e00 STR X0, [X8, X9,LSL #3] |
(1563) 0x431e04 ORR X0, XZR, X24 |
(1563) 0x431e08 BL 4a2570 |
(1563) 0x431e0c LDR X8, [SP, #648] |
(1563) 0x431e10 B 431e20 |
(1563) 0x431e14 LDR X9, [SP, #712] |
(1563) 0x431e18 ORR X0, XZR, XZR |
(1563) 0x431e1c STR XZR, [X9, X8,LSL #3] |
(1563) 0x431e20 STR X0, [X22, X8,LSL #3] |
(1563) 0x431e24 LDR X1, [SP, #392] |
(1563) 0x431e28 LDR X19, [SP, #360] |
(1563) 0x431e2c ORR X2, XZR, X20 |
(1563) 0x431e30 MOVZ W0, #11 |
(1563) 0x431e34 LDR X9, [SP, #712] |
(1563) 0x431e38 LDR X3, [X9, X8,LSL #3] |
(1563) 0x431e3c BL 47cbc0 |
(1563) 0x431e40 BL 47cfa0 |
(1563) 0x431e44 CMP X24, X19 |
(1563) 0x431e48 B.LE 431e64 |
(1563) 0x431e4c ORR X0, XZR, X25 |
(1563) 0x431e50 BL 4a2670 |
(1563) 0x431e54 ORR X0, XZR, X24 |
(1563) 0x431e58 MOVZ W1, #8 |
(1563) 0x431e5c BL 4a2570 |
(1563) 0x431e60 ORR X25, XZR, X0 |
(1563) 0x431e64 LDR X30, [SP, #432] |
(1563) 0x431e68 STR X24, [SP, #360] |
(1563) 0x431e6c LDR X8, [SP, #416] |
(1563) 0x431e70 STR XZR, [SP, #560] |
(1563) 0x431e74 CMP X8, #1 |
(1563) 0x431e78 B.LT 432100 |
(1563) 0x431e7c LDR X28, [X21, XZR,LSL #3] |
(1563) 0x431e80 ORR X19, XZR, XZR |
(1563) 0x431e84 ORR X22, XZR, XZR |
(1563) 0x431e88 ORR X8, XZR, XZR |
(1563) 0x431e8c B 431eac |
0x431e90 HINT #0 |
0x431e94 HINT #0 |
0x431e98 HINT #0 |
0x431e9c HINT #0 |
(1565) 0x431ea0 LDR X8, [SP, #560] |
(1565) 0x431ea4 LDR X21, [SP, #424] |
(1565) 0x431ea8 ORR X22, XZR, X9 |
(1565) 0x431eac ADD X9, X8, #1 |
(1565) 0x431eb0 LDR X10, [X21, X9,LSL #3] |
(1565) 0x431eb4 CMP X28, X10 |
(1565) 0x431eb8 B.GE 43200c |
(1565) 0x431ebc LDR X9, [SP, #576] |
(1565) 0x431ec0 LDR X10, [SP, #648] |
(1565) 0x431ec4 LDR X9, [X9, X28,LSL #3] |
(1565) 0x431ec8 SUB X10, X10, #1 |
(1565) 0x431ecc ADD X28, X28, #1 |
(1565) 0x431ed0 CMP X9, X10 |
(1565) 0x431ed4 B.NE 431eac |
(1565) 0x431ed8 LDR X9, [SP, #696] |
(1565) 0x431edc LDR X9, [X9, X28,LSL #3] |
(1565) 0x431ee0 CMP X9, #1 |
(1565) 0x431ee4 B.LT 432004 |
(1565) 0x431ee8 LDR X8, [SP, #712] |
(1565) 0x431eec ORR X26, XZR, X22 |
(1565) 0x431ef0 B 431f20 |
0x431ef4 HINT #0 |
0x431ef8 HINT #0 |
0x431efc HINT #0 |
(1566) 0x431f00 ORN X9, XZR, X11 |
(1566) 0x431f04 STR X9, [X10, X26,LSL #3] |
(1566) 0x431f08 LDR X9, [SP, #696] |
(1566) 0x431f0c ADD X26, X26, #1 |
(1566) 0x431f10 LDR X9, [X9, X28,LSL #3] |
(1566) 0x431f14 ADD X9, X9, X22 |
(1566) 0x431f18 CMP X26, X9 |
(1566) 0x431f1c B.GE 431ea0 |
(1566) 0x431f20 LDR X9, [SP, #648] |
(1566) 0x431f24 LDR X10, [X8, X9,LSL #3] |
(1566) 0x431f28 LDR X24, [X10, X26,LSL #3] |
(1566) 0x431f2c SUBS X11, X24, X27 |
(1566) 0x431f30 B.MI 431f40 |
(1566) 0x431f34 LDR X12, [SP, #624] |
(1566) 0x431f38 CMP X11, X12 |
(1566) 0x431f3c B.LT 431f00 |
(1566) 0x431f40 CMP X9, #2 |
(1566) 0x431f44 B.LT 431fa8 |
(1566) 0x431f48 ORR X23, XZR, X25 |
(1566) 0x431f4c ORR X25, XZR, X27 |
(1566) 0x431f50 LDR X27, [SP, #704] |
(1566) 0x431f54 ORR X21, XZR, XZR |
(1566) 0x431f58 HINT #0 |
(1566) 0x431f5c HINT #0 |
(1567) 0x431f60 UBFM X8, X21, #61, #60 |
(1567) 0x431f64 ORR X1, XZR, X24 |
(1567) 0x431f68 LDR X0, [X30, X8] |
(1567) 0x431f6c ADD X8, X27, X8 |
(1567) 0x431f70 LDP X8, X9, [X8] |
(1567) 0x431f74 SUB X2, X9, X8 |
(1567) 0x431f78 BL 4a1720 |
(1567) 0x431f7c TBZ X0, #63, 431fe0 |
(1567) 0x431f80 LDR X9, [SP, #648] |
(1567) 0x431f84 LDR X30, [SP, #432] |
(1567) 0x431f88 ADD X21, X21, #1 |
(1567) 0x431f8c SUB X10, X9, #1 |
(1567) 0x431f90 CMP X21, X10 |
(1567) 0x431f94 B.LT 431f60 |
(1566) 0x431f98 LDR X8, [SP, #712] |
(1566) 0x431f9c ORR X27, XZR, X25 |
(1566) 0x431fa0 ORR X25, XZR, X23 |
(1566) 0x431fa4 B 431fac |
(1566) 0x431fa8 SUB X10, X9, #1 |
(1566) 0x431fac LDR X9, [X8, X9,LSL #3] |
(1566) 0x431fb0 LDR X10, [X30, X10,LSL #3] |
(1566) 0x431fb4 LDR X9, [X9, X26,LSL #3] |
(1566) 0x431fb8 STR X9, [X10, X19,LSL #3] |
(1566) 0x431fbc STR X26, [X25, X19,LSL #3] |
(1566) 0x431fc0 ADD X19, X19, #1 |
(1566) 0x431fc4 LDR X9, [SP, #696] |
(1566) 0x431fc8 ADD X26, X26, #1 |
(1566) 0x431fcc LDR X9, [X9, X28,LSL #3] |
(1566) 0x431fd0 ADD X9, X9, X22 |
(1566) 0x431fd4 CMP X26, X9 |
(1566) 0x431fd8 B.LT 431f20 |
(1565) 0x431fdc B 431ea0 |
(1566) 0x431fe0 LDR X8, [X27, X21,LSL #3] |
(1566) 0x431fe4 LDR X10, [SP, #648] |
(1566) 0x431fe8 LDR X30, [SP, #432] |
(1566) 0x431fec ORR X27, XZR, X25 |
(1566) 0x431ff0 ORR X25, XZR, X23 |
(1566) 0x431ff4 ADD X9, X8, X0 |
(1566) 0x431ff8 LDR X8, [SP, #712] |
(1566) 0x431ffc LDR X10, [X8, X10,LSL #3] |
(1566) 0x432000 B 431f04 |
(1565) 0x432004 ADD X22, X9, X22 |
(1565) 0x432008 B 431eac |
(1565) 0x43200c LDR X8, [SP, #416] |
(1565) 0x432010 STR X9, [SP, #560] |
(1565) 0x432014 CMP X9, X8 |
(1565) 0x432018 ORR X8, XZR, X9 |
(1565) 0x43201c B.GE 432028 |
(1565) 0x432020 LDR X28, [X21, X8,LSL #3] |
(1565) 0x432024 B 431eac |
(1563) 0x432028 LDR X22, [SP, #352] |
(1563) 0x43202c SUB X23, X29, #168 |
(1563) 0x432030 SUB X26, X29, #144 |
(1563) 0x432034 CBZ X19, 432100 |
(1563) 0x432038 LDR X8, [SP, #648] |
(1563) 0x43203c ORR X1, XZR, X25 |
(1563) 0x432040 ORR X2, XZR, XZR |
(1563) 0x432044 SUB X3, X19, #1 |
(1563) 0x432048 LDR X0, [X22, X8,LSL #3] |
(1563) 0x43204c BL 4a3060 |
(1563) 0x432050 LDR X9, [SP, #648] |
(1563) 0x432054 LDR X8, [SP, #704] |
(1563) 0x432058 CMP X19, #2 |
(1563) 0x43205c UBFM X10, X9, #61, #60 |
(1563) 0x432060 ADD X9, X10, X8 |
(1563) 0x432064 LDUR X11, [X9, #504] |
(1563) 0x432068 LDR X9, [SP, #712] |
(1563) 0x43206c STR X11, [SP, #488] |
(1563) 0x432070 LDR X12, [X25] |
(1563) 0x432074 LDR X10, [X9, X10] |
(1563) 0x432078 STR X11, [X10, X12,LSL #3] |
(1563) 0x43207c MOVZ W10, #1 |
(1563) 0x432080 STR X10, [SP, #560] |
(1563) 0x432084 B.LT 432140 |
(1563) 0x432088 ORR X10, XZR, XZR |
(1563) 0x43208c MOVZ W11, #1 |
(1563) 0x432090 B 4320dc |
0x432094 HINT #0 |
0x432098 HINT #0 |
0x43209c HINT #0 |
(1564) 0x4320a0 ADD X10, X10, #1 |
(1564) 0x4320a4 STR X14, [X13, X10,LSL #3] |
(1564) 0x4320a8 LDR X11, [SP, #488] |
(1564) 0x4320ac LDR X12, [SP, #648] |
(1564) 0x4320b0 ADD X13, X11, #1 |
(1564) 0x4320b4 LDR X11, [SP, #560] |
(1564) 0x4320b8 STR X13, [SP, #488] |
(1564) 0x4320bc LDR X12, [X9, X12,LSL #3] |
(1564) 0x4320c0 LDR X11, [X25, X11,LSL #3] |
(1564) 0x4320c4 STR X13, [X12, X11,LSL #3] |
(1564) 0x4320c8 LDR X11, [SP, #560] |
(1564) 0x4320cc ADD X11, X11, #1 |
(1564) 0x4320d0 CMP X11, X19 |
(1564) 0x4320d4 STR X11, [SP, #560] |
(1564) 0x4320d8 B.GE 432140 |
(1564) 0x4320dc LDR X12, [SP, #648] |
(1564) 0x4320e0 LDR X13, [X22, X12,LSL #3] |
(1564) 0x4320e4 LDR X14, [X13, X11,LSL #3] |
(1564) 0x4320e8 LDR X15, [X13, X10,LSL #3] |
(1564) 0x4320ec CMP X14, X15 |
(1564) 0x4320f0 B.GT 4320a0 |
(1564) 0x4320f4 LDR X13, [SP, #488] |
(1564) 0x4320f8 B 4320bc |
0x4320fc HINT #0 |
(1563) 0x432100 LDR X8, [SP, #528] |
(1563) 0x432104 LDR X19, [SP, #400] |
(1563) 0x432108 CMP X8, #1 |
(1563) 0x43210c B.LE 432124 |
(1563) 0x432110 LDR X8, [SP, #704] |
(1563) 0x432114 LDR X9, [SP, #648] |
(1563) 0x432118 ADD X8, X8, X9,LSL #3 |
(1563) 0x43211c LDUR X9, [X8, #504] |
(1563) 0x432120 STR X9, [X8] |
(1563) 0x432124 LDP X9, X8, [SP, #480] |
(1563) 0x432128 CMP X9, X8 |
(1563) 0x43212c B.GT 431928 |
(1563) 0x432130 B 432160 |
0x432134 HINT #0 |
0x432138 HINT #0 |
0x43213c HINT #0 |
(1563) 0x432140 LDR X9, [SP, #488] |
(1563) 0x432144 LDR X10, [SP, #648] |
(1563) 0x432148 LDR X19, [SP, #400] |
(1563) 0x43214c ADD X9, X9, #1 |
(1563) 0x432150 STR X9, [X8, X10,LSL #3] |
(1563) 0x432154 LDP X9, X8, [SP, #480] |
(1563) 0x432158 CMP X9, X8 |
(1563) 0x43215c B.GT 431928 |
(1563) 0x432160 ADD X8, X8, #1 |
(1563) 0x432164 STR X8, [SP, #480] |
(1563) 0x432168 B 431928 |
(1540) 0x43216c STP X9, X8, [SP, #200] |
(1540) 0x432170 SUB X8, X29, #160 |
(1540) 0x432174 SUB X10, X29, #72 |
(1540) 0x432178 SUB X11, X29, #232 |
(1540) 0x43217c SUB X9, X29, #88 |
(1540) 0x432180 STP X21, X22, [SP, #80] |
(1540) 0x432184 STP X10, X8, [SP, #184] |
(1540) 0x432188 SUB X8, X29, #224 |
(1540) 0x43218c STR X9, [SP, #160] |
(1540) 0x432190 ADD X9, X29, #104 |
(1540) 0x432194 SUB X10, X29, #32 |
(1540) 0x432198 ADD X12, SP, #728 |
(1540) 0x43219c ADRP X0, |
(1540) 0x4321a0 ADD X0, X0, #784 |
(1540) 0x4321a4 STP X12, X20, [SP, #16] |
(1540) 0x4321a8 STP X8, X11, [SP, #168] |
(1540) 0x4321ac ADD X8, SP, #680 |
(1540) 0x4321b0 SUB X11, X29, #56 |
(1540) 0x4321b4 ADRP X2, 4351b4 |
(1540) 0x4321b8 ADD X2, X2, #1248 |
(1540) 0x4321bc STP X9, X8, [SP, #144] |
(1540) 0x4321c0 SUB X8, X29, #80 |
(1540) 0x4321c4 SUB X9, X29, #256 |
(1540) 0x4321c8 STP X9, X8, [SP, #128] |
(1540) 0x4321cc ADD X8, SP, #720 |
(1540) 0x4321d0 SUB X9, X29, #168 |
(1540) 0x4321d4 ADD X3, SP, #632 |
(1540) 0x4321d8 SUB X4, X29, #128 |
(1540) 0x4321dc STP X9, X8, [SP, #112] |
(1540) 0x4321e0 ADD X8, SP, #736 |
(1540) 0x4321e4 SUB X9, X29, #40 |
(1540) 0x4321e8 ADD X5, SP, #752 |
(1540) 0x4321ec ADD X6, SP, #464 |
(1540) 0x4321f0 STP X24, X8, [SP, #96] |
(1540) 0x4321f4 SUB X8, X29, #48 |
(1540) 0x4321f8 ADD X7, SP, #760 |
(1540) 0x4321fc MOVZ W1, #32 |
(1540) 0x432200 STP X9, X8, [SP, #64] |
(1540) 0x432204 SUB X8, X29, #8 |
(1540) 0x432208 SUB X9, X29, #64 |
(1540) 0x43220c STP X8, X10, [SP, #48] |
(1540) 0x432210 ADD X8, SP, #744 |
(1540) 0x432214 STP X11, X9, [SP, #32] |
(1540) 0x432218 STP X8, X19, [SP] |
(1540) 0x43221c BL 40f670 |
(1540) 0x432220 LDR X8, [SP, #624] |
(1540) 0x432224 CBZ X8, 432234 |
(1540) 0x432228 LDUR X0, [X29, #264] |
(1540) 0x43222c BL 4a2670 |
(1540) 0x432230 STUR XZR, [X29, #264] |
(1540) 0x432234 LDUR X0, [X29, #256] |
(1540) 0x432238 BL 4a2670 |
(1540) 0x43223c LDR X8, [SP, #728] |
(1540) 0x432240 STUR XZR, [X29, #256] |
(1540) 0x432244 LDR X0, [X8, #8] |
(1540) 0x432248 BL 4a2670 |
(1540) 0x43224c LDR X8, [SP, #728] |
(1540) 0x432250 STR XZR, [X8, #8] |
(1540) 0x432254 LDR X8, [SP, #528] |
(1540) 0x432258 CMP X8, #2 |
(1540) 0x43225c B.LT 432274 |
(1540) 0x432260 LDR X8, [SP, #720] |
(1540) 0x432264 LDR X0, [X8, #8] |
(1540) 0x432268 BL 4a2670 |
(1540) 0x43226c LDR X8, [SP, #720] |
(1540) 0x432270 STR XZR, [X8, #8] |
(1540) 0x432274 LDR X24, [SP, #640] |
(1540) 0x432278 MOVZ W8, #2 |
(1540) 0x43227c STR X8, [SP, #648] |
(1540) 0x432280 CMP X24, #2 |
(1540) 0x432284 B.LE 43274c |
(1540) 0x432288 ORR X25, XZR, XZR |
(1540) 0x43228c ORR X27, XZR, XZR |
(1540) 0x432290 MOVZ W8, #2 |
(1540) 0x432294 SUB X23, X29, #232 |
(1540) 0x432298 ADD X26, SP, #752 |
(1540) 0x43229c ORR X19, XZR, XZR |
(1540) 0x4322a0 ADRP X20, |
(1540) 0x4322a4 ADD X20, X20, #808 |
(1540) 0x4322a8 ADRP X21, 4352a8 |
(1540) 0x4322ac ADD X21, X21, #3232 |
(1540) 0x4322b0 B 4322d0 |
0x4322b4 HINT #0 |
0x4322b8 HINT #0 |
0x4322bc HINT #0 |
(1548) 0x4322c0 ADD X8, X8, #1 |
(1548) 0x4322c4 CMP X8, X24 |
(1548) 0x4322c8 STR X8, [SP, #648] |
(1548) 0x4322cc B.GE 432750 |
(1548) 0x4322d0 LDR X9, [SP, #528] |
(1548) 0x4322d4 CMP X9, #2 |
(1548) 0x4322d8 B.LT 4325a0 |
(1548) 0x4322dc LDR X9, [SP, #400] |
(1548) 0x4322e0 LDR X9, [X9, X8,LSL #3] |
(1548) 0x4322e4 LDUR X8, [X29, #328] |
(1548) 0x4322e8 LDR X9, [X9, X8,LSL #3] |
(1548) 0x4322ec CMP X9, X27 |
(1548) 0x4322f0 STR X9, [SP, #504] |
(1548) 0x4322f4 B.LE 432328 |
(1548) 0x4322f8 ORR X0, XZR, X19 |
(1548) 0x4322fc BL 4a2670 |
(1548) 0x432300 LDR X0, [SP, #504] |
(1548) 0x432304 MOVZ W1, #8 |
(1548) 0x432308 BL 4a2570 |
(1548) 0x43230c LDR X27, [SP, #504] |
(1548) 0x432310 LDUR X8, [X29, #328] |
(1548) 0x432314 ORR X19, XZR, X0 |
(1548) 0x432318 CMP X8, #1 |
(1548) 0x43231c STR XZR, [SP, #560] |
(1548) 0x432320 B.GE 432338 |
(1548) 0x432324 B 432504 |
(1548) 0x432328 ORR X27, XZR, X9 |
(1548) 0x43232c CMP X8, #1 |
(1548) 0x432330 STR XZR, [SP, #560] |
(1548) 0x432334 B.LT 432504 |
(1548) 0x432338 LDR X13, [SP, #648] |
(1548) 0x43233c LDP X11, X10, [X29, #824] |
(1548) 0x432340 LDR X12, [SP, #584] |
(1548) 0x432344 ORR X15, XZR, XZR |
(1548) 0x432348 ORR X9, XZR, XZR |
(1548) 0x43234c ADD X14, X19, #16 |
(1548) 0x432350 SUB X13, X13, #1 |
(1548) 0x432354 B 43236c |
0x432358 HINT #0 |
0x43235c HINT #0 |
(1549) 0x432360 CMP X9, X8 |
(1549) 0x432364 STR X9, [SP, #560] |
(1549) 0x432368 B.EQ 432504 |
(1549) 0x43236c LDR X16, [X10, X9,LSL #3] |
(1549) 0x432370 ADD X9, X9, #1 |
(1549) 0x432374 LDR X17, [X10, X9,LSL #3] |
(1549) 0x432378 CMP X16, X17 |
(1549) 0x43237c B.GE 432360 |
(1549) 0x432380 LDP X18, X0, [X29, #880] |
(1549) 0x432384 LDP X1, X2, [X29, #856] |
(1549) 0x432388 ADD X3, X0, #16 |
(1549) 0x43238c ADD X4, X2, #16 |
(1549) 0x432390 B 4323ac |
0x432394 HINT #0 |
0x432398 HINT #0 |
0x43239c HINT #0 |
(1550) 0x4323a0 ADD X16, X16, #1 |
(1550) 0x4323a4 CMP X16, X17 |
(1550) 0x4323a8 B.EQ 432360 |
(1550) 0x4323ac LDR X5, [X11, X16,LSL #3] |
(1550) 0x4323b0 LDR X6, [X12, X5,LSL #3] |
(1550) 0x4323b4 CMP X6, X13 |
(1550) 0x4323b8 B.NE 4323a0 |
(1550) 0x4323bc ADD X6, X5, #1 |
(1550) 0x4323c0 LDR X22, [X18, X5,LSL #3] |
(1550) 0x4323c4 LDR X7, [X18, X6,LSL #3] |
(1550) 0x4323c8 CMP X7, X22 |
(1550) 0x4323cc B.LE 432460 |
(1550) 0x4323d0 SUB W28, W7, W22 |
(1550) 0x4323d4 ANDS X30, X28, #4160 |
(1550) 0x4323d8 B.EQ 43240c |
(1550) 0x4323dc ORR X28, XZR, X22 |
(1554) 0x4323e0 LDR D0, [X0, X28,LSL #3] |
(1554) 0x4323e4 ADD X28, X28, #1 |
(1554) 0x4323e8 SUBS X30, X30, #1 |
(1554) 0x4323ec STR D0, [X19, X15,LSL #3] |
(1554) 0x4323f0 ADD X15, X15, #1 |
(1554) 0x4323f4 B.NE 4323e0 |
(1550) 0x4323f8 ORN X22, XZR, X22 |
(1550) 0x4323fc ADD X22, X7, X22 |
(1550) 0x432400 CMP X22, #3 |
(1550) 0x432404 B.CS 432420 |
(1550) 0x432408 B 432460 |
(1550) 0x43240c ORR X28, XZR, X22 |
(1550) 0x432410 ORN X22, XZR, X22 |
(1550) 0x432414 ADD X22, X7, X22 |
(1550) 0x432418 CMP X22, #3 |
(1550) 0x43241c B.CC 432460 |
(1550) 0x432420 SUB X7, X7, X28 |
(1550) 0x432424 ADD X22, X3, X28,LSL #3 |
(1550) 0x432428 ADD X28, X14, X15,LSL #3 |
(1553) 0x43242c LDUR D0, [X22, #496] |
(1553) 0x432430 ADD X15, X15, #4 |
(1553) 0x432434 SUBS X7, X7, #4 |
(1553) 0x432438 STUR D0, [X28, #496] |
(1553) 0x43243c LDUR D0, [X22, #504] |
(1553) 0x432440 STUR D0, [X28, #504] |
(1553) 0x432444 LDR D0, [X22] |
(1553) 0x432448 STR D0, [X28] |
(1553) 0x43244c LDR D0, [X22, #8] |
(1553) 0x432450 ADD X22, X22, #32 |
(1553) 0x432454 STR D0, [X28, #8] |
(1553) 0x432458 ADD X28, X28, #32 |
(1553) 0x43245c B.NE 43242c |
(1550) 0x432460 LDR X7, [X1, X5,LSL #3] |
(1550) 0x432464 LDR X5, [X1, X6,LSL #3] |
(1550) 0x432468 CMP X5, X7 |
(1550) 0x43246c B.LE 4323a0 |
(1550) 0x432470 SUB W6, W5, W7 |
(1550) 0x432474 ANDS X22, X6, #4160 |
(1550) 0x432478 B.EQ 4324ac |
(1550) 0x43247c ORR X6, XZR, X7 |
(1552) 0x432480 LDR D0, [X2, X6,LSL #3] |
(1552) 0x432484 ADD X6, X6, #1 |
(1552) 0x432488 SUBS X22, X22, #1 |
(1552) 0x43248c STR D0, [X19, X15,LSL #3] |
(1552) 0x432490 ADD X15, X15, #1 |
(1552) 0x432494 B.NE 432480 |
(1550) 0x432498 ORN X7, XZR, X7 |
(1550) 0x43249c ADD X7, X5, X7 |
(1550) 0x4324a0 CMP X7, #3 |
(1550) 0x4324a4 B.CC 4323a0 |
(1550) 0x4324a8 B 4324c0 |
(1550) 0x4324ac ORR X6, XZR, X7 |
(1550) 0x4324b0 ORN X7, XZR, X7 |
(1550) 0x4324b4 ADD X7, X5, X7 |
(1550) 0x4324b8 CMP X7, #3 |
(1550) 0x4324bc B.CC 4323a0 |
(1550) 0x4324c0 SUB X5, X5, X6 |
(1550) 0x4324c4 ADD X6, X4, X6,LSL #3 |
(1550) 0x4324c8 ADD X7, X14, X15,LSL #3 |
(1551) 0x4324cc LDUR D0, [X6, #496] |
(1551) 0x4324d0 ADD X15, X15, #4 |
(1551) 0x4324d4 SUBS X5, X5, #4 |
(1551) 0x4324d8 STUR D0, [X7, #496] |
(1551) 0x4324dc LDUR D0, [X6, #504] |
(1551) 0x4324e0 STUR D0, [X7, #504] |
(1551) 0x4324e4 LDR D0, [X6] |
(1551) 0x4324e8 STR D0, [X7] |
(1551) 0x4324ec LDR D0, [X6, #8] |
(1551) 0x4324f0 ADD X6, X6, #32 |
(1551) 0x4324f4 STR D0, [X7, #8] |
(1551) 0x4324f8 ADD X7, X7, #32 |
(1551) 0x4324fc B.NE 4324cc |
(1550) 0x432500 B 4323a0 |
(1548) 0x432504 LDP X11, X9, [SP, #392] |
(1548) 0x432508 LDP X12, X10, [SP, #408] |
(1548) 0x43250c LDR X3, [SP, #568] |
(1548) 0x432510 STR X8, [X11, #8] |
(1548) 0x432514 LDR X8, [SP, #648] |
(1548) 0x432518 LDR X9, [X9, X8,LSL #3] |
(1548) 0x43251c STR X10, [X11, #40] |
(1548) 0x432520 STR X9, [X11, #24] |
(1548) 0x432524 LDR X9, [X12, X8,LSL #3] |
(1548) 0x432528 STR X9, [X11, #56] |
(1548) 0x43252c LDR X8, [X12, X8,LSL #3] |
(1548) 0x432530 LDR X22, [X8, X10,LSL #3] |
(1548) 0x432534 CMP X22, X25 |
(1548) 0x432538 B.LE 43255c |
(1548) 0x43253c ORR X0, XZR, X3 |
(1548) 0x432540 BL 4a2670 |
(1548) 0x432544 ORR X0, XZR, X22 |
(1548) 0x432548 MOVZ W1, #8 |
(1548) 0x43254c STR XZR, [SP, #568] |
(1548) 0x432550 BL 4a2570 |
(1548) 0x432554 ORR X3, XZR, X0 |
(1548) 0x432558 STR X0, [SP, #568] |
(1548) 0x43255c LDR X1, [SP, #392] |
(1548) 0x432560 ORR X2, XZR, X19 |
(1548) 0x432564 MOVZ W0, #1 |
(1548) 0x432568 BL 47cbc0 |
(1548) 0x43256c BL 47cfa0 |
(1548) 0x432570 LDR X8, [SP, #648] |
(1548) 0x432574 LDR X25, [SP, #400] |
(1548) 0x432578 LDR X0, [X25, X8,LSL #3] |
(1548) 0x43257c BL 4a2670 |
(1548) 0x432580 LDR X8, [SP, #648] |
(1548) 0x432584 STR XZR, [X25, X8,LSL #3] |
(1548) 0x432588 LDR X25, [SP, #408] |
(1548) 0x43258c LDR X0, [X25, X8,LSL #3] |
(1548) 0x432590 BL 4a2670 |
(1548) 0x432594 LDR X8, [SP, #648] |
(1548) 0x432598 STR XZR, [X25, X8,LSL #3] |
(1548) 0x43259c ORR X25, XZR, X22 |
(1548) 0x4325a0 LDR X9, [SP, #752] |
(1548) 0x4325a4 ORR X0, XZR, X20 |
(1548) 0x4325a8 ORR X2, XZR, X21 |
(1548) 0x4325ac ADD X3, SP, #632 |
(1548) 0x4325b0 SUB X4, X29, #128 |
(1548) 0x4325b4 ADD X5, SP, #624 |
(1548) 0x4325b8 ADD X6, SP, #480 |
(1548) 0x4325bc ADD X7, SP, #616 |
(1548) 0x4325c0 MOVZ W1, #42 |
(1548) 0x4325c4 ADD X8, X9, X8,LSL #3 |
(1548) 0x4325c8 LDP X8, X9, [X8] |
(1548) 0x4325cc SUB X8, X9, X8 |
(1548) 0x4325d0 STR X8, [SP, #464] |
(1548) 0x4325d4 SUB X8, X29, #224 |
(1548) 0x4325d8 STP X8, X23, [SP, #280] |
(1548) 0x4325dc ADD X8, SP, #568 |
(1548) 0x4325e0 STR X8, [SP, #272] |
(1548) 0x4325e4 SUB X8, X29, #72 |
(1548) 0x4325e8 STR X8, [SP, #264] |
(1548) 0x4325ec ADD X8, SP, #712 |
(1548) 0x4325f0 STR X8, [SP, #256] |
(1548) 0x4325f4 ADD X8, SP, #696 |
(1548) 0x4325f8 STR X8, [SP, #248] |
(1548) 0x4325fc SUB X8, X29, #208 |
(1548) 0x432600 STR X8, [SP, #240] |
(1548) 0x432604 SUB X8, X29, #88 |
(1548) 0x432608 STR X8, [SP, #232] |
(1548) 0x43260c ADD X8, SP, #680 |
(1548) 0x432610 STR X8, [SP, #224] |
(1548) 0x432614 ADD X8, X29, #104 |
(1548) 0x432618 STR X8, [SP, #216] |
(1548) 0x43261c SUB X8, X29, #80 |
(1548) 0x432620 STR X8, [SP, #208] |
(1548) 0x432624 SUB X8, X29, #40 |
(1548) 0x432628 STR X8, [SP, #200] |
(1548) 0x43262c SUB X8, X29, #32 |
(1548) 0x432630 STR X8, [SP, #192] |
(1548) 0x432634 SUB X8, X29, #8 |
(1548) 0x432638 STR X8, [SP, #184] |
(1548) 0x43263c SUB X8, X29, #48 |
(1548) 0x432640 STR X8, [SP, #176] |
(1548) 0x432644 SUB X8, X29, #64 |
(1548) 0x432648 STR X8, [SP, #168] |
(1548) 0x43264c SUB X8, X29, #56 |
(1548) 0x432650 STR X8, [SP, #160] |
(1548) 0x432654 ADD X8, SP, #576 |
(1548) 0x432658 STR X8, [SP, #152] |
(1548) 0x43265c SUB X8, X29, #120 |
(1548) 0x432660 STR X8, [SP, #144] |
(1548) 0x432664 SUB X8, X29, #112 |
(1548) 0x432668 STR X8, [SP, #136] |
(1548) 0x43266c ADD X8, SP, #584 |
(1548) 0x432670 STR X8, [SP, #128] |
(1548) 0x432674 SUB X8, X29, #104 |
(1548) 0x432678 STR X8, [SP, #120] |
(1548) 0x43267c SUB X8, X29, #96 |
(1548) 0x432680 STR X8, [SP, #112] |
(1548) 0x432684 SUB X8, X29, #176 |
(1548) 0x432688 STR X8, [SP, #104] |
(1548) 0x43268c SUB X8, X29, #160 |
(1548) 0x432690 STR X8, [SP, #96] |
(1548) 0x432694 ADD X8, SP, #720 |
(1548) 0x432698 STR X8, [SP, #88] |
(1548) 0x43269c SUB X8, X29, #168 |
(1548) 0x4326a0 STR X8, [SP, #80] |
(1548) 0x4326a4 ADD X8, SP, #736 |
(1548) 0x4326a8 STR X8, [SP, #72] |
(1548) 0x4326ac SUB X8, X29, #152 |
(1548) 0x4326b0 STR X8, [SP, #64] |
(1548) 0x4326b4 SUB X8, X29, #136 |
(1548) 0x4326b8 STR X8, [SP, #56] |
(1548) 0x4326bc ADD X8, SP, #728 |
(1548) 0x4326c0 STR X8, [SP, #48] |
(1548) 0x4326c4 SUB X8, X29, #144 |
(1548) 0x4326c8 STR X8, [SP, #40] |
(1548) 0x4326cc ADD X8, SP, #744 |
(1548) 0x4326d0 STR X8, [SP, #32] |
(1548) 0x4326d4 ADD X8, SP, #760 |
(1548) 0x4326d8 STR X8, [SP, #24] |
(1548) 0x4326dc ADD X8, SP, #464 |
(1548) 0x4326e0 STR X8, [SP, #16] |
(1548) 0x4326e4 ADD X8, SP, #648 |
(1548) 0x4326e8 STP X26, X8, [SP] |
(1548) 0x4326ec BL 40f670 |
(1548) 0x4326f0 LDR X8, [SP, #728] |
(1548) 0x4326f4 LDR X9, [SP, #648] |
(1548) 0x4326f8 LDR X0, [X8, X9,LSL #3] |
(1548) 0x4326fc BL 4a2670 |
(1548) 0x432700 LDR X9, [SP, #728] |
(1548) 0x432704 LDR X8, [SP, #648] |
(1548) 0x432708 STR XZR, [X9, X8,LSL #3] |
(1548) 0x43270c LDR X9, [SP, #528] |
(1548) 0x432710 CMP X9, #2 |
(1548) 0x432714 B.LT 4322c0 |
(1548) 0x432718 LDR X9, [SP, #720] |
(1548) 0x43271c LDR X0, [X9, X8,LSL #3] |
(1548) 0x432720 BL 4a2670 |
(1548) 0x432724 LDR X8, [SP, #720] |
(1548) 0x432728 LDR X9, [SP, #648] |
(1548) 0x43272c STR XZR, [X8, X9,LSL #3] |
(1548) 0x432730 LDR X8, [SP, #712] |
(1548) 0x432734 LDR X0, [X8, X9,LSL #3] |
(1548) 0x432738 BL 4a2670 |
(1548) 0x43273c LDR X9, [SP, #712] |
(1548) 0x432740 LDR X8, [SP, #648] |
(1548) 0x432744 STR XZR, [X9, X8,LSL #3] |
(1548) 0x432748 B 4322c0 |
(1540) 0x43274c ORR X19, XZR, XZR |
(1540) 0x432750 LDUR X0, [X29, #288] |
(1540) 0x432754 BL 4a2670 |
(1540) 0x432758 LDR X0, [SP, #400] |
(1540) 0x43275c STUR XZR, [X29, #288] |
(1540) 0x432760 BL 4a2670 |
(1540) 0x432764 LDR X0, [SP, #408] |
(1540) 0x432768 BL 4a2670 |
(1540) 0x43276c LDUR X0, [X29, #280] |
(1540) 0x432770 BL 4a2670 |
(1540) 0x432774 ORR X0, XZR, X19 |
(1540) 0x432778 STUR XZR, [X29, #280] |
(1540) 0x43277c BL 4a2670 |
(1540) 0x432780 LDR X0, [SP, #568] |
(1540) 0x432784 BL 4a2670 |
(1540) 0x432788 LDR X0, [SP, #728] |
(1540) 0x43278c STR XZR, [SP, #568] |
(1540) 0x432790 BL 4a2670 |
(1540) 0x432794 LDR X0, [SP, #720] |
(1540) 0x432798 STR XZR, [SP, #728] |
(1540) 0x43279c BL 4a2670 |
(1540) 0x4327a0 LDR X0, [SP, #712] |
(1540) 0x4327a4 STR XZR, [SP, #720] |
(1540) 0x4327a8 BL 4a2670 |
(1540) 0x4327ac LDR X0, [SP, #744] |
(1540) 0x4327b0 STR XZR, [SP, #712] |
(1540) 0x4327b4 BL 4a2670 |
(1540) 0x4327b8 LDR X0, [SP, #736] |
(1540) 0x4327bc STR XZR, [SP, #744] |
(1540) 0x4327c0 BL 4a2670 |
(1540) 0x4327c4 LDUR X0, [X29, #304] |
(1540) 0x4327c8 STR XZR, [SP, #736] |
(1540) 0x4327cc BL 4a2670 |
(1540) 0x4327d0 LDR X0, [SP, #696] |
(1540) 0x4327d4 STUR XZR, [X29, #304] |
(1540) 0x4327d8 BL 4a2670 |
(1540) 0x4327dc LDR X0, [SP, #592] |
(1540) 0x4327e0 STR XZR, [SP, #696] |
(1540) 0x4327e4 BL 4a2670 |
(1540) 0x4327e8 LDR X0, [SP, #584] |
(1540) 0x4327ec STR XZR, [SP, #592] |
(1540) 0x4327f0 BL 4a2670 |
(1540) 0x4327f4 LDR X0, [SP, #576] |
(1540) 0x4327f8 STR XZR, [SP, #584] |
(1540) 0x4327fc BL 4a2670 |
(1540) 0x432800 LDR X0, [SP, #752] |
(1540) 0x432804 STR XZR, [SP, #576] |
(1540) 0x432808 BL 4a2670 |
(1540) 0x43280c LDR X0, [SP, #760] |
(1540) 0x432810 STR XZR, [SP, #752] |
(1540) 0x432814 BL 4a2670 |
(1540) 0x432818 LDR X0, [SP, #688] |
(1540) 0x43281c STR XZR, [SP, #760] |
(1540) 0x432820 BL 4a2670 |
(1540) 0x432824 LDR X0, [SP, #680] |
(1540) 0x432828 STR XZR, [SP, #688] |
(1540) 0x43282c BL 4a2670 |
(1540) 0x432830 LDR X8, [SP, #528] |
(1540) 0x432834 STR XZR, [SP, #680] |
(1540) 0x432838 CMP X8, #2 |
(1540) 0x43283c B.LT 432848 |
(1540) 0x432840 LDR X0, [SP, #392] |
(1540) 0x432844 BL 4a2670 |
(1540) 0x432848 LDP X8, X4, [SP, #312] |
(1540) 0x43284c LDR X9, [SP, #632] |
(1540) 0x432850 LDR X2, [SP, #520] |
(1540) 0x432854 ORR X5, XZR, XZR |
(1540) 0x432858 LDR X0, [SP, #384] |
(1540) 0x43285c LDR X1, [X8, #8] |
(1540) 0x432860 LDR X3, [X8, #104] |
(1540) 0x432864 LDUR X8, [X29, #368] |
(1540) 0x432868 LDR X6, [X8, X9,LSL #3] |
(1540) 0x43286c LDUR X8, [X29, #344] |
(1540) 0x432870 LDR X7, [X8, X9,LSL #3] |
(1540) 0x432874 BL 485ea0 |
(1540) 0x432878 LDR X20, [X0, #56] |
(1540) 0x43287c LDUR X8, [X29, #376] |
(1540) 0x432880 LDR X1, [SP, #304] |
(1540) 0x432884 ORR X19, XZR, X0 |
(1540) 0x432888 FCMP D8, #0 |
(1540) 0x43288c STR X8, [X20, #48] |
(1540) 0x432890 LDUR X8, [X29, #368] |
(1540) 0x432894 STR X8, [X20] |
(1540) 0x432898 LDUR X8, [X29, #360] |
(1540) 0x43289c STR X8, [X20, #8] |
(1540) 0x4328a0 LDUR X8, [X29, #352] |
(1540) 0x4328a4 LDR X22, [X0, #64] |
(1540) 0x4328a8 STR X8, [X22, #48] |
(1540) 0x4328ac LDUR X8, [X29, #344] |
(1540) 0x4328b0 STR X8, [X22] |
(1540) 0x4328b4 LDUR X8, [X29, #336] |
(1540) 0x4328b8 STR X8, [X22, #8] |
(1540) 0x4328bc STR XZR, [X0, #136] |
(1540) 0x4328c0 B.NE 4328e4 |
(1540) 0x4328c4 CBNZ X1, 4328e4 |
(1540) 0x4328c8 LDUR X8, [X29, #344] |
(1540) 0x4328cc LDR X9, [SP, #632] |
(1540) 0x4328d0 LDR X20, [X8, X9,LSL #3] |
(1540) 0x4328d4 STR XZR, [SP, #472] |
(1540) 0x4328d8 STR X20, [SP, #496] |
(1540) 0x4328dc CBNZ X20, 432924 |
(1540) 0x4328e0 B 432b34 |
(1540) 0x4328e4 ORR X0, XZR, X19 |
(1540) 0x4328e8 FMOV D0, D8 |
(1540) 0x4328ec BL 4284c0 |
(1540) 0x4328f0 LDR X8, [X20, #48] |
(1540) 0x4328f4 STUR X8, [X29, #376] |
(1540) 0x4328f8 LDP X8, X9, [X20] |
(1540) 0x4328fc STP X9, X8, [X29, #872] |
(1540) 0x432900 LDR X8, [X22, #48] |
(1540) 0x432904 STUR X8, [X29, #352] |
(1540) 0x432908 LDP X8, X9, [X22] |
(1540) 0x43290c STP X9, X8, [X29, #848] |
(1540) 0x432910 LDR X9, [SP, #632] |
(1540) 0x432914 LDR X20, [X8, X9,LSL #3] |
(1540) 0x432918 STR XZR, [SP, #472] |
(1540) 0x43291c STR X20, [SP, #496] |
(1540) 0x432920 CBZ X20, 432b34 |
(1540) 0x432924 LDR X8, [SP, #480] |
(1540) 0x432928 LDUR X9, [X29, #384] |
(1540) 0x43292c MOVZ W1, #8 |
(1540) 0x432930 CMP X8, X9 |
(1540) 0x432934 CSEL X0, X8, X9, #12 |
(1540) 0x432938 BL 4a2570 |
(1540) 0x43293c STUR X0, [X29, #272] |
(1540) 0x432940 ADRP X0, |
(1540) 0x432944 ADD X0, X0, #880 |
(1540) 0x432948 ADRP X2, 436948 |
(1540) 0x43294c ADD X2, X2, #2080 |
(1540) 0x432950 ADD X3, SP, #480 |
(1540) 0x432954 SUB X4, X29, #240 |
(1540) 0x432958 MOVZ W1, #2 |
(1540) 0x43295c BL 40f670 |
(1540) 0x432960 CMP X20, #1 |
(1540) 0x432964 STR XZR, [SP, #472] |
(1540) 0x432968 STR XZR, [SP, #560] |
(1540) 0x43296c B.LT 4329c8 |
(1540) 0x432970 LDUR X8, [X29, #336] |
(1540) 0x432974 LDUR X9, [X29, #272] |
(1540) 0x432978 ORR X10, XZR, XZR |
(1540) 0x43297c MOVZ W11, #1 |
(1540) 0x432980 B 432994 |
(1547) 0x432984 ADD X10, X10, #1 |
(1547) 0x432988 CMP X10, X20 |
(1547) 0x43298c STR X10, [SP, #560] |
(1547) 0x432990 B.GE 4329bc |
(1547) 0x432994 LDR X12, [X8, X10,LSL #3] |
(1547) 0x432998 LDR X13, [X9, X12,LSL #3] |
(1547) 0x43299c CBNZ X13, 432984 |
(1547) 0x4329a0 LDR X10, [SP, #472] |
(1547) 0x4329a4 ADD X10, X10, #1 |
(1547) 0x4329a8 STR X10, [SP, #472] |
(1547) 0x4329ac STR X11, [X9, X12,LSL #3] |
(1547) 0x4329b0 LDR X10, [SP, #560] |
(1547) 0x4329b4 LDR X20, [SP, #496] |
(1547) 0x4329b8 B 432984 |
(1540) 0x4329bc LDR X20, [SP, #472] |
(1540) 0x4329c0 LDR X24, [SP, #640] |
(1540) 0x4329c4 B 4329cc |
(1540) 0x4329c8 ORR X20, XZR, XZR |
(1540) 0x4329cc ORR X0, XZR, X20 |
(1540) 0x4329d0 MOVZ W1, #8 |
(1540) 0x4329d4 BL 4a2570 |
(1540) 0x4329d8 LDR X8, [SP, #704] |
(1540) 0x4329dc STR X0, [SP, #672] |
(1540) 0x4329e0 ORR X21, XZR, X0 |
(1540) 0x4329e4 MOVZ W1, #8 |
(1540) 0x4329e8 ADD X8, X8, X24,LSL #3 |
(1540) 0x4329ec LDUR X0, [X8, #504] |
(1540) 0x4329f0 BL 4a2570 |
(1540) 0x4329f4 STR X0, [SP, #664] |
(1540) 0x4329f8 ADRP X0, |
(1540) 0x4329fc ADD X0, X0, #952 |
(1540) 0x432a00 ADRP X2, 436a00 |
(1540) 0x432a04 ADD X2, X2, #2336 |
(1540) 0x432a08 ADD X3, SP, #704 |
(1540) 0x432a0c ADD X4, SP, #640 |
(1540) 0x432a10 ADD X5, SP, #664 |
(1540) 0x432a14 MOVZ W1, #3 |
(1540) 0x432a18 BL 40f670 |
(1540) 0x432a1c LDR X13, [SP, #640] |
(1540) 0x432a20 STR XZR, [SP, #560] |
(1540) 0x432a24 CMP X13, #1 |
(1540) 0x432a28 B.LE 432ac8 |
(1540) 0x432a2c LDR X9, [SP, #704] |
(1540) 0x432a30 LDUR X10, [X29, #272] |
(1540) 0x432a34 LDR X17, [SP, #432] |
(1540) 0x432a38 ORR X8, XZR, XZR |
(1540) 0x432a3c ORR X11, XZR, XZR |
(1540) 0x432a40 B 432a5c |
(1545) 0x432a44 LDR X13, [SP, #640] |
(1545) 0x432a48 SUB X11, X13, #1 |
(1545) 0x432a4c STR X15, [SP, #560] |
(1545) 0x432a50 CMP X15, X11 |
(1545) 0x432a54 ORR X11, XZR, X15 |
(1545) 0x432a58 B.GE 432ac0 |
(1545) 0x432a5c ADD X15, X11, #1 |
(1545) 0x432a60 LDR X12, [X9, X11,LSL #3] |
(1545) 0x432a64 LDR X14, [X9, X15,LSL #3] |
(1545) 0x432a68 CMP X12, X14 |
(1545) 0x432a6c B.GE 432a48 |
(1545) 0x432a70 LDR X13, [SP, #672] |
(1545) 0x432a74 LDR X14, [SP, #664] |
(1545) 0x432a78 B 432a94 |
0x432a7c HINT #0 |
(1546) 0x432a80 ADD X15, X11, #1 |
(1546) 0x432a84 ADD X12, X12, #1 |
(1546) 0x432a88 LDR X16, [X9, X15,LSL #3] |
(1546) 0x432a8c CMP X12, X16 |
(1546) 0x432a90 B.GE 432a44 |
(1546) 0x432a94 LDR X15, [X10, X12,LSL #3] |
(1546) 0x432a98 CBZ X15, 432a80 |
(1546) 0x432a9c LDR X15, [X17, X11,LSL #3] |
(1546) 0x432aa0 LDR X11, [X9, X11,LSL #3] |
(1546) 0x432aa4 SUB X11, X15, X11,LSL #3 |
(1546) 0x432aa8 LDR X11, [X11, X12,LSL #3] |
(1546) 0x432aac STR X11, [X13, X8,LSL #3] |
(1546) 0x432ab0 STR X11, [X14, X12,LSL #3] |
(1546) 0x432ab4 ADD X8, X8, #1 |
(1546) 0x432ab8 LDR X11, [SP, #560] |
(1546) 0x432abc B 432a80 |
(1540) 0x432ac0 LDR X21, [SP, #672] |
(1540) 0x432ac4 LDR X20, [SP, #472] |
(1540) 0x432ac8 ORR X0, XZR, X21 |
(1540) 0x432acc ORR X1, XZR, XZR |
(1540) 0x432ad0 SUB X2, X20, #1 |
(1540) 0x432ad4 BL 4a2d10 |
(1540) 0x432ad8 ADRP X0, |
(1540) 0x432adc ADD X0, X0, #1024 |
(1540) 0x432ae0 ADRP X2, 436ae0 |
(1540) 0x432ae4 ADD X2, X2, #2592 |
(1540) 0x432ae8 ADD X3, SP, #704 |
(1540) 0x432aec ADD X4, SP, #640 |
(1540) 0x432af0 ADD X5, SP, #664 |
(1540) 0x432af4 ADD X6, SP, #672 |
(1540) 0x432af8 ADD X7, SP, #472 |
(1540) 0x432afc MOVZ W1, #5 |
(1540) 0x432b00 BL 40f670 |
(1540) 0x432b04 ADRP X0, |
(1540) 0x432b08 ADD X0, X0, #1096 |
(1540) 0x432b0c ADRP X2, 436b0c |
(1540) 0x432b10 ADD X2, X2, #2848 |
(1540) 0x432b14 ADD X3, SP, #496 |
(1540) 0x432b18 SUB X4, X29, #176 |
(1540) 0x432b1c ADD X5, SP, #664 |
(1540) 0x432b20 MOVZ W1, #3 |
(1540) 0x432b24 BL 40f670 |
(1540) 0x432b28 LDUR X0, [X29, #272] |
(1540) 0x432b2c BL 4a2670 |
(1540) 0x432b30 STUR XZR, [X29, #272] |
(1540) 0x432b34 LDR X8, [SP, #528] |
(1540) 0x432b38 CMP X8, #2 |
(1540) 0x432b3c B.LT 432b8c |
(1540) 0x432b40 LDR X8, [SP, #640] |
(1540) 0x432b44 STR XZR, [SP, #560] |
(1540) 0x432b48 CMP X8, #2 |
(1540) 0x432b4c B.LT 432b8c |
(1540) 0x432b50 LDR X10, [SP, #432] |
(1540) 0x432b54 ORR X8, XZR, XZR |
(1540) 0x432b58 HINT #0 |
(1540) 0x432b5c HINT #0 |
(1544) 0x432b60 LDR X0, [X10, X8,LSL #3] |
(1544) 0x432b64 BL 4a2670 |
(1544) 0x432b68 LDR X10, [SP, #432] |
(1544) 0x432b6c LDR X8, [SP, #560] |
(1544) 0x432b70 STR XZR, [X10, X8,LSL #3] |
(1544) 0x432b74 ADD X8, X8, #1 |
(1544) 0x432b78 LDR X9, [SP, #640] |
(1544) 0x432b7c STR X8, [SP, #560] |
(1544) 0x432b80 SUB X9, X9, #1 |
(1544) 0x432b84 CMP X8, X9 |
(1544) 0x432b88 B.LT 432b60 |
(1540) 0x432b8c LDR X0, [SP, #664] |
(1540) 0x432b90 BL 4a2670 |
(1540) 0x432b94 LDR X0, [SP, #432] |
(1540) 0x432b98 STR XZR, [SP, #664] |
(1540) 0x432b9c BL 4a2670 |
(1540) 0x432ba0 LDR X0, [SP, #704] |
(1540) 0x432ba4 BL 4a2670 |
(1540) 0x432ba8 LDR X8, [SP, #472] |
(1540) 0x432bac STR XZR, [SP, #704] |
(1540) 0x432bb0 CBZ X8, 432bc0 |
(1540) 0x432bb4 LDR X9, [SP, #672] |
(1540) 0x432bb8 STR X9, [X19, #88] |
(1540) 0x432bbc STR X8, [X22, #24] |
(1540) 0x432bc0 LDR X20, [X29, #112] |
(1540) 0x432bc4 LDR X8, [SP, #608] |
(1540) 0x432bc8 CBZ X8, 432bec |
(1540) 0x432bcc ADRP X0, |
(1540) 0x432bd0 ADD X0, X0, #1168 |
(1540) 0x432bd4 ADRP X2, 436bd4 |
(1540) 0x432bd8 ADD X2, X2, #3120 |
(1540) 0x432bdc ADD X3, SP, #632 |
(1540) 0x432be0 SUB X4, X29, #8 |
(1540) 0x432be4 MOVZ W1, #2 |
(1540) 0x432be8 BL 40f670 |
(1540) 0x432bec LDR X8, [SP, #528] |
(1540) 0x432bf0 CMP X8, #2 |
(1540) 0x432bf4 B.LT 432c00 |
(1540) 0x432bf8 ORR X0, XZR, X19 |
(1540) 0x432bfc BL 47d700 |
(1540) 0x432c00 STR X19, [X20] |
(1540) 0x432c04 ORR X0, XZR, XZR |
(1540) 0x432c08 ADD SP, SP, #1008 |
(1540) 0x432c0c LDP X20, X19, [SP, #96] |
(1540) 0x432c10 LDP X22, X21, [SP, #80] |
(1540) 0x432c14 LDP X24, X23, [SP, #64] |
(1540) 0x432c18 LDP X26, X25, [SP, #48] |
(1540) 0x432c1c LDP X28, X27, [SP, #32] |
(1540) 0x432c20 LDP X29, X30, [SP, #16] |
(1540) 0x432c24 LDR D8, [SP], #112 |
(1540) 0x432c28 RET |
(1540) 0x432c2c ORR X8, XZR, XZR |
(1540) 0x432c30 STR X8, [X0, #8] |
(1540) 0x432c34 ORR X0, XZR, X21 |
(1540) 0x432c38 MOVZ W1, #8 |
(1540) 0x432c3c BL 4a2570 |
(1540) 0x432c40 ORR X19, XZR, X0 |
(1540) 0x432c44 ADD X0, X21, #1 |
(1540) 0x432c48 MOVZ W1, #8 |
(1540) 0x432c4c BL 4a2570 |
(1540) 0x432c50 STR X0, [SP, #704] |
(1540) 0x432c54 STR XZR, [X0] |
(1540) 0x432c58 ORR X30, XZR, X19 |
(1540) 0x432c5c LDR X8, [SP, #616] |
(1540) 0x432c60 STR X8, [X0, #8] |
(1540) 0x432c64 STR X8, [SP, #480] |
(1540) 0x432c68 STR X26, [X19] |
(1540) 0x432c6c LDR X9, [SP, #752] |
(1540) 0x432c70 LDR X21, [SP, #424] |
(1540) 0x432c74 LDP X1, X8, [X9, #8] |
(1540) 0x432c78 CMP X1, X8 |
(1540) 0x432c7c STR X1, [SP, #560] |
(1540) 0x432c80 B.GE 4310a0 |
(1541) 0x432c84 LDR X11, [SP, #760] |
(1541) 0x432c88 LDR X12, [SP, #744] |
(1541) 0x432c8c LDR X13, [SP, #736] |
(1541) 0x432c90 ORR X8, XZR, XZR |
(1541) 0x432c94 ORR X10, XZR, XZR |
(1541) 0x432c98 LDP X15, X14, [X29, #920] |
(1541) 0x432c9c LDUR X16, [X29, #504] |
(1541) 0x432ca0 LDP X18, X17, [X29, #904] |
(1541) 0x432ca4 LDUR X0, [X29, #288] |
(1541) 0x432ca8 B 432cc4 |
(1541) 0x432cac LDR X1, [SP, #560] |
(1541) 0x432cb0 LDR X2, [X9, #16] |
(1541) 0x432cb4 ADD X1, X1, #1 |
(1541) 0x432cb8 CMP X1, X2 |
(1541) 0x432cbc STR X1, [SP, #560] |
(1541) 0x432cc0 B.GE 4310a8 |
(1541) 0x432cc4 LDR X2, [X11, X1,LSL #3] |
(1541) 0x432cc8 STR X10, [X12, X2,LSL #3] |
(1541) 0x432ccc STR X8, [X13, X2,LSL #3] |
(1541) 0x432cd0 ADD X1, X2, #1 |
(1541) 0x432cd4 LDR X3, [X14, X2,LSL #3] |
(1541) 0x432cd8 LDR X5, [X14, X1,LSL #3] |
(1541) 0x432cdc CMP X3, X5 |
(1541) 0x432ce0 B.GE 432d40 |
(1541) 0x432ce4 LDR X4, [SP, #592] |
(1541) 0x432ce8 LDR X6, [SP, #728] |
(1541) 0x432cec B 432d0c |
0x432cf0 HINT #0 |
0x432cf4 HINT #0 |
0x432cf8 HINT #0 |
0x432cfc HINT #0 |
(1543) 0x432d00 ADD X3, X3, #1 |
(1543) 0x432d04 CMP X3, X5 |
(1543) 0x432d08 B.GE 432d40 |
(1543) 0x432d0c LDR X7, [X15, X3,LSL #3] |
(1543) 0x432d10 LDR X19, [X16, X7,LSL #3] |
(1543) 0x432d14 CMP X19, #1 |
(1543) 0x432d18 B.NE 432d00 |
(1543) 0x432d1c LDR X5, [X4, X7,LSL #3] |
(1543) 0x432d20 LDR X7, [X6, #8] |
(1543) 0x432d24 STR X5, [X7, X10,LSL #3] |
(1543) 0x432d28 ADD X10, X10, #1 |
(1543) 0x432d2c LDR X5, [X14, X1,LSL #3] |
(1543) 0x432d30 B 432d00 |
0x432d34 HINT #0 |
0x432d38 HINT #0 |
0x432d3c HINT #0 |
(1541) 0x432d40 LDR X2, [X17, X2,LSL #3] |
(1541) 0x432d44 LDR X4, [X17, X1,LSL #3] |
(1541) 0x432d48 CMP X2, X4 |
(1541) 0x432d4c B.GE 432cac |
(1542) 0x432d50 LDR X3, [SP, #688] |
(1542) 0x432d54 LDR X5, [SP, #720] |
(1542) 0x432d58 B 432d6c |
0x432d5c HINT #0 |
(1542) 0x432d60 ADD X2, X2, #1 |
(1542) 0x432d64 CMP X2, X4 |
(1542) 0x432d68 B.GE 432cac |
(1542) 0x432d6c LDR X6, [X18, X2,LSL #3] |
(1542) 0x432d70 LDR X7, [X0, X6,LSL #3] |
(1542) 0x432d74 CMP X7, #1 |
(1542) 0x432d78 B.NE 432d60 |
(1542) 0x432d7c LDR X4, [X3, X6,LSL #3] |
(1542) 0x432d80 LDR X6, [X5, #8] |
(1542) 0x432d84 STR X4, [X6, X8,LSL #3] |
(1542) 0x432d88 ADD X8, X8, #1 |
(1542) 0x432d8c LDR X4, [X17, X1,LSL #3] |
(1542) 0x432d90 B 432d60 |
0x432d94 HINT #0 |
0x432d98 HINT #0 |
0x432d9c HINT #0 |
| Coverage (%) | Name | Source Location | Module |
|---|
| Path / |
| Source file and lines | par_multi_interp.c:41-2060 |
| Module | exec |
| nb instructions | 566 |
| loop length | 2264 |
| nb stack references | 0 |
| front end | 61.13 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 48.00 | 48.00 | 51.50 | 51.50 | 51.50 | 51.50 | 0.50 | 0.50 | 0.50 | 0.50 | 76.67 | 76.67 | 76.67 | 55.50 | 55.50 |
| cycles | 48.00 | 48.00 | 51.50 | 51.50 | 51.50 | 51.50 | 0.50 | 0.50 | 0.50 | 0.50 | 76.67 | 76.67 | 76.67 | 55.50 | 55.50 |
| Cycles executing div or sqrt instructions | NA |
| Front-end | 61.13 |
| Overall L1 | 76.67 |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| STR D8, [SP, #400]! | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
| STP X29, X30, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X28, X27, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X26, X25, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X24, X23, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X22, X21, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X20, X19, [SP, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ADD X29, SP, #16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB SP, SP, #1008 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDP X22, X23, [X0, #56] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| STUR X1, [X29, #504] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X5, X4, [X29, #984] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X10, [X0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| FMOV D8, D0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| LDR X24, [X0, #88] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X26, [X2, #88] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STP X7, X0, [SP, #304] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| MOVZ W0, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X3, [SP, #320] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X8, [X22, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X21, [X23, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STUR X8, [X29, #464] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDP X8, X9, [X22] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| STP XZR, X9, [X29, #952] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STUR X8, [X29, #456] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X8, [X23] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STP XZR, X8, [X29, #936] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDP X8, X25, [X2, #56] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDP X9, X8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDR X28, [X25, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STP X8, X9, [X29, #920] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X9, [X2, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X8, [X25] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STUR XZR, [X29, #392] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STUR XZR, [X29, #352] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP XZR, XZR, [X29, #840] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP XZR, XZR, [X29, #808] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP XZR, XZR, [X29, #792] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STUR XZR, [X29, #272] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STUR XZR, [X29, #256] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #760] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #752] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #736] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #720] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #712] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #704] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #696] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #688] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #680] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #672] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #664] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #624] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #616] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #608] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #600] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #592] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #584] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #576] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #568] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #480] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X9, X10, [SP, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STUR X8, [X29, #400] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| MOVN X8, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STP X8, XZR, [SP, #488] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X19, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X0, [SP, #456] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 4a46e0 <hypre_NumThreads> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X0, [X19] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #448] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ORR X20, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X0, [X19] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #440] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X8, [X19] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 430450 <hypre_BoomerAMGBuildMultipass+0x170> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X8, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X19, [SP, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X1, SP, #528 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X0, XZR, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a3b70 <hypre_MPI_Comm_size> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X1, SP, #536 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a3ba0 <hypre_MPI_Comm_rank> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X9, [SP, #528] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X8, [SP, #536] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUB X3, X9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CMP X8, X3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.NE 43048c <hypre_BoomerAMGBuildMultipass+0x1ac> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #320] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X8, [X8, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X8, [SP, #520] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X8, [SP, #320] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADRP X2, <4df490> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X0, SP, #520 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X27, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X2, [X2, #4000] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X4, [SP, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| BL 4a4170 <hypre_MPI_Bcast> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CBZ X8, 430584 <hypre_BoomerAMGBuildMultipass+0x2a4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [X29, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| CSEL X8, X21, X28, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CSEL X20, X24, X26, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STUR X8, [X29, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CBZ X21, 4304dc <hypre_BoomerAMGBuildMultipass+0x1fc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X9, [X23, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STUR X9, [X29, #440] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X9, [X23, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STUR X9, [X29, #424] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CBZ X8, 4304e8 <hypre_BoomerAMGBuildMultipass+0x208> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [X25, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STUR X8, [X29, #392] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X0, [X22, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X0, [SP, #632] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CBZ X0, 430500 <hypre_BoomerAMGBuildMultipass+0x220> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #592] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ADRP X0, <4dc500> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X0, X0, #208 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADRP X2, 432508 <hypre_BoomerAMGBuildMultipass+0x2228> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X2, X2, #3536 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR XZR, [SP, #624] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #608] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ADD X3, SP, #632 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB X4, X29, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X5, SP, #624 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X6, SP, #608 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 40f670 <@plt_start@+0x210> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X9, [SP, #624] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X10, [SP, #608] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X8, [SP, #632] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X9, X10, X9 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUBS X28, X8, X9 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.EQ 430558 <hypre_BoomerAMGBuildMultipass+0x278> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, X28 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #760] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| MOVZ W0, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #752] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X0, [SP, #632] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CBZ X0, 4305c8 <hypre_BoomerAMGBuildMultipass+0x2e8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #632] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X0, [SP, #584] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| B 4305cc <hypre_BoomerAMGBuildMultipass+0x2ec> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #312] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X8, [X8, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X8, [SP, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CBNZ X8, 4305a8 <hypre_BoomerAMGBuildMultipass+0x2c8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X19, [SP, #312] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X0, XZR, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 47d700 <hypre_MatvecCommPkgCreate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [X19, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X8, [SP, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ORR X8, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR XZR, [X29, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X8, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| CSEL X8, X21, X28, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CSEL X20, X24, X26, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STUR X8, [X29, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CBNZ X21, 4304cc <hypre_BoomerAMGBuildMultipass+0x1ec> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| B 4304dc <hypre_BoomerAMGBuildMultipass+0x1fc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X8, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X0, X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #632] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STUR X0, [X29, #368] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X0, X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STUR X0, [X29, #344] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X0, [SP, #624] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CBZ X0, 430604 <hypre_BoomerAMGBuildMultipass+0x324> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STUR X0, [X29, #264] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDUR X0, [X29, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CBZ X0, 430634 <hypre_BoomerAMGBuildMultipass+0x354> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDUR X8, [X29, #480] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STUR X0, [X29, #288] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X8, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 430634 <hypre_BoomerAMGBuildMultipass+0x354> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDUR X0, [X29, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STUR X0, [X29, #280] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X8, [SP, #528] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LE 430690 <hypre_BoomerAMGBuildMultipass+0x3b0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X11, [SP, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDP X8, X9, [X11, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| STR X9, [SP, #336] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDP X9, X10, [X11, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| STUR X10, [X29, #312] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X10, [X11, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STP X9, X8, [X29, #832] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X0, [X9, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X10, [SP, #416] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDP X10, X19, [X11, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| STR X10, [SP, #328] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CBZ X0, 4306ac <hypre_BoomerAMGBuildMultipass+0x3cc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X25, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDUR X13, [X29, #328] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR XZR, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X13, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GE 4306c0 <hypre_BoomerAMGBuildMultipass+0x3e0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| B 430730 <hypre_BoomerAMGBuildMultipass+0x450> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR XZR, [SP, #416] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ORR X25, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDUR X13, [X29, #328] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR XZR, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X13, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GE 4306c0 <hypre_BoomerAMGBuildMultipass+0x3e0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| B 430730 <hypre_BoomerAMGBuildMultipass+0x450> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X25, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDUR X13, [X29, #328] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR XZR, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X13, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 430730 <hypre_BoomerAMGBuildMultipass+0x450> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X11, X8, [X29, #824] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDUR X9, [X29, #504] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X10, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X12, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 4306ec <hypre_BoomerAMGBuildMultipass+0x40c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| LDR X8, [SP, #528] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LE 430754 <hypre_BoomerAMGBuildMultipass+0x474> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDUR X3, [X29, #288] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X1, [SP, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X2, XZR, X25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W0, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 47cbc0 <hypre_ParCSRCommHandleCreate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| BL 47cfa0 <hypre_ParCSRCommHandleDestroy> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDUR X8, [X29, #480] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 4307f8 <hypre_BoomerAMGBuildMultipass+0x518> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDUR X13, [X29, #328] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR XZR, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X13, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 4307d4 <hypre_BoomerAMGBuildMultipass+0x4f4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X11, X8, [X29, #824] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDUR X9, [X29, #472] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X10, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X12, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 430790 <hypre_BoomerAMGBuildMultipass+0x4b0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #528] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LE 4307f8 <hypre_BoomerAMGBuildMultipass+0x518> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDUR X3, [X29, #280] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X1, [SP, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X2, XZR, X25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W0, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 47cbc0 <hypre_ParCSRCommHandleCreate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| BL 47cfa0 <hypre_ParCSRCommHandleDestroy> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ADRP X0, <4dc7f8> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X0, X0, #304 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADRP X2, 432800 <hypre_BoomerAMGBuildMultipass+0x2520> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X2, X2, #4048 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X19, [SP, #424] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #616] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #600] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| SUB X3, X29, #128 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB X4, X29, #224 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X5, SP, #616 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X6, SP, #600 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 40f670 <@plt_start@+0x210> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDUR X0, [X29, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CBZ X0, 430874 <hypre_BoomerAMGBuildMultipass+0x594> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #576] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDUR X0, [X29, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #688] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDUR X0, [X29, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X19, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X0, [SP, #616] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X26, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 43087c <hypre_BoomerAMGBuildMultipass+0x59c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X19, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X26, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDUR X12, [X29, #368] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUB X23, X28, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR XZR, [X12] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDUR X13, [X29, #344] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR XZR, [X13] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X8, [SP, #632] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 430974 <hypre_BoomerAMGBuildMultipass+0x694> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDUR X8, [X29, #504] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X9, [SP, #760] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X10, [SP, #584] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X11, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X18, XZR, X23 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X15, [SP, #592] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDUR X17, [X29, #264] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X12, X12, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X13, X13, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVN X14, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W16, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 430920 <hypre_BoomerAMGBuildMultipass+0x640> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| LDUR X13, [X29, #328] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR XZR, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X13, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 4309fc <hypre_BoomerAMGBuildMultipass+0x71c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X11, X9, [X29, #824] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDR X10, [SP, #592] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X8, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X12, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 4309ac <hypre_BoomerAMGBuildMultipass+0x6cc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| LDR X8, [SP, #528] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LE 430a20 <hypre_BoomerAMGBuildMultipass+0x740> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X1, [SP, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X2, XZR, X25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X3, XZR, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W0, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 47cbc0 <hypre_ParCSRCommHandleCreate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| BL 47cfa0 <hypre_ParCSRCommHandleDestroy> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #416] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X0, X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X0, [SP, #344] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X22, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X0, [SP, #616] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CBZ X0, 430a4c <hypre_BoomerAMGBuildMultipass+0x76c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STUR X0, [X29, #256] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X8, [SP, #416] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR XZR, [X22] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 430b1c <hypre_BoomerAMGBuildMultipass+0x83c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDUR X9, [X29, #288] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X8, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X10, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVN X11, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 430a90 <hypre_BoomerAMGBuildMultipass+0x7b0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| ORR X0, XZR, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2670 <hypre_Free> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [X29, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CBZ X8, 430bb4 <hypre_BoomerAMGBuildMultipass+0x8d4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, X21 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| CMP X21, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| STR X0, [SP, #680] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| B.LT 430bb4 <hypre_BoomerAMGBuildMultipass+0x8d4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X8, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X9, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 430b8c <hypre_BoomerAMGBuildMultipass+0x8ac> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| LDR X8, [SP, #752] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X22, [SP, #296] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ORR X22, XZR, X23 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CMP X28, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| STP XZR, XZR, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #512] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X9, [SP, #624] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X23, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR X9, [SP, #656] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| B.LT 430d0c <hypre_BoomerAMGBuildMultipass+0xa2c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X9, [SP, #760] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDP X11, X10, [X29, #920] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDUR X12, [X29, #504] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X19, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X23, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X20, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDP X14, X13, [X29, #904] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDUR X15, [X29, #288] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X17, [SP, #584] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X18, XZR, X22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W16, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 430c20 <hypre_BoomerAMGBuildMultipass+0x940> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| ORR X20, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X23, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X19, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDUR X13, [X29, #328] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X23, [X8, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X13, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 430d90 <hypre_BoomerAMGBuildMultipass+0xab0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X11, X8, [X29, #824] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDR X9, [SP, #584] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X10, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X12, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 430d4c <hypre_BoomerAMGBuildMultipass+0xa6c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #528] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LE 430db4 <hypre_BoomerAMGBuildMultipass+0xad4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X3, [SP, #576] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X1, [SP, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X2, XZR, X25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W0, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 47cbc0 <hypre_ParCSRCommHandleCreate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| BL 47cfa0 <hypre_ParCSRCommHandleDestroy> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOVZ W8, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADRP X3, <4dfdb8> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADRP X4, <4dfdbc> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X0, SP, #544 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X8, [SP, #648] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| SUB X8, X28, X23 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X1, SP, #552 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W2, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X8, [SP, #544] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X3, [X3, #4000] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X4, [X4, #4032] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X5, [SP, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| BL 4a43b0 <hypre_MPI_Allreduce> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #552] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CBZ X8, 430ff8 <hypre_BoomerAMGBuildMultipass+0xd18> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #648] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #9 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 430ff8 <hypre_BoomerAMGBuildMultipass+0xd18> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ADRP X21, <4dfdfc> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADRP X24, <4dfe00> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X21, [X21, #4000] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X24, [X24, #4032] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| HINT #0 | ||||||||||||||||||
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| ORR X0, XZR, X25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2670 <hypre_Free> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X21, [SP, #648] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X0, XZR, X21 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X21, [SP, #640] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #728] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ORR X0, XZR, X20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #728] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X0, [X8, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X0, [SP, #632] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #744] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X0, [SP, #632] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #528] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X0, [SP, #736] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X8, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 431084 <hypre_BoomerAMGBuildMultipass+0xda4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, X21 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #720] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CBZ X19, 432c2c <hypre_BoomerAMGBuildMultipass+0x294c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X8, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X0, [SP, #720] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| B 432c30 <hypre_BoomerAMGBuildMultipass+0x2950> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X30, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X9, [SP, #752] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X21, [SP, #424] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDP X1, X8, [X9, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| CMP X1, X8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| STR X1, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| B.LT 432c84 <hypre_BoomerAMGBuildMultipass+0x29a4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| HINT #0 | ||||||||||||||||||
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| Source file and lines | par_multi_interp.c:41-2060 |
| Module | exec |
| nb instructions | 566 |
| loop length | 2264 |
| nb stack references | 0 |
| front end | 61.13 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 48.00 | 48.00 | 51.50 | 51.50 | 51.50 | 51.50 | 0.50 | 0.50 | 0.50 | 0.50 | 76.67 | 76.67 | 76.67 | 55.50 | 55.50 |
| cycles | 48.00 | 48.00 | 51.50 | 51.50 | 51.50 | 51.50 | 0.50 | 0.50 | 0.50 | 0.50 | 76.67 | 76.67 | 76.67 | 55.50 | 55.50 |
| Cycles executing div or sqrt instructions | NA |
| Front-end | 61.13 |
| Overall L1 | 76.67 |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| STR D8, [SP, #400]! | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
| STP X29, X30, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X28, X27, [SP, #32] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X26, X25, [SP, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X24, X23, [SP, #64] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X22, X21, [SP, #80] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X20, X19, [SP, #96] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ADD X29, SP, #16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB SP, SP, #1008 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDP X22, X23, [X0, #56] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| STUR X1, [X29, #504] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X5, X4, [X29, #984] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X10, [X0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| FMOV D8, D0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| LDR X24, [X0, #88] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X26, [X2, #88] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STP X7, X0, [SP, #304] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| MOVZ W0, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X3, [SP, #320] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X8, [X22, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X21, [X23, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STUR X8, [X29, #464] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDP X8, X9, [X22] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| STP XZR, X9, [X29, #952] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STUR X8, [X29, #456] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X8, [X23] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STP XZR, X8, [X29, #936] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDP X8, X25, [X2, #56] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDP X9, X8, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDR X28, [X25, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STP X8, X9, [X29, #920] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X9, [X2, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X8, [X25] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STUR XZR, [X29, #392] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STUR XZR, [X29, #352] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP XZR, XZR, [X29, #840] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP XZR, XZR, [X29, #808] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP XZR, XZR, [X29, #792] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STUR XZR, [X29, #272] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STUR XZR, [X29, #256] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #760] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #752] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #736] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #720] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #712] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #704] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #696] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #688] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #680] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #672] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #664] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #624] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #616] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #608] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #600] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #592] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #584] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #576] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #568] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #480] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STP X9, X10, [SP, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STUR X8, [X29, #400] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| MOVN X8, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STP X8, XZR, [SP, #488] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X19, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X0, [SP, #456] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 4a46e0 <hypre_NumThreads> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X0, [X19] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #448] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ORR X20, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X0, [X19] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #440] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X8, [X19] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 430450 <hypre_BoomerAMGBuildMultipass+0x170> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X8, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X19, [SP, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X1, SP, #528 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X0, XZR, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a3b70 <hypre_MPI_Comm_size> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X1, SP, #536 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a3ba0 <hypre_MPI_Comm_rank> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X9, [SP, #528] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X8, [SP, #536] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUB X3, X9, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CMP X8, X3 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.NE 43048c <hypre_BoomerAMGBuildMultipass+0x1ac> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #320] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X8, [X8, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X8, [SP, #520] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X8, [SP, #320] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADRP X2, <4df490> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X0, SP, #520 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X27, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X2, [X2, #4000] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X4, [SP, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| BL 4a4170 <hypre_MPI_Bcast> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CBZ X8, 430584 <hypre_BoomerAMGBuildMultipass+0x2a4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [X29, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| CSEL X8, X21, X28, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CSEL X20, X24, X26, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STUR X8, [X29, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CBZ X21, 4304dc <hypre_BoomerAMGBuildMultipass+0x1fc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X9, [X23, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STUR X9, [X29, #440] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X9, [X23, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STUR X9, [X29, #424] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CBZ X8, 4304e8 <hypre_BoomerAMGBuildMultipass+0x208> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [X25, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STUR X8, [X29, #392] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X0, [X22, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X0, [SP, #632] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CBZ X0, 430500 <hypre_BoomerAMGBuildMultipass+0x220> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #592] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ADRP X0, <4dc500> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X0, X0, #208 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADRP X2, 432508 <hypre_BoomerAMGBuildMultipass+0x2228> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X2, X2, #3536 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR XZR, [SP, #624] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #608] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ADD X3, SP, #632 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB X4, X29, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X5, SP, #624 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X6, SP, #608 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 40f670 <@plt_start@+0x210> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X9, [SP, #624] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X10, [SP, #608] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X8, [SP, #632] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X9, X10, X9 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUBS X28, X8, X9 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.EQ 430558 <hypre_BoomerAMGBuildMultipass+0x278> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, X28 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #760] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| MOVZ W0, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #752] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X0, [SP, #632] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CBZ X0, 4305c8 <hypre_BoomerAMGBuildMultipass+0x2e8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #632] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X0, [SP, #584] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| B 4305cc <hypre_BoomerAMGBuildMultipass+0x2ec> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #312] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X8, [X8, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X8, [SP, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CBNZ X8, 4305a8 <hypre_BoomerAMGBuildMultipass+0x2c8> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X19, [SP, #312] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X0, XZR, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 47d700 <hypre_MatvecCommPkgCreate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [X19, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X8, [SP, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ORR X8, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR XZR, [X29, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X8, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| CSEL X8, X21, X28, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CSEL X20, X24, X26, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STUR X8, [X29, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CBNZ X21, 4304cc <hypre_BoomerAMGBuildMultipass+0x1ec> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| B 4304dc <hypre_BoomerAMGBuildMultipass+0x1fc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X8, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X0, X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #632] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STUR X0, [X29, #368] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X0, X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STUR X0, [X29, #344] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X0, [SP, #624] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CBZ X0, 430604 <hypre_BoomerAMGBuildMultipass+0x324> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STUR X0, [X29, #264] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDUR X0, [X29, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CBZ X0, 430634 <hypre_BoomerAMGBuildMultipass+0x354> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDUR X8, [X29, #480] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STUR X0, [X29, #288] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X8, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 430634 <hypre_BoomerAMGBuildMultipass+0x354> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDUR X0, [X29, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STUR X0, [X29, #280] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X8, [SP, #528] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LE 430690 <hypre_BoomerAMGBuildMultipass+0x3b0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X11, [SP, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDP X8, X9, [X11, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| STR X9, [SP, #336] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDP X9, X10, [X11, #24] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| STUR X10, [X29, #312] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X10, [X11, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STP X9, X8, [X29, #832] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X0, [X9, X8,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X10, [SP, #416] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDP X10, X19, [X11, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| STR X10, [SP, #328] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CBZ X0, 4306ac <hypre_BoomerAMGBuildMultipass+0x3cc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X25, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDUR X13, [X29, #328] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR XZR, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X13, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GE 4306c0 <hypre_BoomerAMGBuildMultipass+0x3e0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| B 430730 <hypre_BoomerAMGBuildMultipass+0x450> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR XZR, [SP, #416] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ORR X25, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDUR X13, [X29, #328] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR XZR, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X13, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GE 4306c0 <hypre_BoomerAMGBuildMultipass+0x3e0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| B 430730 <hypre_BoomerAMGBuildMultipass+0x450> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X25, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDUR X13, [X29, #328] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR XZR, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X13, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 430730 <hypre_BoomerAMGBuildMultipass+0x450> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X11, X8, [X29, #824] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDUR X9, [X29, #504] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X10, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X12, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 4306ec <hypre_BoomerAMGBuildMultipass+0x40c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| LDR X8, [SP, #528] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LE 430754 <hypre_BoomerAMGBuildMultipass+0x474> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDUR X3, [X29, #288] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X1, [SP, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X2, XZR, X25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W0, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 47cbc0 <hypre_ParCSRCommHandleCreate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| BL 47cfa0 <hypre_ParCSRCommHandleDestroy> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDUR X8, [X29, #480] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 4307f8 <hypre_BoomerAMGBuildMultipass+0x518> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDUR X13, [X29, #328] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR XZR, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X13, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 4307d4 <hypre_BoomerAMGBuildMultipass+0x4f4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X11, X8, [X29, #824] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDUR X9, [X29, #472] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X10, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X12, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 430790 <hypre_BoomerAMGBuildMultipass+0x4b0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #528] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LE 4307f8 <hypre_BoomerAMGBuildMultipass+0x518> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDUR X3, [X29, #280] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X1, [SP, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X2, XZR, X25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W0, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 47cbc0 <hypre_ParCSRCommHandleCreate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| BL 47cfa0 <hypre_ParCSRCommHandleDestroy> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ADRP X0, <4dc7f8> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X0, X0, #304 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADRP X2, 432800 <hypre_BoomerAMGBuildMultipass+0x2520> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X2, X2, #4048 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X19, [SP, #424] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #616] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #600] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| SUB X3, X29, #128 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| SUB X4, X29, #224 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X5, SP, #616 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X6, SP, #600 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 40f670 <@plt_start@+0x210> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDUR X0, [X29, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CBZ X0, 430874 <hypre_BoomerAMGBuildMultipass+0x594> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #576] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDUR X0, [X29, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #688] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDUR X0, [X29, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X19, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X0, [SP, #616] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X26, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 43087c <hypre_BoomerAMGBuildMultipass+0x59c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X19, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X26, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDUR X12, [X29, #368] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| SUB X23, X28, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR XZR, [X12] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDUR X13, [X29, #344] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR XZR, [X13] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X8, [SP, #632] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 430974 <hypre_BoomerAMGBuildMultipass+0x694> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDUR X8, [X29, #504] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X9, [SP, #760] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X10, [SP, #584] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X11, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X0, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X18, XZR, X23 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X15, [SP, #592] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDUR X17, [X29, #264] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X12, X12, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X13, X13, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVN X14, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W16, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 430920 <hypre_BoomerAMGBuildMultipass+0x640> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| LDUR X13, [X29, #328] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR XZR, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X13, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 4309fc <hypre_BoomerAMGBuildMultipass+0x71c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X11, X9, [X29, #824] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDR X10, [SP, #592] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X8, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X12, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 4309ac <hypre_BoomerAMGBuildMultipass+0x6cc> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| LDR X8, [SP, #528] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LE 430a20 <hypre_BoomerAMGBuildMultipass+0x740> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X1, [SP, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X2, XZR, X25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X3, XZR, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W0, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 47cbc0 <hypre_ParCSRCommHandleCreate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| BL 47cfa0 <hypre_ParCSRCommHandleDestroy> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #416] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X0, X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X0, [SP, #344] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X22, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X0, [SP, #616] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CBZ X0, 430a4c <hypre_BoomerAMGBuildMultipass+0x76c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STUR X0, [X29, #256] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X8, [SP, #416] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR XZR, [X22] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 430b1c <hypre_BoomerAMGBuildMultipass+0x83c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDUR X9, [X29, #288] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X8, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X10, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVN X11, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 430a90 <hypre_BoomerAMGBuildMultipass+0x7b0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| ORR X0, XZR, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2670 <hypre_Free> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [X29, #104] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CBZ X8, 430bb4 <hypre_BoomerAMGBuildMultipass+0x8d4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, X21 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| CMP X21, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| STR X0, [SP, #680] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| B.LT 430bb4 <hypre_BoomerAMGBuildMultipass+0x8d4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X8, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X9, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 430b8c <hypre_BoomerAMGBuildMultipass+0x8ac> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| LDR X8, [SP, #752] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X22, [SP, #296] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ORR X22, XZR, X23 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CMP X28, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| STP XZR, XZR, [X8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #512] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X9, [SP, #624] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X23, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR X9, [SP, #656] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| B.LT 430d0c <hypre_BoomerAMGBuildMultipass+0xa2c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X9, [SP, #760] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDP X11, X10, [X29, #920] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDUR X12, [X29, #504] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X19, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X23, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X20, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDP X14, X13, [X29, #904] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDUR X15, [X29, #288] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X17, [SP, #584] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X18, XZR, X22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W16, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 430c20 <hypre_BoomerAMGBuildMultipass+0x940> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| ORR X20, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X23, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X19, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDUR X13, [X29, #328] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X23, [X8, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| STR XZR, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X13, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 430d90 <hypre_BoomerAMGBuildMultipass+0xab0> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDP X11, X8, [X29, #824] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| LDR X9, [SP, #584] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X10, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X12, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 430d4c <hypre_BoomerAMGBuildMultipass+0xa6c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #528] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LE 430db4 <hypre_BoomerAMGBuildMultipass+0xad4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X3, [SP, #576] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X1, [SP, #376] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X2, XZR, X25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W0, #11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 47cbc0 <hypre_ParCSRCommHandleCreate> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| BL 47cfa0 <hypre_ParCSRCommHandleDestroy> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOVZ W8, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADRP X3, <4dfdb8> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADRP X4, <4dfdbc> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X0, SP, #544 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X8, [SP, #648] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| SUB X8, X28, X23 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X1, SP, #552 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W2, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X8, [SP, #544] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X3, [X3, #4000] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X4, [X4, #4032] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X5, [SP, #384] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| BL 4a43b0 <hypre_MPI_Allreduce> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #552] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CBZ X8, 430ff8 <hypre_BoomerAMGBuildMultipass+0xd18> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #648] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP X8, #9 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 430ff8 <hypre_BoomerAMGBuildMultipass+0xd18> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ADRP X21, <4dfdfc> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADRP X24, <4dfe00> | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X21, [X21, #4000] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X24, [X24, #4032] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| ORR X0, XZR, X25 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2670 <hypre_Free> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X21, [SP, #648] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR X0, XZR, X21 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X21, [SP, #640] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #728] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| ORR X0, XZR, X20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #728] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| STR X0, [X8, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X0, [SP, #632] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #744] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X0, [SP, #632] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X8, [SP, #528] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| STR X0, [SP, #736] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CMP X8, #2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LT 431084 <hypre_BoomerAMGBuildMultipass+0xda4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, X21 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| STR X0, [SP, #720] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| CBZ X19, 432c2c <hypre_BoomerAMGBuildMultipass+0x294c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X0, XZR, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ W1, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| BL 4a2570 <hypre_CAlloc> | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X8, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X0, [SP, #720] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| B 432c30 <hypre_BoomerAMGBuildMultipass+0x2950> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ORR X30, XZR, XZR | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X9, [SP, #752] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X21, [SP, #424] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDP X1, X8, [X9, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 1 |
| CMP X1, X8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| STR X1, [SP, #560] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| B.LT 432c84 <hypre_BoomerAMGBuildMultipass+0x29a4> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 |
| Name | Coverage (%) | Time (s) |
|---|---|---|
| ▼hypre_BoomerAMGBuildMultipass– | 0.27 | 0.1 |
| ▼Loop 1595 - par_multi_interp.c:385-400 - exec– | 0.03 | 0.65 |
| ○Loop 1596 - par_multi_interp.c:385-395 - exec | 0 | 0.03 |
| ○Loop 1594 - par_multi_interp.c:399-400 - exec | 0.01 | 0.27 |
| ▼Loop 1584 - par_multi_interp.c:488-514 - exec– | 0.01 | 0.25 |
| ○Loop 1586 - par_multi_interp.c:491-498 - exec | 0.06 | 1.28 |
| ○Loop 1585 - par_multi_interp.c:501-508 - exec | 0 | 0 |
| ▼Loop 1590 - par_multi_interp.c:440-457 - exec– | 0 | 0 |
| ▼Loop 1591 - par_multi_interp.c:440-457 - exec– | 0 | 0 |
| ○Loop 1589 - par_multi_interp.c:440-457 - exec | 0 | 0 |
| ○Loop 1601 - par_multi_interp.c:205-208 - exec | 0 | 0 |
| ▼Loop 1587 - par_multi_interp.c:466-468 - exec– | 0 | 0 |
| ○Loop 1588 - par_multi_interp.c:466-468 - exec | 0 | 0 |
| ▼Loop 1592 - par_multi_interp.c:415-423 - exec– | 0 | 0 |
| ○Loop 1593 - par_multi_interp.c:418-423 - exec | 0 | 0 |
| ▼Loop 1582 - par_multi_interp.c:526-530 - exec– | 0 | 0 |
| ○Loop 1583 - par_multi_interp.c:529-530 - exec | 0 | 0 |
| ▼Loop 1597 - par_multi_interp.c:323-327 - exec– | 0 | 0 |
| ○Loop 1598 - par_multi_interp.c:326-327 - exec | 0 | 0 |
| ▼Loop 1542 - par_multi_interp.c:628-2060 - exec– | 0 | 0 |
| ▼Loop 1541 - par_multi_interp.c:628-2060 - exec– | 0.02 | 0.51 |
| ○Loop 1543 - par_multi_interp.c:651-655 - exec | 0.06 | 1.2 |
| ▼Loop 1540 - par_multi_interp.c:628-2060 - exec– | 0 | 0 |
| ○Loop 1562 - par_multi_interp.c:1158-1161 - exec | 0.01 | 0.16 |
| ▼Loop 1555 - par_multi_interp.c:1310-1566 - exec– | 0 | 0 |
| ▼Loop 1556 - par_multi_interp.c:1324-1338 - exec– | 0 | 0 |
| ▼Loop 1557 - par_multi_interp.c:1326-1338 - exec– | 0 | 0 |
| ○Loop 1560 - par_multi_interp.c:1333-1334 - exec | 0 | 0 |
| ○Loop 1559 - par_multi_interp.c:1337-1338 - exec | 0 | 0 |
| ○Loop 1561 - par_multi_interp.c:1333-1334 - exec | 0 | 0 |
| ○Loop 1558 - par_multi_interp.c:1337-1338 - exec | 0 | 0 |
| ▼Loop 1548 - par_multi_interp.c:1674-1888 - exec– | 0 | 0 |
| ▼Loop 1549 - par_multi_interp.c:1688-1705 - exec– | 0 | 0 |
| ▼Loop 1550 - par_multi_interp.c:1690-1705 - exec– | 0 | 0 |
| ○Loop 1554 - par_multi_interp.c:1697-1699 - exec | 0 | 0 |
| ○Loop 1551 - par_multi_interp.c:1703-1705 - exec | 0 | 0 |
| ○Loop 1552 - par_multi_interp.c:1703-1705 - exec | 0 | 0 |
| ○Loop 1553 - par_multi_interp.c:1697-1699 - exec | 0 | 0 |
| ▼Loop 1563 - par_multi_interp.c:693-891 - exec– | 0 | 0 |
| ○Loop 1564 - par_multi_interp.c:872-879 - exec | 0 | 0 |
| ▼Loop 1565 - par_multi_interp.c:823-856 - exec– | 0 | 0 |
| ▼Loop 1566 - par_multi_interp.c:829-856 - exec– | 0 | 0 |
| ○Loop 1567 - par_multi_interp.c:839-843 - exec | 0 | 0 |
| ○Loop 1575 - par_multi_interp.c:703-717 - exec | 0 | 0 |
| ▼Loop 1570 - par_multi_interp.c:733-758 - exec– | 0 | 0 |
| ▼Loop 1571 - par_multi_interp.c:735-758 - exec– | 0 | 0 |
| ○Loop 1574 - par_multi_interp.c:742-745 - exec | 0 | 0 |
| ▼Loop 1572 - par_multi_interp.c:749-758 - exec– | 0 | 0 |
| ○Loop 1573 - par_multi_interp.c:753-755 - exec | 0 | 0 |
| ▼Loop 1568 - par_multi_interp.c:773-784 - exec– | 0 | 0 |
| ○Loop 1569 - par_multi_interp.c:775-780 - exec | 0 | 0 |
| ○Loop 1544 - par_multi_interp.c:2016-2017 - exec | 0 | 0 |
| ○Loop 1547 - par_multi_interp.c:1962-1968 - exec | 0 | 0 |
| ▼Loop 1545 - par_multi_interp.c:1982-1989 - exec– | 0 | 0 |
| ○Loop 1546 - par_multi_interp.c:1984-1989 - exec | 0 | 0 |
| ▼Loop 1576 - par_multi_interp.c:548-600 - exec– | 0 | 0 |
| ▼Loop 1579 - par_multi_interp.c:550-571 - exec– | 0.01 | 0.27 |
| ○Loop 1581 - par_multi_interp.c:554-557 - exec | 0.05 | 1.1 |
| ○Loop 1580 - par_multi_interp.c:568-571 - exec | 0 | 0 |
| ▼Loop 1577 - par_multi_interp.c:590-594 - exec– | 0 | 0 |
| ○Loop 1578 - par_multi_interp.c:593-594 - exec | 0 | 0 |
| ▼Loop 1599 - par_multi_interp.c:307-311 - exec– | 0 | 0 |
| ○Loop 1600 - par_multi_interp.c:310-311 - exec | 0 | 0 |