OV - exec - Function .omp

	Function: .omp_outlined..46	Module: exec	Source: par_interp.c:2726-3155 [...]	Coverage: 0.02%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_interp.c: 2726 - 3155

--------------------------------------------------------------------------------

2726: #pragma omp parallel private(i,my_thread_num,num_threads,max_coef,j,start_j,row_sum,scale,num_lost,now_checking,next_open,num_lost_offd,now_checking_offd,next_open_offd,start,stop,cnt_diag,cnt_offd,num_elmts,cnt)

2727: #endif

2728:    {

2729:        my_thread_num = hypre_GetThreadNum();

2730:        num_threads = hypre_NumActiveThreads();

[...]

2740:        start = (n_fine/num_threads)*my_thread_num;

2741:        if (my_thread_num == num_threads-1)

[...]

2750:        if (trunc_factor > 0)

2751:        {

2752:           num_lost = 0;

2753:           num_lost_offd = 0;

2754:

2755:           next_open = P_diag_i[start];

2756:           now_checking = P_diag_i[start];

2757:           next_open_offd = P_offd_i[start];;

2758:           now_checking_offd = P_offd_i[start];;

2759:

2760:           for (i = start; i < stop; i++)

2761:           {

2762:             max_coef = 0;

2763:             for (j = P_diag_i[i]; j < P_diag_i[i+1]; j++)

2764:                max_coef = (max_coef < fabs(P_diag_data[j])) ?

2765:                       fabs(P_diag_data[j]) : max_coef;

2766:             for (j = P_offd_i[i]; j < P_offd_i[i+1]; j++)

2767:                max_coef = (max_coef < fabs(P_offd_data[j])) ?

2768:                       fabs(P_offd_data[j]) : max_coef;

2769:             max_coef *= trunc_factor;

2770:

2771:             start_j = P_diag_i[i];

2772:             if (num_lost) P_diag_i[i] -= num_lost;

2773:             row_sum = 0;

2774:             scale = 0;

2775:             for (j = start_j; j < P_diag_i[i+1]; j++)

2776:             {

2777:                row_sum += P_diag_data[now_checking];

2778:                if (fabs(P_diag_data[now_checking]) < max_coef)

2779:                {

2780:                   num_lost++;

2781:                   now_checking++;

2782:                }

2783:                else

2784:                {

2785:                   scale += P_diag_data[now_checking];

2786:                   P_diag_data[next_open] = P_diag_data[now_checking];

2787:                   P_diag_j[next_open] = P_diag_j[now_checking];

2788:                   now_checking++;

2789:                   next_open++;

2790:                }

2791:             }

2792:

2793:             start_j = P_offd_i[i];

2794:             if (num_lost_offd) P_offd_i[i] -= num_lost_offd;

2795:             for (j = start_j; j < P_offd_i[i+1]; j++)

2796:             {

2797:                row_sum += P_offd_data[now_checking_offd];

2798:                if (fabs(P_offd_data[now_checking_offd]) < max_coef)

2799:                {

2800:                   num_lost_offd++;

2801:                   now_checking_offd++;

2802:                }

2803:                else

2804:                {

2805:                   scale += P_offd_data[now_checking_offd];

2806:                   P_offd_data[next_open_offd] = P_offd_data[now_checking_offd];

2807:                   P_offd_j[next_open_offd] = P_offd_j[now_checking_offd];

2808:                   now_checking_offd++;

2809:                   next_open_offd++;

2810:                }

2811:             }

2812:             /* normalize row of P */

2813:

2814:             if (scale != 0.)

2815:             {

2816:                if (scale != row_sum)

2817:                {

2818:                    scale = row_sum/scale;

2819:                    for (j = P_diag_i[i]; j < (P_diag_i[i+1]-num_lost); j++)

2820:                           P_diag_data[j] *= scale;

2821:                    for (j = P_offd_i[i]; j < (P_offd_i[i+1]-num_lost_offd); j++)

2822:                           P_offd_data[j] *= scale;

[...]

2828:           if(my_thread_num == 0)

2829:           {   max_num_threads[0] = num_threads; }

2830:           num_lost_per_thread[my_thread_num] = num_lost;

2831:           num_lost_offd_per_thread[my_thread_num] = num_lost_offd;

[...]

2840:        if (max_elmts > 0)

[...]

2848:            for (i=start; i<stop; i++)

2849:            {

2850:               /* Note P_diag_i[stop] is the starting point for the next thread

2851:                * in j and data, not the stop point for this thread */

2852:               last_index = P_diag_i[i+1];

2853:               last_index_offd = P_offd_i[i+1];

2854:               if(i == stop-1)

2855:               {

2856:                   last_index -= num_lost_per_thread[my_thread_num];

2857:                   last_index_offd -= num_lost_offd_per_thread[my_thread_num];

2858:               }

2859:               cnt1 = last_index-P_diag_i[i] + last_index_offd-P_offd_i[i];

2860:               if (cnt1 > P_mxnum) P_mxnum = cnt1;

2861:            }

2862:

2863:            /* Some rows exceed max_elmts, and require truncation.  Essentially,

2864:             * each thread truncates and compresses its range of rows locally. */

2865:            if (P_mxnum > max_elmts)

[...]

2872:                P_aux_j = hypre_CTAlloc(HYPRE_Int, P_mxnum);

2873:                P_aux_data = hypre_CTAlloc(HYPRE_Real, P_mxnum);

2874:                cnt_diag = P_diag_i[start];

2875:                cnt_offd = P_offd_i[start];

2876:

2877:                for (i = start; i < stop; i++)

2878:                {

2879:                 /* Note P_diag_i[stop] is the starting point for the next thread

2880:                  * in j and data, not the stop point for this thread */

2881:                 last_index = P_diag_i[i+1];

2882:                 last_index_offd = P_offd_i[i+1];

2883:                 if(i == stop-1)

2884:                 {

2885:                     last_index -= num_lost_per_thread[my_thread_num];

2886:                     last_index_offd -= num_lost_offd_per_thread[my_thread_num];

2887:                 }

2888:

2889:                 row_sum = 0;

2890:                 num_elmts = last_index-P_diag_i[i] + last_index_offd-P_offd_i[i];

2891:                 if (max_elmts < num_elmts)

2892:                 {

2893:                   /* copy both diagonal and off-diag parts of row i to _aux_ arrays */

2894:                   cnt = 0;

2895:                   for (j = P_diag_i[i]; j < last_index; j++)

2896:                   {

2897:                      P_aux_j[cnt] = P_diag_j[j];

2898:                      P_aux_data[cnt++] = P_diag_data[j];

2899:                      row_sum += P_diag_data[j];

2900:                   }

2901:                   num_lost += cnt;

2902:                   cnt1 = cnt;

2903:                   for (j = P_offd_i[i]; j < last_index_offd; j++)

2904:                   {

2905:                      P_aux_j[cnt] = P_offd_j[j]+num_cols;

2906:                      P_aux_data[cnt++] = P_offd_data[j];

2907:                      row_sum += P_offd_data[j];

2908:                   }

2909:                   num_lost_offd += cnt-cnt1;

2910:

2911:                   /* sort data */

2912:                   hypre_qsort2abs(P_aux_j,P_aux_data,0,cnt-1);

2913:                   scale = 0;

2914:                   if (i > start)

2915:                   {

2916:                      P_diag_i[i] = cnt_diag;

2917:                      P_offd_i[i] = cnt_offd;

2918:                   }

2919:                   for (j = 0; j < max_elmts; j++)

2920:                   {

2921:                      scale += P_aux_data[j];

2922:                      if (P_aux_j[j] < num_cols)

2923:                      {

2924:                         P_diag_j[cnt_diag] = P_aux_j[j];

2925:                         P_diag_data[cnt_diag++] = P_aux_data[j];

2926:                      }

2927:                      else

2928:                      {

2929:                         P_offd_j[cnt_offd] = P_aux_j[j]-num_cols;

2930:                         P_offd_data[cnt_offd++] = P_aux_data[j];

2931:                      }

2932:                   }

2933:                   num_lost -= cnt_diag-P_diag_i[i];

2934:                   num_lost_offd -= cnt_offd-P_offd_i[i];

2935:

2936:                   /* normalize row of P */

2937:                   if (scale != 0.)

2938:                   {

2939:                      if (scale != row_sum)

2940:                      {

2941:                         scale = row_sum/scale;

2942:                         for (j = P_diag_i[i]; j < cnt_diag; j++)

2943:                                P_diag_data[j] *= scale;

2944:                         for (j = P_offd_i[i]; j < cnt_offd; j++)

2945:                                P_offd_data[j] *= scale;

[...]

2955:                   if (P_diag_i[i] != cnt_diag)

2956:                   {

2957:                      start_j = P_diag_i[i];

2958:                      P_diag_i[i] = cnt_diag;

2959:                      for (j = start_j; j < last_index; j++)

2960:                      {

2961:                         P_diag_j[cnt_diag] = P_diag_j[j];

2962:                         P_diag_data[cnt_diag++] = P_diag_data[j];

2963:                      }

2964:                   }

2965:                   else

2966:                      cnt_diag += last_index-P_diag_i[i];

2967:

2968:                   if (P_offd_i[i] != cnt_offd)

2969:                   {

2970:                      start_j = P_offd_i[i];

2971:                      P_offd_i[i] = cnt_offd;

2972:                      for (j = start_j; j < last_index_offd; j++)

2973:                      {

2974:                         P_offd_j[cnt_offd] = P_offd_j[j];

2975:                         P_offd_data[cnt_offd++] = P_offd_data[j];

[...]

2983:                num_lost_per_thread[my_thread_num] += num_lost;

2984:                num_lost_offd_per_thread[my_thread_num] += num_lost_offd;

2985:                hypre_TFree(P_aux_j);

2986:                hypre_TFree(P_aux_data);

[...]

2994: #pragma omp barrier

2995: #endif

2996:        if(my_thread_num == 0)

2997:        {

2998:            num_lost_global = 0;

2999:            num_lost_global_offd = 0;

3000:            for(i = 0; i < max_num_threads[0]; i++)

3001:            {

3002:                num_lost_global += num_lost_per_thread[i];

3003:                num_lost_global_offd += num_lost_offd_per_thread[i];

3004:            }

3005:        }

3006: #ifdef HYPRE_USING_OPENMP

3007: #pragma omp barrier

[...]

3013:        if (num_lost_global)

[...]

3023:           if(my_thread_num == 0)

3024:           {

3025:               P_diag_size = P_diag_i[n_fine];

3026:

3027:               for(i = 0; i < max_num_threads[0]; i++)

3028:               {

3029:                   P_diag_size -= num_lost_per_thread[i];

3030:                   if(i > 0)

3031:                   {   cum_lost_per_thread[i] = num_lost_per_thread[i] + cum_lost_per_thread[i-1]; }

3032:                   else

3033:                   {   cum_lost_per_thread[i] = num_lost_per_thread[i]; }

3034:               }

3035:

3036:               P_diag_j_new = hypre_CTAlloc(HYPRE_Int,P_diag_size);

3037:               P_diag_data_new = hypre_CTAlloc(HYPRE_Real,P_diag_size);

3038:           }

3039: #ifdef HYPRE_USING_OPENMP

3040: #pragma omp barrier

3041: #endif

3042:

3043:           /* points to next open spot in new data structures for this thread */

3044:           if(my_thread_num == 0)

[...]

3050:               next_open = P_diag_i[start] - cum_lost_per_thread[my_thread_num-1];

3051:           }

3052:           /* copy the j and data arrays over */

3053:           for(i = P_diag_i[start]; i < P_diag_i[stop] - num_lost_per_thread[my_thread_num]; i++)

3054:           {

3055:               P_diag_j_new[next_open] = P_diag_j[i];

3056:               P_diag_data_new[next_open] = P_diag_data[i];

3057:               next_open += 1;

3058:           }

3059:

3060: #ifdef HYPRE_USING_OPENMP

3061: #pragma omp barrier

3062: #endif

3063:           /* update P_diag_i with number of dropped entries by all lower ranked

3064:            * threads */

3065:           if(my_thread_num > 0)

3066:           {

3067:               for(i=start; i<stop; i++)

3068:               {

3069:                   P_diag_i[i] -= cum_lost_per_thread[my_thread_num-1];

3070:               }

3071:           }

3072:

3073:           if(my_thread_num == 0)

3074:           {

3075:               /* Set last entry */

3076:               P_diag_i[n_fine] = P_diag_size ;

3077:

3078:               hypre_TFree(P_diag_j);

3079:               hypre_TFree(P_diag_data);

3080:               hypre_CSRMatrixJ(P_diag) = P_diag_j_new;

3081:               hypre_CSRMatrixData(P_diag) = P_diag_data_new;

3082:               hypre_CSRMatrixNumNonzeros(P_diag) = P_diag_size;

[...]

3091: #pragma omp barrier

3092: #endif

3093:        if (num_lost_global_offd)

3094:        {

3095:           /* Repeat process for off-diagonal */

3096:           if(my_thread_num == 0)

3097:           {

3098:               P_offd_size = P_offd_i[n_fine];

3099:               for(i = 0; i < max_num_threads[0]; i++)

3100:               {

3101:                   P_offd_size -= num_lost_offd_per_thread[i];

3102:                   if(i > 0)

3103:                   {   cum_lost_per_thread[i] = num_lost_offd_per_thread[i] + cum_lost_per_thread[i-1]; }

3104:                   else

3105:                   {   cum_lost_per_thread[i] = num_lost_offd_per_thread[i]; }

3106:               }

3107:

3108:               P_offd_j_new = hypre_CTAlloc(HYPRE_Int,P_offd_size);

3109:               P_offd_data_new = hypre_CTAlloc(HYPRE_Real,P_offd_size);

3110:           }

3111: #ifdef HYPRE_USING_OPENMP

3112: #pragma omp barrier

3113: #endif

3114:

3115:           /* points to next open spot in new data structures for this thread */

3116:           if(my_thread_num == 0)

[...]

3122:               next_open = P_offd_i[start] - cum_lost_per_thread[my_thread_num-1];

3123:           }

3124:

3125:           /* copy the j and data arrays over */

3126:           for(i = P_offd_i[start]; i < P_offd_i[stop] - num_lost_offd_per_thread[my_thread_num]; i++)

3127:           {

3128:               P_offd_j_new[next_open] = P_offd_j[i];

3129:               P_offd_data_new[next_open] = P_offd_data[i];

3130:               next_open += 1;

3131:           }

3132:

3133: #ifdef HYPRE_USING_OPENMP

3134: #pragma omp barrier

3135: #endif

3136:           /* update P_offd_i with number of dropped entries by all lower ranked

3137:            * threads */

3138:           if(my_thread_num > 0)

3139:           {

3140:               for(i=start; i<stop; i++)

3141:               {

3142:                   P_offd_i[i] -= cum_lost_per_thread[my_thread_num-1];

3143:               }

3144:           }

3145:

3146:           if(my_thread_num == 0)

3147:           {

3148:               /* Set last entry */

3149:               P_offd_i[n_fine] = P_offd_size ;

3150:

3151:               hypre_TFree(P_offd_j);

3152:               hypre_TFree(P_offd_data);

3153:               hypre_CSRMatrixJ(P_offd) = P_offd_j_new;

3154:               hypre_CSRMatrixData(P_offd) = P_offd_data_new;

3155:               hypre_CSRMatrixNumNonzeros(P_offd) = P_offd_size;

0x42c720 SUB	SP, SP, #288

0x42c724 STR	D8, [SP, #176]

0x42c728 STP	X29, X30, [SP, #192]

0x42c72c STP	X28, X27, [SP, #208]

0x42c730 STP	X26, X25, [SP, #224]

0x42c734 STP	X24, X23, [SP, #240]

0x42c738 STP	X22, X21, [SP, #256]

0x42c73c STP	X20, X19, [SP, #272]

0x42c740 ADD	X29, SP, #192

0x42c744 LDP	X9, X20, [X29, #128]

0x42c748 LDR	X8, [X29, #120]

0x42c74c STP	X6, X7, [X29, #960]

0x42c750 ORR	X26, XZR, X3

0x42c754 ORR	X19, XZR, X2

0x42c758 STP	X4, X5, [X29, #984]

0x42c75c STR	X0, [SP, #48]

0x42c760 STP	X8, X9, [X29, #944]

0x42c764 LDR	X8, [X29, #112]

0x42c768 STR	X8, [SP, #56]

0x42c76c LDP	X8, X28, [X29, #96]

0x42c770 STUR	X8, [X29, #504]

0x42c774 BL	4a4720

0x42c778 ORR	X22, XZR, X0

0x42c77c BL	4a4700

0x42c780 LDR	X9, [X19]

0x42c784 LDR	D0, [X26]

0x42c788 SUB	X10, X0, #1

0x42c78c STR	X19, [SP, #40]

0x42c790 CMP	X22, X10

0x42c794 STR	X20, [SP, #88]

0x42c798 SDIV	X8, X9, X0

0x42c79c MADD	X23, X8, X22, XZR

0x42c7a0 ADD	X11, X8, X23

0x42c7a4 CSEL	X27, X9, X11, #0

0x42c7a8 FCMP	D0, #0

0x42c7ac B.LE	42cbe8

0x42c7b0 CMP	X27, X23

0x42c7b4 B.LE	42cbb4

0x42c7b8 LDP	X11, X12, [X29, #984]

0x42c7bc LDP	X14, X16, [X29, #960]

0x42c7c0 ORR	X9, XZR, XZR

0x42c7c4 ORR	X10, XZR, XZR

0x42c7c8 LDR	X11, [X11]

0x42c7cc LDR	X12, [X12]

0x42c7d0 LDR	X14, [X14]

0x42c7d4 LDR	X16, [X16]

0x42c7d8 ORR	X2, XZR, X23

0x42c7dc LDR	X5, [X12, X23,LSL #3]

0x42c7e0 LDR	X13, [X11, X23,LSL #3]

0x42c7e4 ADD	X15, X14, #16

0x42c7e8 ADD	X17, X16, #16

0x42c7ec ORR	X18, XZR, X5

0x42c7f0 ORR	X1, XZR, X5

0x42c7f4 ORR	X3, XZR, X13

0x42c7f8 B	42c808

0x42c7fc HINT	#0

  (1419) 0x42c800 CMP	X2, X27

  (1419) 0x42c804 B.EQ	42cbbc

  (1419) 0x42c808 ORR	X4, XZR, X2

  (1419) 0x42c80c LDR	X6, [X11, X2,LSL #3]

  (1419) 0x42c810 ADD	X2, X2, #1

  (1419) 0x42c814 MOVI	D0, #0

  (1419) 0x42c818 LDR	X7, [X11, X2,LSL #3]

  (1419) 0x42c81c CMP	X7, X6

  (1419) 0x42c820 B.LE	42c8cc

  (1419) 0x42c824 SUB	W19, W7, W6

  (1419) 0x42c828 MOVI	D0, #0

  (1419) 0x42c82c ANDS	X20, X19, #4160

  (1419) 0x42c830 B.EQ	42c870

  (1419) 0x42c834 ORR	X19, XZR, X6

  (1419) 0x42c838 HINT	#0

  (1419) 0x42c83c HINT	#0

    (1424) 0x42c840 LDR	D1, [X14, X19,LSL #3]

    (1424) 0x42c844 ADD	X19, X19, #1

    (1424) 0x42c848 FABS	D1, D1

    (1424) 0x42c84c FCMP	D0, D1

    (1424) 0x42c850 FCSEL	D0, D1, D0, #4

    (1424) 0x42c854 SUBS	X20, X20, #1

    (1424) 0x42c858 B.NE	42c840

  (1419) 0x42c85c ORN	X20, XZR, X6

  (1419) 0x42c860 ADD	X20, X7, X20

  (1419) 0x42c864 CMP	X20, #3

  (1419) 0x42c868 B.CS	42c884

  (1419) 0x42c86c B	42c8cc

  (1419) 0x42c870 ORR	X19, XZR, X6

  (1419) 0x42c874 ORN	X20, XZR, X6

  (1419) 0x42c878 ADD	X20, X7, X20

  (1419) 0x42c87c CMP	X20, #3

  (1419) 0x42c880 B.CC	42c8cc

  (1419) 0x42c884 SUB	X20, X7, X19

  (1419) 0x42c888 ADD	X19, X15, X19,LSL #3

    (1423) 0x42c88c LDP	D1, D2, [X19, #1008]

    (1423) 0x42c890 FABS	D1, D1

    (1423) 0x42c894 FCMP	D0, D1

    (1423) 0x42c898 FCSEL	D0, D1, D0, #4

    (1423) 0x42c89c FABS	D1, D2

    (1423) 0x42c8a0 FCMP	D0, D1

    (1423) 0x42c8a4 FCSEL	D0, D1, D0, #4

    (1423) 0x42c8a8 LDP	D1, D2, [X19], #32

    (1423) 0x42c8ac FABS	D1, D1

    (1423) 0x42c8b0 FCMP	D0, D1

    (1423) 0x42c8b4 FCSEL	D0, D1, D0, #4

    (1423) 0x42c8b8 FABS	D1, D2

    (1423) 0x42c8bc FCMP	D0, D1

    (1423) 0x42c8c0 FCSEL	D0, D1, D0, #4

    (1423) 0x42c8c4 SUBS	X20, X20, #4

    (1423) 0x42c8c8 B.NE	42c88c

  (1419) 0x42c8cc LDR	X19, [X12, X2,LSL #3]

  (1419) 0x42c8d0 CMP	X19, X5

  (1419) 0x42c8d4 B.LE	42c980

  (1419) 0x42c8d8 SUB	W20, W19, W5

  (1419) 0x42c8dc ANDS	X21, X20, #4160

  (1419) 0x42c8e0 B.EQ	42c918

  (1419) 0x42c8e4 ORR	X20, XZR, X5

    (1422) 0x42c8e8 LDR	D1, [X16, X20,LSL #3]

    (1422) 0x42c8ec ADD	X20, X20, #1

    (1422) 0x42c8f0 FABS	D1, D1

    (1422) 0x42c8f4 FCMP	D0, D1

    (1422) 0x42c8f8 FCSEL	D0, D1, D0, #4

    (1422) 0x42c8fc SUBS	X21, X21, #1

    (1422) 0x42c900 B.NE	42c8e8

  (1419) 0x42c904 ORN	X5, XZR, X5

  (1419) 0x42c908 ADD	X5, X19, X5

  (1419) 0x42c90c CMP	X5, #3

  (1419) 0x42c910 B.CS	42c92c

  (1419) 0x42c914 B	42c980

  (1419) 0x42c918 ORR	X20, XZR, X5

  (1419) 0x42c91c ORN	X5, XZR, X5

  (1419) 0x42c920 ADD	X5, X19, X5

  (1419) 0x42c924 CMP	X5, #3

  (1419) 0x42c928 B.CC	42c980

  (1419) 0x42c92c SUB	X5, X19, X20

  (1419) 0x42c930 ADD	X19, X17, X20,LSL #3

  (1419) 0x42c934 HINT	#0

  (1419) 0x42c938 HINT	#0

  (1419) 0x42c93c HINT	#0

    (1421) 0x42c940 LDP	D1, D2, [X19, #1008]

    (1421) 0x42c944 FABS	D1, D1

    (1421) 0x42c948 FCMP	D0, D1

    (1421) 0x42c94c FCSEL	D0, D1, D0, #4

    (1421) 0x42c950 FABS	D1, D2

    (1421) 0x42c954 FCMP	D0, D1

    (1421) 0x42c958 FCSEL	D0, D1, D0, #4

    (1421) 0x42c95c LDP	D1, D2, [X19], #32

    (1421) 0x42c960 FABS	D1, D1

    (1421) 0x42c964 FCMP	D0, D1

    (1421) 0x42c968 FCSEL	D0, D1, D0, #4

    (1421) 0x42c96c FABS	D1, D2

    (1421) 0x42c970 FCMP	D0, D1

    (1421) 0x42c974 FCSEL	D0, D1, D0, #4

    (1421) 0x42c978 SUBS	X5, X5, #4

    (1421) 0x42c97c B.NE	42c940

  (1419) 0x42c980 LDR	D1, [X26]

  (1419) 0x42c984 CBZ	X10, 42c990

  (1419) 0x42c988 SUB	X5, X6, X10

  (1419) 0x42c98c STR	X5, [X11, X4,LSL #3]

  (1419) 0x42c990 FMUL	D2, D0, D1

  (1419) 0x42c994 MOVI	D1, #0

  (1419) 0x42c998 CMP	X7, X6

  (1419) 0x42c99c B.LE	42ca20

  (1419) 0x42c9a0 LDUR	X5, [X29, #504]

  (1419) 0x42c9a4 MOVI	D0, #0

  (1419) 0x42c9a8 MOVI	D1, #0

  (1419) 0x42c9ac LDR	X5, [X5]

  (1419) 0x42c9b0 B	42c9ec

0x42c9b4 HINT	#0

0x42c9b8 HINT	#0

0x42c9bc HINT	#0

    (1420) 0x42c9c0 LDR	X7, [X5, X3,LSL #3]

    (1420) 0x42c9c4 FADD	D0, D0, D3

    (1420) 0x42c9c8 STR	D3, [X14, X13,LSL #3]

    (1420) 0x42c9cc STR	X7, [X5, X13,LSL #3]

    (1420) 0x42c9d0 ADD	X13, X13, #1

    (1420) 0x42c9d4 LDR	X7, [X11, X2,LSL #3]

    (1420) 0x42c9d8 FADD	D1, D1, D3

    (1420) 0x42c9dc ADD	X6, X6, #1

    (1420) 0x42c9e0 ADD	X3, X3, #1

    (1420) 0x42c9e4 CMP	X6, X7

    (1420) 0x42c9e8 B.GE	42ca24

    (1420) 0x42c9ec LDR	D3, [X14, X3,LSL #3]

    (1420) 0x42c9f0 FABS	D4, D3

    (1420) 0x42c9f4 FCMP	D4, D2

    (1420) 0x42c9f8 B.PL	42c9c0

    (1420) 0x42c9fc ADD	X10, X10, #1

    (1420) 0x42ca00 FADD	D1, D1, D3

    (1420) 0x42ca04 ADD	X6, X6, #1

    (1420) 0x42ca08 ADD	X3, X3, #1

    (1420) 0x42ca0c CMP	X6, X7

    (1420) 0x42ca10 B.LT	42c9ec

  (1419) 0x42ca14 B	42ca24

0x42ca18 HINT	#0

0x42ca1c HINT	#0

(1418) 0x42ca20 MOVI	D0, #0

  (1419) 0x42ca24 LDR	X6, [X12, X4,LSL #3]

  (1419) 0x42ca28 CBZ	X9, 42ca34

  (1419) 0x42ca2c SUB	X5, X6, X9

  (1419) 0x42ca30 STR	X5, [X12, X4,LSL #3]

  (1419) 0x42ca34 LDR	X5, [X12, X2,LSL #3]

  (1419) 0x42ca38 CMP	X6, X5

  (1419) 0x42ca3c B.GE	42ca9c

  (1419) 0x42ca40 LDR	X7, [X28]

  (1419) 0x42ca44 B	42ca74

    (1429) 0x42ca48 LDR	X5, [X7, X1,LSL #3]

    (1429) 0x42ca4c FADD	D0, D0, D3

    (1429) 0x42ca50 STR	D3, [X16, X18,LSL #3]

    (1429) 0x42ca54 STR	X5, [X7, X18,LSL #3]

    (1429) 0x42ca58 ADD	X18, X18, #1

    (1429) 0x42ca5c LDR	X5, [X12, X2,LSL #3]

    (1429) 0x42ca60 FADD	D1, D1, D3

    (1429) 0x42ca64 ADD	X6, X6, #1

    (1429) 0x42ca68 ADD	X1, X1, #1

    (1429) 0x42ca6c CMP	X6, X5

    (1429) 0x42ca70 B.GE	42ca9c

    (1429) 0x42ca74 LDR	D3, [X16, X1,LSL #3]

    (1429) 0x42ca78 FABS	D4, D3

    (1429) 0x42ca7c FCMP	D4, D2

    (1429) 0x42ca80 B.PL	42ca48

    (1429) 0x42ca84 ADD	X9, X9, #1

    (1429) 0x42ca88 FADD	D1, D1, D3

    (1429) 0x42ca8c ADD	X6, X6, #1

    (1429) 0x42ca90 ADD	X1, X1, #1

    (1429) 0x42ca94 CMP	X6, X5

    (1429) 0x42ca98 B.LT	42ca74

  (1419) 0x42ca9c FCMP	D0, #0

  (1419) 0x42caa0 FCCMP	D0, D1, #4, #1

  (1419) 0x42caa4 B.EQ	42c800

  (1419) 0x42caa8 FDIV	D0, D1, D0

  (1419) 0x42caac LDR	X19, [X11, X2,LSL #3]

  (1419) 0x42cab0 LDR	X6, [X11, X4,LSL #3]

  (1419) 0x42cab4 SUB	X7, X19, X10

  (1419) 0x42cab8 CMP	X6, X7

  (1419) 0x42cabc B.GE	42cb30

  (1419) 0x42cac0 ADD	W20, W10, W6

  (1419) 0x42cac4 ORN	X21, XZR, X10

  (1419) 0x42cac8 SUB	W20, W19, W20

  (1419) 0x42cacc ADD	X19, X19, X21

  (1419) 0x42cad0 SUB	X19, X19, X6

  (1419) 0x42cad4 ANDS	X20, X20, #4160

  (1419) 0x42cad8 B.EQ	42caf8

  (1419) 0x42cadc HINT	#0

    (1428) 0x42cae0 LDR	D1, [X14, X6,LSL #3]

    (1428) 0x42cae4 SUBS	X20, X20, #1

    (1428) 0x42cae8 FMUL	D1, D0, D1

    (1428) 0x42caec STR	D1, [X14, X6,LSL #3]

    (1428) 0x42caf0 ADD	X6, X6, #1

    (1428) 0x42caf4 B.NE	42cae0

  (1419) 0x42caf8 CMP	X19, #3

  (1419) 0x42cafc B.CC	42cb30

  (1419) 0x42cb00 ADD	X19, X15, X6,LSL #3

    (1427) 0x42cb04 LDP	D1, D2, [X19, #1008]

    (1427) 0x42cb08 ADD	X6, X6, #4

    (1427) 0x42cb0c CMP	X6, X7

    (1427) 0x42cb10 FMUL	D2, D0, D2

    (1427) 0x42cb14 FMUL	D1, D0, D1

    (1427) 0x42cb18 STP	D1, D2, [X19, #1008]

    (1427) 0x42cb1c LDP	D1, D2, [X19]

    (1427) 0x42cb20 FMUL	D2, D0, D2

    (1427) 0x42cb24 FMUL	D1, D0, D1

    (1427) 0x42cb28 STP	D1, D2, [X19], #32

    (1427) 0x42cb2c B.LT	42cb04

  (1419) 0x42cb30 LDR	X4, [X12, X4,LSL #3]

  (1419) 0x42cb34 SUB	X6, X5, X9

  (1419) 0x42cb38 CMP	X4, X6

  (1419) 0x42cb3c B.GE	42c800

  (1419) 0x42cb40 SUB	W7, W5, W9

  (1419) 0x42cb44 SUB	W19, W7, W4

  (1419) 0x42cb48 ORN	X7, XZR, X9

  (1419) 0x42cb4c ADD	X7, X5, X7

  (1419) 0x42cb50 ANDS	X19, X19, #4160

  (1419) 0x42cb54 SUB	X7, X7, X4

  (1419) 0x42cb58 B.EQ	42cb78

  (1419) 0x42cb5c HINT	#0

    (1426) 0x42cb60 LDR	D1, [X16, X4,LSL #3]

    (1426) 0x42cb64 SUBS	X19, X19, #1

    (1426) 0x42cb68 FMUL	D1, D0, D1

    (1426) 0x42cb6c STR	D1, [X16, X4,LSL #3]

    (1426) 0x42cb70 ADD	X4, X4, #1

    (1426) 0x42cb74 B.NE	42cb60

  (1419) 0x42cb78 CMP	X7, #3

  (1419) 0x42cb7c B.CC	42c800

  (1419) 0x42cb80 ADD	X7, X17, X4,LSL #3

    (1425) 0x42cb84 LDP	D1, D2, [X7, #1008]

    (1425) 0x42cb88 ADD	X4, X4, #4

    (1425) 0x42cb8c CMP	X4, X6

    (1425) 0x42cb90 FMUL	D2, D0, D2

    (1425) 0x42cb94 FMUL	D1, D0, D1

    (1425) 0x42cb98 STP	D1, D2, [X7, #1008]

    (1425) 0x42cb9c LDP	D1, D2, [X7]

    (1425) 0x42cba0 FMUL	D2, D0, D2

    (1425) 0x42cba4 FMUL	D1, D0, D1

    (1425) 0x42cba8 STP	D1, D2, [X7], #32

    (1425) 0x42cbac B.LT	42cb84

  (1419) 0x42cbb0 B	42c800

0x42cbb4 ORR	X10, XZR, XZR

0x42cbb8 ORR	X9, XZR, XZR

0x42cbbc CBNZ	X22, 42cbcc

0x42cbc0 LDR	X11, [SP, #56]

0x42cbc4 LDR	X11, [X11]

0x42cbc8 STR	X0, [X11]

0x42cbcc LDUR	X11, [X29, #432]

0x42cbd0 LDR	X20, [SP, #88]

0x42cbd4 LDR	X11, [X11]

0x42cbd8 STR	X10, [X11, X22,LSL #3]

0x42cbdc LDUR	X10, [X29, #440]

0x42cbe0 LDR	X10, [X10]

0x42cbe4 STR	X9, [X10, X22,LSL #3]

0x42cbe8 LDR	X9, [X20]

0x42cbec LDP	X19, X24, [X29, #152]

0x42cbf0 STUR	X23, [X29, #424]

0x42cbf4 CMP	X9, #1

0x42cbf8 STR	X22, [SP, #72]

0x42cbfc STUR	X27, [X29, #464]

0x42cc00 B.LT	42d4a0

0x42cc04 LDUR	X10, [X29, #424]

0x42cc08 SUBS	X10, X27, X10

0x42cc0c B.LE	42cc98

0x42cc10 LDUR	X11, [X29, #472]

0x42cc14 MADD	X8, X22, X8, XZR

0x42cc18 ORR	X27, XZR, XZR

0x42cc1c UBFM	X8, X8, #61, #60

0x42cc20 ADD	X15, X8, #8

0x42cc24 LDR	X13, [X11]

0x42cc28 LDUR	X11, [X29, #480]

0x42cc2c LDR	X14, [X11]

0x42cc30 LDP	X11, X12, [X29, #944]

0x42cc34 ADD	X13, X13, X15

0x42cc38 LDR	X11, [X11]

0x42cc3c LDR	X12, [X12]

0x42cc40 ADD	X8, X14, X15

0x42cc44 B	42cc74

(1417) 0x42cc48 LDUR	X16, [X13, #504]

(1417) 0x42cc4c LDUR	X17, [X8, #504]

(1417) 0x42cc50 ADD	X14, X15, X14

(1417) 0x42cc54 ADD	X8, X8, #8

(1417) 0x42cc58 ADD	X13, X13, #8

(1417) 0x42cc5c ADD	X15, X16, X17

(1417) 0x42cc60 SUB	X14, X14, X15

(1417) 0x42cc64 CMP	X14, X27

(1417) 0x42cc68 CSEL	X27, X14, X27, #12

(1417) 0x42cc6c SUBS	X10, X10, #1

(1417) 0x42cc70 B.EQ	42cc9c

(1417) 0x42cc74 LDR	X14, [X13]

(1417) 0x42cc78 LDR	X15, [X8]

(1417) 0x42cc7c CMP	X10, #1

(1417) 0x42cc80 B.NE	42cc48

(1417) 0x42cc84 LDR	X16, [X11, X22,LSL #3]

(1417) 0x42cc88 SUB	X14, X14, X16

(1417) 0x42cc8c LDR	X16, [X12, X22,LSL #3]

(1417) 0x42cc90 SUB	X15, X15, X16

(1417) 0x42cc94 B	42cc48

0x42cc98 ORR	X27, XZR, XZR

0x42cc9c CMP	X27, X9

0x42cca0 B.LE	42d4a0

0x42cca4 ORR	X0, XZR, X27

0x42cca8 MOVZ	W1, #8

0x42ccac BL	4a2570

0x42ccb0 ORR	X26, XZR, X0

0x42ccb4 ORR	X0, XZR, X27

0x42ccb8 MOVZ	W1, #8

0x42ccbc BL	4a2570

0x42ccc0 LDUR	X3, [X29, #464]

0x42ccc4 LDUR	X20, [X29, #424]

0x42ccc8 ORR	X27, XZR, X0

0x42cccc CMP	X3, X20

0x42ccd0 B.LE	42d454

0x42ccd4 LDP	X9, X8, [X29, #984]

0x42ccd8 STR	X28, [SP, #80]

0x42ccdc LDR	X28, [X29, #144]

0x42cce0 ORR	X4, XZR, XZR

0x42cce4 ORR	X5, XZR, XZR

0x42cce8 SUB	X6, X3, #1

0x42ccec ADD	X11, X27, #8

0x42ccf0 ADD	X10, X26, #8

0x42ccf4 LDR	X30, [SP, #88]

0x42ccf8 STP	X19, X24, [SP, #8]

0x42ccfc STP	X10, X11, [SP, #24]

0x42cd00 STR	X6, [SP, #64]

0x42cd04 LDR	X8, [X8]

0x42cd08 LDR	X9, [X9]

0x42cd0c LDR	X23, [X8, X20,LSL #3]

0x42cd10 LDR	X21, [X9, X20,LSL #3]

0x42cd14 B	42cd30

0x42cd18 HINT	#0

0x42cd1c HINT	#0

  (1404) 0x42cd20 ORR	X23, XZR, X10

  (1404) 0x42cd24 ORR	X20, XZR, X7

  (1404) 0x42cd28 CMP	X7, X3

  (1404) 0x42cd2c B.EQ	42d460

  (1404) 0x42cd30 ADD	X7, X20, #1

  (1404) 0x42cd34 CMP	X20, X6

  (1404) 0x42cd38 LDR	X11, [X9, X7,LSL #3]

  (1404) 0x42cd3c LDR	X10, [X8, X7,LSL #3]

  (1404) 0x42cd40 B.NE	42cd64

  (1404) 0x42cd44 LDUR	X12, [X29, #432]

  (1404) 0x42cd48 LDR	X12, [X12]

  (1404) 0x42cd4c LDR	X12, [X12, X22,LSL #3]

  (1404) 0x42cd50 SUB	X11, X11, X12

  (1404) 0x42cd54 LDUR	X12, [X29, #440]

  (1404) 0x42cd58 LDR	X12, [X12]

  (1404) 0x42cd5c LDR	X12, [X12, X22,LSL #3]

  (1404) 0x42cd60 SUB	X10, X10, X12

  (1404) 0x42cd64 LDR	X12, [X9, X20,LSL #3]

  (1404) 0x42cd68 LDR	X13, [X8, X20,LSL #3]

  (1404) 0x42cd6c LDR	X15, [X30]

  (1404) 0x42cd70 SUB	X19, X11, X12

  (1404) 0x42cd74 ADD	X14, X19, X10

  (1404) 0x42cd78 SUB	X14, X14, X13

  (1404) 0x42cd7c CMP	X15, X14

  (1404) 0x42cd80 B.GE	42cdc0

  (1404) 0x42cd84 CMP	X11, X12

  (1404) 0x42cd88 B.LE	42cde0

  (1404) 0x42cd8c LDUR	X9, [X29, #504]

  (1404) 0x42cd90 ADD	X14, X12, #1

  (1404) 0x42cd94 CMP	X11, X14

  (1404) 0x42cd98 LDR	X13, [X9]

  (1404) 0x42cd9c LDUR	X9, [X29, #448]

  (1404) 0x42cda0 LDR	X9, [X9]

  (1404) 0x42cda4 B.NE	42ce7c

  (1404) 0x42cda8 ORR	X14, XZR, XZR

  (1404) 0x42cdac MOVI	D8, #0

  (1404) 0x42cdb0 ORR	X15, XZR, X12

  (1404) 0x42cdb4 TBNZ	W19, #0, 42cee8

  (1404) 0x42cdb8 B	42cf00

0x42cdbc HINT	#0

  (1404) 0x42cdc0 CMP	X12, X21

  (1404) 0x42cdc4 B.NE	42ce04

  (1404) 0x42cdc8 ADD	X21, X19, X21

  (1404) 0x42cdcc B	42d224

0x42cdd0 HINT	#0

0x42cdd4 HINT	#0

0x42cdd8 HINT	#0

0x42cddc HINT	#0

  (1404) 0x42cde0 ORR	X19, XZR, XZR

  (1404) 0x42cde4 MOVI	D8, #0

  (1404) 0x42cde8 SUBS	X15, X10, X13

  (1404) 0x42cdec STR	X7, [SP, #96]

  (1404) 0x42cdf0 B.GT	42cf10

  (1404) 0x42cdf4 ORR	X22, XZR, X5

  (1404) 0x42cdf8 ORR	X24, XZR, X4

  (1404) 0x42cdfc ORR	X18, XZR, X19

  (1404) 0x42ce00 B	42d004

  (1404) 0x42ce04 CMP	X11, X12

  (1404) 0x42ce08 STR	X21, [X9, X20,LSL #3]

  (1404) 0x42ce0c B.LE	42d224

  (1404) 0x42ce10 LDUR	X13, [X29, #504]

  (1404) 0x42ce14 LDUR	X14, [X29, #448]

  (1404) 0x42ce18 ANDS	X16, X19, #4160

  (1404) 0x42ce1c LDR	X13, [X13]

  (1404) 0x42ce20 LDR	X14, [X14]

  (1404) 0x42ce24 B.EQ	42d190

  (1404) 0x42ce28 UBFM	X18, X21, #61, #60

  (1404) 0x42ce2c UBFM	X1, X12, #61, #60

  (1404) 0x42ce30 ORR	X15, XZR, XZR

  (1404) 0x42ce34 ADD	X17, X14, X18

  (1404) 0x42ce38 ADD	X18, X13, X18

  (1404) 0x42ce3c ADD	X0, X14, X1

  (1404) 0x42ce40 ADD	X1, X13, X1

    (1408) 0x42ce44 LDR	D0, [X0, X15,LSL #3]

    (1408) 0x42ce48 LDR	X2, [X1, X15,LSL #3]

    (1408) 0x42ce4c STR	X2, [X18, X15,LSL #3]

    (1408) 0x42ce50 STR	D0, [X17, X15,LSL #3]

    (1408) 0x42ce54 ADD	X15, X15, #1

    (1408) 0x42ce58 CMP	X16, X15

    (1408) 0x42ce5c B.NE	42ce44

  (1404) 0x42ce60 ADD	X21, X21, X15

  (1404) 0x42ce64 ADD	X15, X12, X15

  (1404) 0x42ce68 ORN	X12, XZR, X12

  (1404) 0x42ce6c ADD	X12, X11, X12

  (1404) 0x42ce70 CMP	X12, #3

  (1404) 0x42ce74 B.CS	42d1a4

  (1404) 0x42ce78 B	42d224

  (1404) 0x42ce7c UBFM	X17, X12, #61, #60

  (1404) 0x42ce80 LDP	X18, X0, [SP, #24]

  (1404) 0x42ce84 AND	X15, X19, #8127

  (1404) 0x42ce88 ORR	X14, XZR, XZR

  (1404) 0x42ce8c MOVI	D8, #0

  (1404) 0x42ce90 ADD	X16, X9, X17

  (1404) 0x42ce94 ADD	X17, X13, X17

  (1404) 0x42ce98 SUB	X15, XZR, X15

  (1404) 0x42ce9c ADD	X16, X16, #8

  (1404) 0x42cea0 ADD	X17, X17, #8

    (1412) 0x42cea4 LDUR	D0, [X16, #504]

    (1412) 0x42cea8 LDUR	X1, [X17, #504]

    (1412) 0x42ceac SUB	X14, X14, #2

    (1412) 0x42ceb0 CMP	X15, X14

    (1412) 0x42ceb4 STUR	X1, [X18, #504]

    (1412) 0x42ceb8 LDR	X1, [X17], #16

    (1412) 0x42cebc STUR	D0, [X0, #504]

    (1412) 0x42cec0 LDP	D0, D1, [X16, #1016]

    (1412) 0x42cec4 STR	X1, [X18], #16

    (1412) 0x42cec8 STR	D1, [X0], #16

    (1412) 0x42cecc FADD	D0, D8, D0

    (1412) 0x42ced0 LDR	D1, [X16], #16

    (1412) 0x42ced4 FADD	D8, D0, D1

    (1412) 0x42ced8 B.NE	42cea4

  (1404) 0x42cedc SUB	X15, X12, X14

  (1404) 0x42cee0 SUB	X14, XZR, X14

  (1404) 0x42cee4 TBZ	W19, #0, 42cf00

  (1404) 0x42cee8 LDR	D0, [X9, X15,LSL #3]

  (1404) 0x42ceec LDR	X13, [X13, X15,LSL #3]

  (1404) 0x42cef0 STR	X13, [X26, X14,LSL #3]

  (1404) 0x42cef4 STR	D0, [X27, X14,LSL #3]

  (1404) 0x42cef8 LDR	D0, [X9, X15,LSL #3]

  (1404) 0x42cefc FADD	D8, D8, D0

  (1404) 0x42cf00 LDR	X13, [X8, X20,LSL #3]

  (1404) 0x42cf04 SUBS	X15, X10, X13

  (1404) 0x42cf08 STR	X7, [SP, #96]

  (1404) 0x42cf0c B.LE	42cdf4

  (1404) 0x42cf10 LDR	X8, [SP, #80]

  (1404) 0x42cf14 LDUR	X9, [X29, #456]

  (1404) 0x42cf18 ADD	X16, X13, #1

  (1404) 0x42cf1c LDR	X8, [X8]

  (1404) 0x42cf20 LDR	X9, [X9]

  (1404) 0x42cf24 TBNZ	W15, #0, 42cf48

  (1404) 0x42cf28 ORR	X14, XZR, X19

  (1404) 0x42cf2c ORR	X17, XZR, X13

  (1404) 0x42cf30 ADD	X18, X15, X19

  (1404) 0x42cf34 ORR	X22, XZR, X5

  (1404) 0x42cf38 ORR	X24, XZR, X4

  (1404) 0x42cf3c CMP	X10, X16

  (1404) 0x42cf40 B.NE	42cf84

  (1404) 0x42cf44 B	42d004

  (1404) 0x42cf48 LDR	D0, [X9, X13,LSL #3]

  (1404) 0x42cf4c LDR	X14, [X8, X13,LSL #3]

  (1404) 0x42cf50 LDR	X17, [X28]

  (1404) 0x42cf54 ADD	X14, X17, X14

  (1404) 0x42cf58 ORR	X17, XZR, X16

  (1404) 0x42cf5c STR	D0, [X27, X19,LSL #3]

  (1404) 0x42cf60 LDR	D0, [X9, X13,LSL #3]

  (1404) 0x42cf64 FADD	D8, D8, D0

  (1404) 0x42cf68 STR	X14, [X26, X19,LSL #3]

  (1404) 0x42cf6c ADD	X14, X19, #1

  (1404) 0x42cf70 ADD	X18, X15, X19

  (1404) 0x42cf74 ORR	X22, XZR, X5

  (1404) 0x42cf78 ORR	X24, XZR, X4

  (1404) 0x42cf7c CMP	X10, X16

  (1404) 0x42cf80 B.EQ	42d004

  (1404) 0x42cf84 ADD	X13, X14, X13

  (1404) 0x42cf88 CMP	X11, X12

  (1404) 0x42cf8c UBFM	X15, X17, #61, #60

  (1404) 0x42cf90 CSEL	X11, X11, X12, #12

  (1404) 0x42cf94 ADD	X8, X8, X15

  (1404) 0x42cf98 ADD	X9, X9, X15

  (1404) 0x42cf9c ADD	X8, X8, #8

  (1404) 0x42cfa0 ADD	X13, X13, X12

  (1404) 0x42cfa4 UBFM	X12, X14, #61, #60

  (1404) 0x42cfa8 ADD	X9, X9, #8

  (1404) 0x42cfac SUB	X10, X13, X10

  (1404) 0x42cfb0 SUB	X10, X10, X11

  (1404) 0x42cfb4 LDP	X13, X11, [SP, #24]

  (1404) 0x42cfb8 ADD	X11, X11, X12

  (1404) 0x42cfbc ADD	X12, X13, X12

    (1411) 0x42cfc0 LDUR	D0, [X9, #504]

    (1411) 0x42cfc4 LDUR	X13, [X8, #504]

    (1411) 0x42cfc8 LDR	X14, [X28]

    (1411) 0x42cfcc ADDS	X10, X10, #2

    (1411) 0x42cfd0 ADD	X13, X14, X13

    (1411) 0x42cfd4 STUR	D0, [X11, #504]

    (1411) 0x42cfd8 STUR	X13, [X12, #504]

    (1411) 0x42cfdc LDP	D0, D1, [X9, #1016]

    (1411) 0x42cfe0 LDR	X13, [X8], #16

    (1411) 0x42cfe4 LDR	X14, [X28]

    (1411) 0x42cfe8 ADD	X13, X14, X13

    (1411) 0x42cfec STR	D1, [X11], #16

    (1411) 0x42cff0 FADD	D0, D8, D0

    (1411) 0x42cff4 STR	X13, [X12], #16

    (1411) 0x42cff8 LDR	D1, [X9], #16

    (1411) 0x42cffc FADD	D8, D0, D1

    (1411) 0x42d000 B.NE	42cfc0

  (1404) 0x42d004 ORR	X0, XZR, X26

  (1404) 0x42d008 ORR	X1, XZR, X27

  (1404) 0x42d00c SUB	X3, X18, #1

  (1404) 0x42d010 ORR	X2, XZR, XZR

  (1404) 0x42d014 ORR	X25, XZR, X18

  (1404) 0x42d018 BL	42c610

  (1404) 0x42d01c LDUR	X8, [X29, #424]

  (1404) 0x42d020 CMP	X20, X8

  (1404) 0x42d024 B.LE	42d040

  (1404) 0x42d028 LDUR	X8, [X29, #472]

  (1404) 0x42d02c LDR	X8, [X8]

  (1404) 0x42d030 STR	X21, [X8, X20,LSL #3]

  (1404) 0x42d034 LDUR	X8, [X29, #480]

  (1404) 0x42d038 LDR	X8, [X8]

  (1404) 0x42d03c STR	X23, [X8, X20,LSL #3]

  (1404) 0x42d040 LDR	X30, [SP, #88]

  (1404) 0x42d044 LDUR	X3, [X29, #464]

  (1404) 0x42d048 LDR	X8, [X30]

  (1404) 0x42d04c CMP	X8, #1

  (1404) 0x42d050 B.LT	42d0e8

  (1404) 0x42d054 LDR	X9, [SP, #80]

  (1404) 0x42d058 LDP	X12, X10, [X29, #960]

  (1404) 0x42d05c LDUR	X11, [X29, #504]

  (1404) 0x42d060 ORR	X8, XZR, XZR

  (1404) 0x42d064 MOVI	D0, #0

  (1404) 0x42d068 LDR	X9, [X9]

  (1404) 0x42d06c LDR	X10, [X10]

  (1404) 0x42d070 LDR	X11, [X11]

  (1404) 0x42d074 LDR	X12, [X12]

  (1404) 0x42d078 B	42d0a8

0x42d07c HINT	#0

    (1410) 0x42d080 UBFM	X13, X23, #61, #60

    (1410) 0x42d084 ADD	X23, X23, #1

    (1410) 0x42d088 STR	X14, [X9, X13]

    (1410) 0x42d08c ADD	X13, X10, X13

    (1410) 0x42d090 STR	D1, [X13]

    (1410) 0x42d094 LDR	X13, [X30]

    (1410) 0x42d098 FADD	D0, D0, D1

    (1410) 0x42d09c ADD	X8, X8, #1

    (1410) 0x42d0a0 CMP	X8, X13

    (1410) 0x42d0a4 B.GE	42d0ec

    (1410) 0x42d0a8 LDR	D1, [X27, X8,LSL #3]

    (1410) 0x42d0ac LDR	X13, [X26, X8,LSL #3]

    (1410) 0x42d0b0 LDR	X14, [X28]

    (1410) 0x42d0b4 SUBS	X14, X13, X14

    (1410) 0x42d0b8 B.GE	42d080

    (1410) 0x42d0bc UBFM	X14, X21, #61, #60

    (1410) 0x42d0c0 ADD	X21, X21, #1

    (1410) 0x42d0c4 STR	X13, [X11, X14]

    (1410) 0x42d0c8 ADD	X13, X12, X14

    (1410) 0x42d0cc STR	D1, [X13]

    (1410) 0x42d0d0 LDR	X13, [X30]

    (1410) 0x42d0d4 FADD	D0, D0, D1

    (1410) 0x42d0d8 ADD	X8, X8, #1

    (1410) 0x42d0dc CMP	X8, X13

    (1410) 0x42d0e0 B.LT	42d0a8

  (1404) 0x42d0e4 B	42d0ec

  (1404) 0x42d0e8 MOVI	D0, #0

  (1404) 0x42d0ec LDUR	X9, [X29, #472]

  (1404) 0x42d0f0 ADD	X8, X19, X22

  (1404) 0x42d0f4 SUB	X13, X24, X19

  (1404) 0x42d0f8 FCMP	D0, #0

  (1404) 0x42d0fc FCCMP	D0, D8, #4, #1

  (1404) 0x42d100 ADD	X13, X13, X25

  (1404) 0x42d104 LDR	X9, [X9]

  (1404) 0x42d108 LDR	X11, [X9, X20,LSL #3]

  (1404) 0x42d10c SUB	X10, X11, X21

  (1404) 0x42d110 ADD	X5, X8, X10

  (1404) 0x42d114 LDUR	X8, [X29, #480]

  (1404) 0x42d118 LDR	X8, [X8]

  (1404) 0x42d11c LDR	X10, [X8, X20,LSL #3]

  (1404) 0x42d120 SUB	X12, X10, X23

  (1404) 0x42d124 ADD	X4, X13, X12

  (1404) 0x42d128 B.NE	42d140

  (1404) 0x42d12c LDP	X6, X22, [SP, #64]

  (1404) 0x42d130 LDR	X7, [SP, #96]

  (1404) 0x42d134 B	42cd24

0x42d138 HINT	#0

0x42d13c HINT	#0

(1409) 0x42d140 FDIV	D0, D8, D0

(1409) 0x42d144 CMP	X11, X21

(1409) 0x42d148 B.GE	42d308

(1409) 0x42d14c LDUR	X12, [X29, #448]

(1409) 0x42d150 SUB	W13, W21, W11

(1409) 0x42d154 ANDS	X14, X13, #4160

(1409) 0x42d158 LDR	X12, [X12]

(1409) 0x42d15c B.EQ	42d2b8

(1409) 0x42d160 ORR	X13, XZR, X11

  (1416) 0x42d164 LDR	D1, [X12, X13,LSL #3]

  (1416) 0x42d168 SUBS	X14, X14, #1

  (1416) 0x42d16c FMUL	D1, D0, D1

  (1416) 0x42d170 STR	D1, [X12, X13,LSL #3]

  (1416) 0x42d174 ADD	X13, X13, #1

  (1416) 0x42d178 B.NE	42d164

(1409) 0x42d17c ORN	X11, XZR, X11

(1409) 0x42d180 ADD	X11, X21, X11

(1409) 0x42d184 CMP	X11, #3

(1409) 0x42d188 B.CS	42d2cc

(1409) 0x42d18c B	42d308

  (1404) 0x42d190 ORR	X15, XZR, X12

  (1404) 0x42d194 ORN	X12, XZR, X12

  (1404) 0x42d198 ADD	X12, X11, X12

  (1404) 0x42d19c CMP	X12, #3

  (1404) 0x42d1a0 B.CC	42d224

  (1404) 0x42d1a4 SUB	X11, X11, X15

  (1404) 0x42d1a8 UBFM	X12, X15, #61, #60

  (1404) 0x42d1ac UBFM	X15, X21, #61, #60

  (1404) 0x42d1b0 ADD	X12, X12, #24

  (1404) 0x42d1b4 HINT	#0

  (1404) 0x42d1b8 HINT	#0

  (1404) 0x42d1bc HINT	#0

    (1407) 0x42d1c0 ADD	X16, X13, X12

    (1407) 0x42d1c4 ADD	X18, X13, X15

    (1407) 0x42d1c8 ADD	X21, X21, #4

    (1407) 0x42d1cc SUBS	X11, X11, #4

    (1407) 0x42d1d0 LDUR	X17, [X16, #488]

    (1407) 0x42d1d4 ADD	X0, X14, X15

    (1407) 0x42d1d8 ADD	X15, X15, #32

    (1407) 0x42d1dc STR	X17, [X18]

    (1407) 0x42d1e0 ADD	X17, X14, X12

    (1407) 0x42d1e4 ADD	X12, X12, #32

    (1407) 0x42d1e8 LDUR	X1, [X16, #496]

    (1407) 0x42d1ec LDUR	D0, [X17, #488]

    (1407) 0x42d1f0 STR	X1, [X18, #8]

    (1407) 0x42d1f4 LDUR	X1, [X16, #504]

    (1407) 0x42d1f8 STR	D0, [X0]

    (1407) 0x42d1fc LDUR	D0, [X17, #496]

    (1407) 0x42d200 STR	X1, [X18, #16]

    (1407) 0x42d204 LDR	X16, [X16]

    (1407) 0x42d208 STR	D0, [X0, #8]

    (1407) 0x42d20c STR	X16, [X18, #24]

    (1407) 0x42d210 LDUR	D0, [X17, #504]

    (1407) 0x42d214 STR	D0, [X0, #16]

    (1407) 0x42d218 LDR	D0, [X17]

    (1407) 0x42d21c STR	D0, [X0, #24]

    (1407) 0x42d220 B.NE	42d1c0

  (1404) 0x42d224 LDR	X13, [X8, X20,LSL #3]

  (1404) 0x42d228 CMP	X13, X23

  (1404) 0x42d22c B.EQ	42cd20

  (1404) 0x42d230 CMP	X10, X13

  (1404) 0x42d234 STR	X23, [X8, X20,LSL #3]

  (1404) 0x42d238 B.LE	42cd24

  (1404) 0x42d23c LDR	X11, [SP, #80]

  (1404) 0x42d240 LDUR	X12, [X29, #456]

  (1404) 0x42d244 SUB	W14, W10, W13

  (1404) 0x42d248 ANDS	X15, X14, #4160

  (1404) 0x42d24c LDR	X11, [X11]

  (1404) 0x42d250 LDR	X12, [X12]

  (1404) 0x42d254 B.EQ	42d36c

  (1404) 0x42d258 UBFM	X17, X23, #61, #60

  (1404) 0x42d25c UBFM	X0, X13, #61, #60

  (1404) 0x42d260 ORR	X14, XZR, XZR

  (1404) 0x42d264 ADD	X16, X12, X17

  (1404) 0x42d268 ADD	X17, X11, X17

  (1404) 0x42d26c ADD	X18, X12, X0

  (1404) 0x42d270 ADD	X0, X11, X0

  (1404) 0x42d274 HINT	#0

  (1404) 0x42d278 HINT	#0

  (1404) 0x42d27c HINT	#0

    (1406) 0x42d280 LDR	D0, [X18, X14,LSL #3]

    (1406) 0x42d284 LDR	X1, [X0, X14,LSL #3]

    (1406) 0x42d288 STR	X1, [X17, X14,LSL #3]

    (1406) 0x42d28c STR	D0, [X16, X14,LSL #3]

    (1406) 0x42d290 ADD	X14, X14, #1

    (1406) 0x42d294 CMP	X15, X14

    (1406) 0x42d298 B.NE	42d280

  (1404) 0x42d29c ADD	X23, X23, X14

  (1404) 0x42d2a0 ADD	X14, X13, X14

  (1404) 0x42d2a4 ORN	X13, XZR, X13

  (1404) 0x42d2a8 ADD	X13, X10, X13

  (1404) 0x42d2ac CMP	X13, #3

  (1404) 0x42d2b0 B.CC	42cd24

  (1404) 0x42d2b4 B	42d380

(1409) 0x42d2b8 ORR	X13, XZR, X11

(1409) 0x42d2bc ORN	X11, XZR, X11

(1409) 0x42d2c0 ADD	X11, X21, X11

(1409) 0x42d2c4 CMP	X11, #3

(1409) 0x42d2c8 B.CC	42d308

(1409) 0x42d2cc ADD	X12, X12, X13,LSL #3

(1409) 0x42d2d0 SUB	X11, X21, X13

(1409) 0x42d2d4 ADD	X12, X12, #16

(1409) 0x42d2d8 HINT	#0

(1409) 0x42d2dc HINT	#0

  (1415) 0x42d2e0 LDP	D1, D2, [X12, #1008]

  (1415) 0x42d2e4 SUBS	X11, X11, #4

  (1415) 0x42d2e8 FMUL	D2, D0, D2

  (1415) 0x42d2ec FMUL	D1, D0, D1

  (1415) 0x42d2f0 STP	D1, D2, [X12, #1008]

  (1415) 0x42d2f4 LDP	D1, D2, [X12]

  (1415) 0x42d2f8 FMUL	D2, D0, D2

  (1415) 0x42d2fc FMUL	D1, D0, D1

  (1415) 0x42d300 STP	D1, D2, [X12], #32

  (1415) 0x42d304 B.NE	42d2e0

(1409) 0x42d308 LDP	X6, X22, [SP, #64]

(1409) 0x42d30c LDR	X7, [SP, #96]

(1409) 0x42d310 CMP	X10, X23

(1409) 0x42d314 B.GE	42cd24

(1409) 0x42d318 LDUR	X11, [X29, #456]

(1409) 0x42d31c LDR	X12, [X11]

(1409) 0x42d320 SUB	W11, W23, W10

(1409) 0x42d324 ANDS	X13, X11, #4160

(1409) 0x42d328 B.EQ	42d408

(1409) 0x42d32c ORR	X11, XZR, X10

(1409) 0x42d330 HINT	#0

(1409) 0x42d334 HINT	#0

(1409) 0x42d338 HINT	#0

(1409) 0x42d33c HINT	#0

  (1414) 0x42d340 LDR	D1, [X12, X11,LSL #3]

  (1414) 0x42d344 SUBS	X13, X13, #1

  (1414) 0x42d348 FMUL	D1, D0, D1

  (1414) 0x42d34c STR	D1, [X12, X11,LSL #3]

  (1414) 0x42d350 ADD	X11, X11, #1

  (1414) 0x42d354 B.NE	42d340

(1409) 0x42d358 ORN	X10, XZR, X10

(1409) 0x42d35c ADD	X10, X23, X10

(1409) 0x42d360 CMP	X10, #3

(1409) 0x42d364 B.CC	42cd24

(1409) 0x42d368 B	42d41c

  (1404) 0x42d36c ORR	X14, XZR, X13

  (1404) 0x42d370 ORN	X13, XZR, X13

  (1404) 0x42d374 ADD	X13, X10, X13

  (1404) 0x42d378 CMP	X13, #3

  (1404) 0x42d37c B.CC	42cd24

  (1404) 0x42d380 SUB	X10, X10, X14

  (1404) 0x42d384 UBFM	X13, X14, #61, #60

  (1404) 0x42d388 UBFM	X14, X23, #61, #60

  (1404) 0x42d38c ADD	X13, X13, #24

  (1404) 0x42d390 HINT	#0

  (1404) 0x42d394 HINT	#0

  (1404) 0x42d398 HINT	#0

  (1404) 0x42d39c HINT	#0

    (1405) 0x42d3a0 ADD	X15, X11, X13

    (1405) 0x42d3a4 ADD	X17, X11, X14

    (1405) 0x42d3a8 ADD	X23, X23, #4

    (1405) 0x42d3ac SUBS	X10, X10, #4

    (1405) 0x42d3b0 LDUR	X16, [X15, #488]

    (1405) 0x42d3b4 ADD	X18, X12, X14

    (1405) 0x42d3b8 ADD	X14, X14, #32

    (1405) 0x42d3bc STR	X16, [X17]

    (1405) 0x42d3c0 ADD	X16, X12, X13

    (1405) 0x42d3c4 ADD	X13, X13, #32

    (1405) 0x42d3c8 LDUR	X0, [X15, #496]

    (1405) 0x42d3cc LDUR	D0, [X16, #488]

    (1405) 0x42d3d0 STR	X0, [X17, #8]

    (1405) 0x42d3d4 LDUR	X0, [X15, #504]

    (1405) 0x42d3d8 STR	D0, [X18]

    (1405) 0x42d3dc LDUR	D0, [X16, #496]

    (1405) 0x42d3e0 STR	X0, [X17, #16]

    (1405) 0x42d3e4 LDR	X15, [X15]

    (1405) 0x42d3e8 STR	D0, [X18, #8]

    (1405) 0x42d3ec STR	X15, [X17, #24]

    (1405) 0x42d3f0 LDUR	D0, [X16, #504]

    (1405) 0x42d3f4 STR	D0, [X18, #16]

    (1405) 0x42d3f8 LDR	D0, [X16]

    (1405) 0x42d3fc STR	D0, [X18, #24]

    (1405) 0x42d400 B.NE	42d3a0

  (1404) 0x42d404 B	42cd24

(1409) 0x42d408 ORR	X11, XZR, X10

(1409) 0x42d40c ORN	X10, XZR, X10

(1409) 0x42d410 ADD	X10, X23, X10

(1409) 0x42d414 CMP	X10, #3

(1409) 0x42d418 B.CC	42cd24

(1409) 0x42d41c ADD	X10, X12, X11,LSL #3

(1409) 0x42d420 ADD	X10, X10, #16

  (1413) 0x42d424 LDP	D1, D2, [X10, #1008]

  (1413) 0x42d428 ADD	X11, X11, #4

  (1413) 0x42d42c CMP	X23, X11

  (1413) 0x42d430 FMUL	D2, D0, D2

  (1413) 0x42d434 FMUL	D1, D0, D1

  (1413) 0x42d438 STP	D1, D2, [X10, #1008]

  (1413) 0x42d43c LDP	D1, D2, [X10]

  (1413) 0x42d440 FMUL	D2, D0, D2

  (1413) 0x42d444 FMUL	D1, D0, D1

  (1413) 0x42d448 STP	D1, D2, [X10], #32

  (1413) 0x42d44c B.NE	42d424

(1409) 0x42d450 B	42cd24

0x42d454 ORR	X5, XZR, XZR

0x42d458 ORR	X4, XZR, XZR

0x42d45c B	42d468

0x42d460 LDR	X28, [SP, #80]

0x42d464 LDP	X19, X24, [SP, #8]

0x42d468 LDUR	X8, [X29, #432]

0x42d46c ORR	X0, XZR, X26

0x42d470 LDR	X8, [X8]

0x42d474 LDR	X9, [X8, X22,LSL #3]

0x42d478 ADD	X9, X9, X5

0x42d47c STR	X9, [X8, X22,LSL #3]

0x42d480 LDUR	X8, [X29, #440]

0x42d484 LDR	X8, [X8]

0x42d488 LDR	X9, [X8, X22,LSL #3]

0x42d48c ADD	X9, X9, X4

0x42d490 STR	X9, [X8, X22,LSL #3]

0x42d494 BL	4a2670

0x42d498 ORR	X0, XZR, X27

0x42d49c BL	4a2670

0x42d4a0 LDR	X8, [SP, #48]

0x42d4a4 LDR	X20, [X29, #176]

0x42d4a8 ADRP	X0,

0x42d4ac ADD	X0, X0, #3536

0x42d4b0 LDR	W25, [X8]

0x42d4b4 ORR	W1, WZR, W25

0x42d4b8 BL	40f4b0

0x42d4bc LDUR	X26, [X29, #424]

0x42d4c0 CBNZ	X22, 42d530

0x42d4c4 LDR	X8, [SP, #56]

0x42d4c8 STR	XZR, [X19]

0x42d4cc STR	XZR, [X24]

0x42d4d0 LDR	X8, [X8]

0x42d4d4 LDR	X9, [X8]

0x42d4d8 CMP	X9, #1

0x42d4dc B.LT	42d530

0x42d4e0 LDP	X10, X11, [X29, #944]

0x42d4e4 ORR	X9, XZR, XZR

0x42d4e8 LDR	X10, [X10]

0x42d4ec LDR	X11, [X11]

0x42d4f0 HINT	#0

0x42d4f4 HINT	#0

0x42d4f8 HINT	#0

0x42d4fc HINT	#0

(1403) 0x42d500 LDR	X12, [X10, X9,LSL #3]

(1403) 0x42d504 LDR	X13, [X19]

(1403) 0x42d508 ADD	X12, X13, X12

(1403) 0x42d50c STR	X12, [X19]

(1403) 0x42d510 LDR	X12, [X11, X9,LSL #3]

(1403) 0x42d514 LDR	X13, [X24]

(1403) 0x42d518 ADD	X9, X9, #1

(1403) 0x42d51c ADD	X12, X13, X12

(1403) 0x42d520 STR	X12, [X24]

(1403) 0x42d524 LDR	X12, [X8]

(1403) 0x42d528 CMP	X9, X12

(1403) 0x42d52c B.LT	42d500

0x42d530 ORR	W1, WZR, W25

0x42d534 ADRP	X0,

0x42d538 ADD	X0, X0, #3560

0x42d53c BL	40f4b0

0x42d540 LDR	X8, [X19]

0x42d544 CBZ	X8, 42d7d0

0x42d548 LDP	X23, X21, [X29, #184]

0x42d54c LDR	X19, [X29, #168]

0x42d550 CBNZ	X22, 42d61c

0x42d554 LDUR	X8, [X29, #472]

0x42d558 LDR	X9, [SP, #40]

0x42d55c LDR	X8, [X8]

0x42d560 LDR	X9, [X9]

0x42d564 LDR	X0, [X8, X9,LSL #3]

0x42d568 LDR	X8, [SP, #56]

0x42d56c LDR	X8, [X8]

0x42d570 STR	X0, [X19]

0x42d574 LDR	X9, [X8]

0x42d578 CMP	X9, #1

0x42d57c B.LT	42d600

0x42d580 LDUR	X9, [X29, #432]

0x42d584 LDR	X10, [X9]

0x42d588 LDR	X9, [X20]

0x42d58c LDR	X11, [X10]

0x42d590 SUB	X11, X0, X11

0x42d594 STR	X11, [X19]

0x42d598 LDR	X11, [X10]

0x42d59c STR	X11, [X9]

0x42d5a0 LDR	X11, [X8]

0x42d5a4 CMP	X11, #2

0x42d5a8 B.LT	42d5fc

0x42d5ac ORR	X11, XZR, XZR

0x42d5b0 ADD	X10, X10, #8

0x42d5b4 HINT	#0

0x42d5b8 HINT	#0

0x42d5bc HINT	#0

(1402) 0x42d5c0 UBFM	X12, X11, #61, #60

(1402) 0x42d5c4 LDR	X14, [X19]

(1402) 0x42d5c8 LDR	X13, [X10, X12]

(1402) 0x42d5cc SUB	X13, X14, X13

(1402) 0x42d5d0 STR	X13, [X19]

(1402) 0x42d5d4 ADD	X13, X9, X12

(1402) 0x42d5d8 LDR	X12, [X10, X12]

(1402) 0x42d5dc LDR	X14, [X13]

(1402) 0x42d5e0 ADD	X12, X12, X14

(1402) 0x42d5e4 STR	X12, [X13, #8]

(1402) 0x42d5e8 ADD	X13, X11, #2

(1402) 0x42d5ec ADD	X11, X11, #1

(1402) 0x42d5f0 LDR	X12, [X8]

(1402) 0x42d5f4 CMP	X13, X12

(1402) 0x42d5f8 B.LT	42d5c0

0x42d5fc LDR	X0, [X19]

0x42d600 MOVZ	W1, #8

0x42d604 BL	4a2570

0x42d608 STR	X0, [X23]

0x42d60c LDR	X0, [X19]

0x42d610 MOVZ	W1, #8

0x42d614 BL	4a2570

0x42d618 STR	X0, [X21]

0x42d61c ORR	W1, WZR, W25

0x42d620 ADRP	X0,

0x42d624 ADD	X0, X0, #3584

0x42d628 BL	40f4b0

0x42d62c LDUR	X8, [X29, #472]

0x42d630 LDR	X8, [X8]

0x42d634 LDR	X9, [X8, X26,LSL #3]

0x42d638 CBZ	X22, 42d650

0x42d63c LDR	X10, [X20]

0x42d640 ADD	X10, X10, X22,LSL #3

0x42d644 LDUR	X10, [X10, #504]

0x42d648 SUB	X13, X9, X10

0x42d64c B	42d654

0x42d650 ORR	X13, XZR, XZR

0x42d654 LDUR	X10, [X29, #432]

0x42d658 LDUR	X17, [X29, #464]

0x42d65c LDR	X10, [X10]

0x42d660 LDR	X11, [X8, X17,LSL #3]

0x42d664 LDR	X12, [X10, X22,LSL #3]

0x42d668 SUB	X11, X11, X12

0x42d66c CMP	X9, X11

0x42d670 B.GE	42d6c8

0x42d674 LDUR	X11, [X29, #504]

0x42d678 LDUR	X12, [X29, #448]

0x42d67c LDR	X14, [X23]

0x42d680 UBFM	X16, X13, #61, #60

0x42d684 ADD	X14, X14, X16

0x42d688 LDR	X15, [X21]

0x42d68c LDR	X11, [X11]

0x42d690 LDR	X12, [X12]

0x42d694 ADD	X13, X15, X16

0x42d698 HINT	#0

0x42d69c HINT	#0

(1401) 0x42d6a0 LDR	X15, [X11, X9,LSL #3]

(1401) 0x42d6a4 LDR	D0, [X12, X9,LSL #3]

(1401) 0x42d6a8 ADD	X9, X9, #1

(1401) 0x42d6ac STR	X15, [X14], #8

(1401) 0x42d6b0 LDR	X15, [X8, X17,LSL #3]

(1401) 0x42d6b4 LDR	X16, [X10, X22,LSL #3]

(1401) 0x42d6b8 STR	D0, [X13], #8

(1401) 0x42d6bc SUB	X15, X15, X16

(1401) 0x42d6c0 CMP	X9, X15

(1401) 0x42d6c4 B.LT	42d6a0

0x42d6c8 ORR	W1, WZR, W25

0x42d6cc ADRP	X0,

0x42d6d0 ADD	X0, X0, #3608

0x42d6d4 BL	40f4b0

0x42d6d8 LDUR	X14, [X29, #464]

0x42d6dc SUBS	X8, X22, #1

0x42d6e0 B.LT	42d768

0x42d6e4 CMP	X14, X26

0x42d6e8 B.LE	42d768

0x42d6ec LDUR	X10, [X29, #472]

0x42d6f0 LDR	X9, [X20]

0x42d6f4 SUB	W13, W14, W26

0x42d6f8 ORR	X12, XZR, X26

0x42d6fc ADD	X11, X26, #1

0x42d700 LDR	X10, [X10]

0x42d704 TBZ	W13, #0, 42d71c

0x42d708 LDR	X12, [X9, X8,LSL #3]

0x42d70c LDR	X13, [X10, X26,LSL #3]

0x42d710 SUB	X12, X13, X12

0x42d714 STR	X12, [X10, X26,LSL #3]

0x42d718 ORR	X12, XZR, X11

0x42d71c CMP	X14, X11

0x42d720 B.EQ	42d768

0x42d724 ADD	X10, X10, X12,LSL #3

0x42d728 SUB	X11, X14, X12

0x42d72c ADD	X10, X10, #8

0x42d730 HINT	#0

0x42d734 HINT	#0

0x42d738 HINT	#0

0x42d73c HINT	#0

(1400) 0x42d740 LDR	X12, [X9, X8,LSL #3]

(1400) 0x42d744 LDUR	X13, [X10, #504]

(1400) 0x42d748 SUBS	X11, X11, #2

(1400) 0x42d74c SUB	X12, X13, X12

(1400) 0x42d750 LDR	X13, [X10]

(1400) 0x42d754 STUR	X12, [X10, #504]

(1400) 0x42d758 LDR	X12, [X9, X8,LSL #3]

(1400) 0x42d75c SUB	X12, X13, X12

(1400) 0x42d760 STR	X12, [X10], #16

(1400) 0x42d764 B.NE	42d740

0x42d768 CBNZ	X22, 42d7d0

0x42d76c LDUR	X9, [X29, #472]

0x42d770 LDR	X10, [SP, #40]

0x42d774 LDUR	X27, [X29, #504]

0x42d778 LDR	X8, [X19]

0x42d77c LDR	X22, [X29, #200]

0x42d780 LDR	X9, [X9]

0x42d784 LDR	X10, [X10]

0x42d788 LDR	X0, [X27]

0x42d78c STR	X8, [X9, X10,LSL #3]

0x42d790 BL	4a2670

0x42d794 STR	XZR, [X27]

0x42d798 LDUR	X27, [X29, #448]

0x42d79c LDR	X0, [X27]

0x42d7a0 BL	4a2670

0x42d7a4 STR	XZR, [X27]

0x42d7a8 LDR	X8, [X23]

0x42d7ac LDR	X9, [X22]

0x42d7b0 STR	X8, [X9, #8]

0x42d7b4 LDR	X8, [X21]

0x42d7b8 LDR	X9, [X22]

0x42d7bc STR	X8, [X9, #48]

0x42d7c0 LDR	X8, [X19]

0x42d7c4 LDR	X9, [X22]

0x42d7c8 LDR	X22, [SP, #72]

0x42d7cc STR	X8, [X9, #32]

0x42d7d0 ORR	W1, WZR, W25

0x42d7d4 ADRP	X0,

0x42d7d8 ADD	X0, X0, #3632

0x42d7dc BL	40f4b0

0x42d7e0 LDR	X8, [X24]

0x42d7e4 CBZ	X8, 42da54

0x42d7e8 LDP	X23, X21, [X29, #216]

0x42d7ec LDR	X19, [X29, #208]

0x42d7f0 CBNZ	X22, 42d8bc

0x42d7f4 LDUR	X8, [X29, #480]

0x42d7f8 LDR	X9, [SP, #40]

0x42d7fc LDR	X8, [X8]

0x42d800 LDR	X9, [X9]

0x42d804 LDR	X0, [X8, X9,LSL #3]

0x42d808 LDR	X8, [SP, #56]

0x42d80c LDR	X8, [X8]

0x42d810 STR	X0, [X19]

0x42d814 LDR	X9, [X8]

0x42d818 CMP	X9, #1

0x42d81c B.LT	42d8a0

0x42d820 LDUR	X9, [X29, #440]

0x42d824 LDR	X10, [X9]

0x42d828 LDR	X9, [X20]

0x42d82c LDR	X11, [X10]

0x42d830 SUB	X11, X0, X11

0x42d834 STR	X11, [X19]

0x42d838 LDR	X11, [X10]

0x42d83c STR	X11, [X9]

0x42d840 LDR	X11, [X8]

0x42d844 CMP	X11, #2

0x42d848 B.LT	42d89c

0x42d84c ORR	X11, XZR, XZR

0x42d850 ADD	X10, X10, #8

0x42d854 HINT	#0

0x42d858 HINT	#0

0x42d85c HINT	#0

(1399) 0x42d860 UBFM	X12, X11, #61, #60

(1399) 0x42d864 LDR	X14, [X19]

(1399) 0x42d868 LDR	X13, [X10, X12]

(1399) 0x42d86c SUB	X13, X14, X13

(1399) 0x42d870 STR	X13, [X19]

(1399) 0x42d874 ADD	X13, X9, X12

(1399) 0x42d878 LDR	X12, [X10, X12]

(1399) 0x42d87c LDR	X14, [X13]

(1399) 0x42d880 ADD	X12, X12, X14

(1399) 0x42d884 STR	X12, [X13, #8]

(1399) 0x42d888 ADD	X13, X11, #2

(1399) 0x42d88c ADD	X11, X11, #1

(1399) 0x42d890 LDR	X12, [X8]

(1399) 0x42d894 CMP	X13, X12

(1399) 0x42d898 B.LT	42d860

0x42d89c LDR	X0, [X19]

0x42d8a0 MOVZ	W1, #8

0x42d8a4 BL	4a2570

0x42d8a8 STR	X0, [X23]

0x42d8ac LDR	X0, [X19]

0x42d8b0 MOVZ	W1, #8

0x42d8b4 BL	4a2570

0x42d8b8 STR	X0, [X21]

0x42d8bc ORR	W1, WZR, W25

0x42d8c0 ADRP	X0,

0x42d8c4 ADD	X0, X0, #3656

0x42d8c8 BL	40f4b0

0x42d8cc LDUR	X8, [X29, #480]

0x42d8d0 LDR	X8, [X8]

0x42d8d4 LDR	X9, [X8, X26,LSL #3]

0x42d8d8 CBZ	X22, 42d8f0

0x42d8dc LDR	X10, [X20]

0x42d8e0 ADD	X10, X10, X22,LSL #3

0x42d8e4 LDUR	X10, [X10, #504]

0x42d8e8 SUB	X13, X9, X10

0x42d8ec B	42d8f4

0x42d8f0 ORR	X13, XZR, XZR

0x42d8f4 LDUR	X10, [X29, #440]

0x42d8f8 LDUR	X17, [X29, #464]

0x42d8fc LDR	X10, [X10]

0x42d900 LDR	X11, [X8, X17,LSL #3]

0x42d904 LDR	X12, [X10, X22,LSL #3]

0x42d908 SUB	X11, X11, X12

0x42d90c CMP	X9, X11

0x42d910 B.GE	42d968

0x42d914 LDUR	X12, [X29, #456]

0x42d918 LDR	X14, [X23]

0x42d91c LDR	X15, [X21]

0x42d920 UBFM	X16, X13, #61, #60

0x42d924 ADD	X13, X15, X16

0x42d928 LDR	X11, [X28]

0x42d92c LDR	X12, [X12]

0x42d930 ADD	X14, X14, X16

0x42d934 HINT	#0

0x42d938 HINT	#0

0x42d93c HINT	#0

(1398) 0x42d940 LDR	X15, [X11, X9,LSL #3]

(1398) 0x42d944 LDR	D0, [X12, X9,LSL #3]

(1398) 0x42d948 ADD	X9, X9, #1

(1398) 0x42d94c STR	X15, [X14], #8

(1398) 0x42d950 LDR	X15, [X8, X17,LSL #3]

(1398) 0x42d954 LDR	X16, [X10, X22,LSL #3]

(1398) 0x42d958 STR	D0, [X13], #8

(1398) 0x42d95c SUB	X15, X15, X16

(1398) 0x42d960 CMP	X9, X15

(1398) 0x42d964 B.LT	42d940

0x42d968 ORR	W1, WZR, W25

0x42d96c ADRP	X0,

0x42d970 ADD	X0, X0, #3680

0x42d974 BL	40f4b0

0x42d978 LDUR	X14, [X29, #464]

0x42d97c SUBS	X8, X22, #1

0x42d980 B.LT	42d9f4

0x42d984 CMP	X14, X26

0x42d988 B.LE	42d9f4

0x42d98c LDUR	X10, [X29, #480]

0x42d990 LDR	X9, [X20]

0x42d994 SUB	W12, W14, W26

0x42d998 ADD	X11, X26, #1

0x42d99c LDR	X10, [X10]

0x42d9a0 TBZ	W12, #0, 42d9b8

0x42d9a4 LDR	X12, [X9, X8,LSL #3]

0x42d9a8 LDR	X13, [X10, X26,LSL #3]

0x42d9ac SUB	X12, X13, X12

0x42d9b0 STR	X12, [X10, X26,LSL #3]

0x42d9b4 ORR	X26, XZR, X11

0x42d9b8 CMP	X14, X11

0x42d9bc B.EQ	42d9f4

0x42d9c0 ADD	X10, X10, X26,LSL #3

0x42d9c4 SUB	X11, X14, X26

0x42d9c8 ADD	X10, X10, #8

(1397) 0x42d9cc LDR	X12, [X9, X8,LSL #3]

(1397) 0x42d9d0 LDUR	X13, [X10, #504]

(1397) 0x42d9d4 SUBS	X11, X11, #2

(1397) 0x42d9d8 SUB	X12, X13, X12

(1397) 0x42d9dc LDR	X13, [X10]

(1397) 0x42d9e0 STUR	X12, [X10, #504]

(1397) 0x42d9e4 LDR	X12, [X9, X8,LSL #3]

(1397) 0x42d9e8 SUB	X12, X13, X12

(1397) 0x42d9ec STR	X12, [X10], #16

(1397) 0x42d9f0 B.NE	42d9cc

0x42d9f4 CBNZ	X22, 42da54

0x42d9f8 LDUR	X9, [X29, #480]

0x42d9fc LDR	X10, [SP, #40]

0x42da00 LDR	X8, [X19]

0x42da04 LDR	X0, [X28]

0x42da08 LDR	X20, [X29, #232]

0x42da0c LDR	X9, [X9]

0x42da10 LDR	X10, [X10]

0x42da14 STR	X8, [X9, X10,LSL #3]

0x42da18 BL	4a2670

0x42da1c LDUR	X22, [X29, #456]

0x42da20 STR	XZR, [X28]

0x42da24 LDR	X0, [X22]

0x42da28 BL	4a2670

0x42da2c STR	XZR, [X22]

0x42da30 LDR	X8, [X23]

0x42da34 LDR	X9, [X20]

0x42da38 STR	X8, [X9, #8]

0x42da3c LDR	X8, [X21]

0x42da40 LDR	X9, [X20]

0x42da44 STR	X8, [X9, #48]

0x42da48 LDR	X8, [X19]

0x42da4c LDR	X9, [X20]

0x42da50 STR	X8, [X9, #32]

0x42da54 LDR	D8, [SP, #176]

0x42da58 LDP	X20, X19, [SP, #272]

0x42da5c LDP	X22, X21, [SP, #256]

0x42da60 LDP	X24, X23, [SP, #240]

0x42da64 LDP	X26, X25, [SP, #224]

0x42da68 LDP	X28, X27, [SP, #208]

0x42da6c LDP	X29, X30, [SP, #192]

0x42da70 ADD	SP, SP, #288

0x42da74 RET

0x42da78 HINT	#0

0x42da7c HINT	#0

0x455d1c HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	par_interp.c:2726-3155
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_interp.c:2726-2730,2740-2741,2750-2822,2828-2831,2840,2848-2865,2872-2945,2955-2975,2983-2986,2994-3007,3013,3023-3044,3050-3082,3091-3116,3122-3155.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 77.17 to 6.00 cycles (12.86x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 22% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 77.17 to 10.00 cycles (7.72x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 77.17 to 10.50 cycles (7.35x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 1556 bytes. The binary function is storing 512 bytes.

General properties

nb instructions	454
loop length	1816
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

52.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	29.50	29.50	36.50	36.50	36.50	36.50	1.00	1.00	0.00	0.00	77.17	76.83	77.00	26.00	26.00
cycles	29.50	29.50	36.50	36.50	36.50	36.50	1.00	1.00	0.00	0.00	77.17	76.83	77.00	26.00	26.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	52.00
Overall L1	77.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 77.17 cycles. At this rate:

21% of peak load performance is reached (20.16 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.63 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42c720

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D8, [SP, #176]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP X29, X30, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X9, X20, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X6, X7, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X26, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X4, X5, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X0, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X8, X9, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X28, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4a4720 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a4700 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D0, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
SUB X10, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X19, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X22, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STR X20, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SDIV X8, X9, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
MADD X23, X8, X22, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X11, X8, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X27, X9, X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FCMP D0, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.LE 42cbe8 <.omp_outlined..46+0x4c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X27, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 42cbb4 <.omp_outlined..46+0x494>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X12, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X14, X16, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X2, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X5, [X12, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X11, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X14, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X16, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X18, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X3, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42c808 <.omp_outlined..46+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBNZ X22, 42cbcc <.omp_outlined..46+0x4ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X11, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X20, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [X11, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X10, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X9, [X10, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X19, X24, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X23, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STR X22, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X27, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.LT 42d4a0 <.omp_outlined..46+0xd80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS X10, X27, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 42cc98 <.omp_outlined..46+0x578>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X11, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X8, X22, X8, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X8, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X13, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X11, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X11, X12, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X13, X13, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42cc74 <.omp_outlined..46+0x554>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X27, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 42d4a0 <.omp_outlined..46+0xd80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X26, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X3, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X20, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X27, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X3, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 42d454 <.omp_outlined..46+0xd34>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X9, X8, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X28, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X4, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X5, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X27, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X26, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X30, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X24, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X10, X11, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X6, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X8, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 42cd30 <.omp_outlined..46+0x610>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
ORR X5, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X4, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42d468 <.omp_outlined..46+0xd48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X19, X24, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X0, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X8, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X9, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X9, [X8, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X8, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X9, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X9, [X8, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X20, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <4db4a8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3536	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W25, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X26, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X22, 42d530 <.omp_outlined..46+0xe10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42d530 <.omp_outlined..46+0xe10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X10, X11, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
HINT #0
HINT #0
HINT #0
HINT #0
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4db534>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3560	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X8, 42d7d0 <.omp_outlined..46+0x10b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X23, X21, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X19, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X22, 42d61c <.omp_outlined..46+0xefc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42d600 <.omp_outlined..46+0xee0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X11, X0, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X11, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42d5fc <.omp_outlined..46+0xedc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X11, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
LDR X0, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4db620>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3584	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X8, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X22, 42d650 <.omp_outlined..46+0xf30>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X10, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X10, [X10, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X13, X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42d654 <.omp_outlined..46+0xf34>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X13, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X10, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X17, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X8, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X10, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X11, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 42d6c8 <.omp_outlined..46+0xfa8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X11, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X12, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X16, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X14, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X15, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X15, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4db6cc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3608	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X14, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS X8, X22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42d768 <.omp_outlined..46+0x1048>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 42d768 <.omp_outlined..46+0x1048>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X10, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W13, W14, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X12, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
TBZ W13, #0, 42d71c <.omp_outlined..46+0xffc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X12, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X10, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X12, X13, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X12, [X10, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X12, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X14, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42d768 <.omp_outlined..46+0x1048>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X10, X10, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X11, X14, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
CBNZ X22, 42d7d0 <.omp_outlined..46+0x10b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X27, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X9, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR XZR, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X27, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR XZR, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X9, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X9, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X9, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4db7d4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3632	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X8, 42da54 <.omp_outlined..46+0x1334>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X23, X21, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X19, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X22, 42d8bc <.omp_outlined..46+0x119c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42d8a0 <.omp_outlined..46+0x1180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X11, X0, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X11, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42d89c <.omp_outlined..46+0x117c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X11, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
LDR X0, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4db8c0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3656	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X8, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X22, 42d8f0 <.omp_outlined..46+0x11d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X10, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X10, [X10, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X13, X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42d8f4 <.omp_outlined..46+0x11d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X13, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X10, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X17, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X8, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X10, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X11, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 42d968 <.omp_outlined..46+0x1248>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X12, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X16, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X15, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X14, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4db96c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3680	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X14, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS X8, X22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42d9f4 <.omp_outlined..46+0x12d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 42d9f4 <.omp_outlined..46+0x12d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X10, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W12, W14, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
TBZ W12, #0, 42d9b8 <.omp_outlined..46+0x1298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X12, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X10, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X12, X13, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X12, [X10, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X26, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X14, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42d9f4 <.omp_outlined..46+0x12d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X10, X10, X26,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X11, X14, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBNZ X22, 42da54 <.omp_outlined..46+0x1334>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X20, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X9, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X22, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR XZR, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X9, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X9, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X9, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR D8, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X20, X19, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Source file and lines	par_interp.c:2726-3155
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 77.17 to 10.50 cycles (7.35x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 1556 bytes. The binary function is storing 512 bytes.

General properties

nb instructions	454
loop length	1816
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

52.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	29.50	29.50	36.50	36.50	36.50	36.50	1.00	1.00	0.00	0.00	77.17	76.83	77.00	26.00	26.00
cycles	29.50	29.50	36.50	36.50	36.50	36.50	1.00	1.00	0.00	0.00	77.17	76.83	77.00	26.00	26.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	52.00
Overall L1	77.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 77.17 cycles. At this rate:

21% of peak load performance is reached (20.16 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.63 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42c720

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D8, [SP, #176]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP X29, X30, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X9, X20, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X6, X7, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X26, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X4, X5, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X0, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X8, X9, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X28, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4a4720 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a4700 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D0, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
SUB X10, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X19, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X22, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STR X20, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SDIV X8, X9, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
MADD X23, X8, X22, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X11, X8, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X27, X9, X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FCMP D0, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.LE 42cbe8 <.omp_outlined..46+0x4c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X27, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 42cbb4 <.omp_outlined..46+0x494>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X12, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X14, X16, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X2, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X5, [X12, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X11, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X14, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X16, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X18, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X1, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X3, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42c808 <.omp_outlined..46+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBNZ X22, 42cbcc <.omp_outlined..46+0x4ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X11, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X20, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [X11, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X10, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X9, [X10, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X19, X24, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X23, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STR X22, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X27, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.LT 42d4a0 <.omp_outlined..46+0xd80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS X10, X27, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 42cc98 <.omp_outlined..46+0x578>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X11, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X8, X22, X8, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X8, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X13, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X11, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X11, X12, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X13, X13, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42cc74 <.omp_outlined..46+0x554>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X27, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X27, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 42d4a0 <.omp_outlined..46+0xd80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X26, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X3, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X20, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X27, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X3, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 42d454 <.omp_outlined..46+0xd34>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X9, X8, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X28, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X4, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X5, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X27, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X26, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X30, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X24, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X10, X11, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X6, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X8, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 42cd30 <.omp_outlined..46+0x610>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
ORR X5, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X4, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42d468 <.omp_outlined..46+0xd48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X19, X24, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X0, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X8, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X9, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X9, [X8, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X8, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X9, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X9, [X8, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X20, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <4db4a8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3536	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W25, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X26, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X22, 42d530 <.omp_outlined..46+0xe10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR XZR, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42d530 <.omp_outlined..46+0xe10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X10, X11, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
HINT #0
HINT #0
HINT #0
HINT #0
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4db534>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3560	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X8, 42d7d0 <.omp_outlined..46+0x10b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X23, X21, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X19, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X22, 42d61c <.omp_outlined..46+0xefc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42d600 <.omp_outlined..46+0xee0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X11, X0, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X11, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42d5fc <.omp_outlined..46+0xedc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X11, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
LDR X0, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4db620>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3584	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X8, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X22, 42d650 <.omp_outlined..46+0xf30>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X10, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X10, [X10, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X13, X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42d654 <.omp_outlined..46+0xf34>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X13, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X10, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X17, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X8, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X10, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X11, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 42d6c8 <.omp_outlined..46+0xfa8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X11, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X12, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X16, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X14, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X15, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X15, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4db6cc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3608	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X14, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS X8, X22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42d768 <.omp_outlined..46+0x1048>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 42d768 <.omp_outlined..46+0x1048>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X10, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W13, W14, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X12, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
TBZ W13, #0, 42d71c <.omp_outlined..46+0xffc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X12, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X10, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X12, X13, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X12, [X10, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X12, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X14, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42d768 <.omp_outlined..46+0x1048>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X10, X10, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X11, X14, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
CBNZ X22, 42d7d0 <.omp_outlined..46+0x10b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X27, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X9, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR XZR, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X27, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR XZR, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X9, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X9, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X22, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X9, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4db7d4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3632	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X8, 42da54 <.omp_outlined..46+0x1334>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X23, X21, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X19, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X22, 42d8bc <.omp_outlined..46+0x119c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42d8a0 <.omp_outlined..46+0x1180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X11, X0, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X11, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X11, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X11, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42d89c <.omp_outlined..46+0x117c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X11, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
LDR X0, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4db8c0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3656	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X8, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X22, 42d8f0 <.omp_outlined..46+0x11d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X10, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X10, [X10, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X13, X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42d8f4 <.omp_outlined..46+0x11d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X13, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X10, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X17, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X8, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X10, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X11, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 42d968 <.omp_outlined..46+0x1248>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X12, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X16, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X15, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X14, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
ORR W1, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4db96c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3680	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X14, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS X8, X22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42d9f4 <.omp_outlined..46+0x12d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X14, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 42d9f4 <.omp_outlined..46+0x12d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X10, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W12, W14, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
TBZ W12, #0, 42d9b8 <.omp_outlined..46+0x1298>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X12, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X10, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X12, X13, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X12, [X10, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X26, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X14, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 42d9f4 <.omp_outlined..46+0x12d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X10, X10, X26,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X11, X14, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBNZ X22, 42da54 <.omp_outlined..46+0x1334>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X20, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X9, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X22, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR XZR, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X9, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X9, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X9, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR D8, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X20, X19, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..46–	0.02	0.01
○Loop 1401 - par_interp.c:3053-3056 - exec	0.02	0
○Loop 1417 - par_interp.c:2848-2860 - exec	0	0
▼Loop 1418 - par_interp.c:2760-2822 - exec–	0	0
▼Loop 1419 - par_interp.c:2760-2822 - exec–	0	0
○Loop 1423 - par_interp.c:2763-2764 - exec	0	0
○Loop 1420 - par_interp.c:2775-2789 - exec	0	0
○Loop 1422 - par_interp.c:2766-2767 - exec	0	0
○Loop 1429 - par_interp.c:2795-2809 - exec	0	0
○Loop 1421 - par_interp.c:2766-2767 - exec	0	0
○Loop 1427 - par_interp.c:2819-2820 - exec	0	0
○Loop 1425 - par_interp.c:2821-2822 - exec	0	0
○Loop 1426 - par_interp.c:2821-2822 - exec	0	0
○Loop 1424 - par_interp.c:2763-2764 - exec	0	0
○Loop 1428 - par_interp.c:2819-2820 - exec	0	0
▼Loop 1409 - par_interp.c:2874-2975 - exec–	0	0
○Loop 1416 - par_interp.c:2942-2943 - exec	0	0
○Loop 1414 - par_interp.c:2944-2945 - exec	0	0
▼Loop 1404 - par_interp.c:2874-2975 - exec–	0	0
○Loop 1411 - par_interp.c:2903-2907 - exec	0	0
○Loop 1406 - par_interp.c:2972-2975 - exec	0	0
○Loop 1408 - par_interp.c:2959-2962 - exec	0	0
○Loop 1407 - par_interp.c:2959-2962 - exec	0	0
○Loop 1412 - par_interp.c:2895-2899 - exec	0	0
○Loop 1405 - par_interp.c:2972-2975 - exec	0	0
○Loop 1410 - par_interp.c:2919-2930 - exec	0	0
○Loop 1415 - par_interp.c:2942-2943 - exec	0	0
○Loop 1413 - par_interp.c:2944-2945 - exec	0	0
○Loop 1398 - par_interp.c:3126-3129 - exec	0	0
○Loop 1402 - par_interp.c:3027-3031 - exec	0	0
○Loop 1400 - par_interp.c:3067-3069 - exec	0	0
○Loop 1399 - par_interp.c:3099-3103 - exec	0	0
○Loop 1403 - par_interp.c:3000-3003 - exec	0	0
○Loop 1397 - par_interp.c:3140-3142 - exec	0	0

Report Configuration

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

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Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code