OV - exec - Function hypre_BoomerAMGCoarsenPMIS

	Function: hypre_BoomerAMGCoarsenPMIS	Module: exec	Source: par_coarsen.c:1980-2624 [...]	Coverage: 0.02%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c: 1980 - 2624

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1980: {

1981: #ifdef HYPRE_PROFILE

1982:    hypre_profile_times[HYPRE_TIMER_ID_PMIS] -= hypre_MPI_Wtime();

1983: #endif

1984:

1985:    MPI_Comm 	       comm            = hypre_ParCSRMatrixComm(S);

1986:    hypre_ParCSRCommPkg      *comm_pkg        = hypre_ParCSRMatrixCommPkg(S);

1987:    hypre_ParCSRCommHandle   *comm_handle;

1988:

1989:    hypre_CSRMatrix    *S_diag          = hypre_ParCSRMatrixDiag(S);

1990:    HYPRE_Int                *S_diag_i        = hypre_CSRMatrixI(S_diag);

1991:    HYPRE_Int                *S_diag_j        = hypre_CSRMatrixJ(S_diag);

1992:

1993:    hypre_CSRMatrix    *S_offd          = hypre_ParCSRMatrixOffd(S);

1994:    HYPRE_Int                *S_offd_i        = hypre_CSRMatrixI(S_offd);

1995:    HYPRE_Int                *S_offd_j;

1996:

1997:    HYPRE_Int                 num_variables   = hypre_CSRMatrixNumRows(S_diag);

[...]

2058:    if (debug_flag == 3) wall_time = time_getWallclockSeconds();

2059:    hypre_MPI_Comm_size(comm,&num_procs);

2060:    hypre_MPI_Comm_rank(comm,&my_id);

2061:

2062:    if (!comm_pkg)

2063:    {

2064:         comm_pkg = hypre_ParCSRMatrixCommPkg(A);

2065:    }

2066:

2067:    if (!comm_pkg)

2068:    {

2069:         hypre_MatvecCommPkgCreate(A);

2070:         comm_pkg = hypre_ParCSRMatrixCommPkg(A);

2071:    }

2072:

2073:    num_sends = hypre_ParCSRCommPkgNumSends(comm_pkg);

2074:

2075:    int_buf_data = hypre_CTAlloc(HYPRE_Int, hypre_ParCSRCommPkgSendMapStart(comm_pkg,

2076:                                                 num_sends));

2077:    buf_data = hypre_CTAlloc(HYPRE_Real, hypre_ParCSRCommPkgSendMapStart(comm_pkg,

2078:                                                 num_sends));

2079:

2080:    num_cols_offd = hypre_CSRMatrixNumCols(S_offd);

2081:

2082:    S_diag_j = hypre_CSRMatrixJ(S_diag);

2083:

2084:    if (num_cols_offd)

2085:    {

2086:       S_offd_j = hypre_CSRMatrixJ(S_offd);

[...]

2100:    measure_array = hypre_CTAlloc(HYPRE_Real, num_variables+num_cols_offd);

2101:

2102:    /* first calculate the local part of the sums for the external nodes */

2103: #ifdef HYPRE_USING_OPENMP

2104:    HYPRE_Int *measure_array_temp = hypre_CTAlloc(HYPRE_Int, num_variables+num_cols_offd);

2105:

2106: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

[...]

2113: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

[...]

2126:    if (num_procs > 1)

2127:    comm_handle = hypre_ParCSRCommHandleCreate(2, comm_pkg,

2128:                         &measure_array[num_variables], buf_data);

2129:

2130:    /* calculate the local part for the local nodes */

2131: #ifdef HYPRE_USING_OPENMP

2132: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

[...]

2139: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

[...]

2145:    hypre_TFree(measure_array_temp);

[...]

2154:    if (num_procs > 1)

2155:    hypre_ParCSRCommHandleDestroy(comm_handle);

2156:

2157:    /* now add the externally calculated part of the local nodes to the local nodes */

2158:    index = 0;

2159:    for (i=0; i < num_sends; i++)

2160:    {

2161:       start = hypre_ParCSRCommPkgSendMapStart(comm_pkg, i);

2162:       for (j=start; j < hypre_ParCSRCommPkgSendMapStart(comm_pkg, i+1); j++)

2163:             measure_array[hypre_ParCSRCommPkgSendMapElmt(comm_pkg,j)]

2164:                         += buf_data[index++];

2165:    }

2166:

2167:    /* set the measures of the external nodes to zero */

2168:    for (i=num_variables; i < num_variables+num_cols_offd; i++)

2169:    {

2170:       measure_array[i] = 0;

[...]

2176:    if (CF_init == 2 || CF_init == 4)

2177:       hypre_BoomerAMGIndepSetInit(S, measure_array, 1);

2178:    else

2179:       hypre_BoomerAMGIndepSetInit(S, measure_array, 0);

[...]

2186:    if (num_cols_offd)

2187:       graph_array_offd = hypre_CTAlloc(HYPRE_Int, num_cols_offd);

2188:    else

2189:       graph_array_offd = NULL;

2190:

2191:    for (ig = 0; ig < num_cols_offd; ig++)

2192:       graph_array_offd[ig] = ig;

2193:

2194:    graph_offd_size = num_cols_offd;

2195:

2196:    /* now the local part of the graph array, and the local CF_marker array */

2197:    graph_array = hypre_CTAlloc(HYPRE_Int, num_variables);

2198:

2199:    if (CF_init==1)

2200:    {

2201:       CF_marker = *CF_marker_ptr;

2202:       cnt = 0;

2203:       for (i=0; i < num_variables; i++)

2204:       {

2205:          if ( (S_offd_i[i+1]-S_offd_i[i]) > 0 || CF_marker[i] == -1)

[...]

2211:             if (measure_array[i] >= 1.0 ||

2212:                 (S_diag_i[i+1]-S_diag_i[i]) > 0)

[...]

2219:                CF_marker[i] = F_PT;

2220:             }

2221:          }

2222:          else if (CF_marker[i] == SF_PT)

2223:             measure_array[i] = 0;

[...]

2230:       CF_marker = hypre_CTAlloc(HYPRE_Int, num_variables);

2231:       cnt = 0;

2232:       for (i=0; i < num_variables; i++)

2233:       {

2234:          CF_marker[i] = 0;

2235:          if ( (S_diag_i[i+1]-S_diag_i[i]) == 0

2236:                 && (S_offd_i[i+1]-S_offd_i[i]) == 0)

2237:          {

2238:             CF_marker[i] = SF_PT; /* an isolated fine grid */

2239:             if (CF_init == 3 || CF_init == 4) CF_marker[i] = C_PT;

2240:             measure_array[i] = 0;

2241:          }

2242:          else

2243:             graph_array[cnt++] = i;

2244:       }

2245:    }

2246:    graph_size = cnt;

2247:

2248:    /* now the off-diagonal part of CF_marker */

2249:    if (num_cols_offd)

2250:      CF_marker_offd = hypre_CTAlloc(HYPRE_Int, num_cols_offd);

2251:    else

2252:      CF_marker_offd = NULL;

2253:

2254:    for (i=0; i < num_cols_offd; i++)

2255: 	CF_marker_offd[i] = 0;

[...]

2262:    for (i = 0; i < num_sends; i++)

2263:      {

2264:        start = hypre_ParCSRCommPkgSendMapStart(comm_pkg, i);

2265:        for (j = start; j < hypre_ParCSRCommPkgSendMapStart(comm_pkg, i+1); j++)

2266: 	 {

2267: 	   jrow = hypre_ParCSRCommPkgSendMapElmt(comm_pkg,j);

2268: 	   buf_data[index++] = measure_array[jrow];

2269:          }

2270:      }

2271:

2272:    if (num_procs > 1)

2273:      {

2274:        comm_handle = hypre_ParCSRCommHandleCreate(1, comm_pkg, buf_data,

2275: 						  &measure_array[num_variables]);

2276:

2277:        hypre_ParCSRCommHandleDestroy(comm_handle);

2278:

2279:      }

2280:

2281:    if (debug_flag == 3)

2282:    {

2283:       wall_time = time_getWallclockSeconds() - wall_time;

2284:       hypre_printf("Proc = %d    Initialize CLJP phase = %f\n",

2285:                      my_id, wall_time);

2286:    }

2287:

2288:    HYPRE_Int                *graph_array2 = hypre_CTAlloc(HYPRE_Int, num_variables);

2289:    HYPRE_Int *graph_array_offd2 = NULL;

2290:    if (num_cols_offd)

2291:      graph_array_offd2 = hypre_CTAlloc(HYPRE_Int, num_cols_offd);

[...]

2305:      hypre_MPI_Allreduce(&graph_size,&global_graph_size,1,HYPRE_MPI_INT,hypre_MPI_SUM,comm);

2306:

2307:      if (global_graph_size == 0)

[...]

2320:       if (!CF_init || iter)

[...]

2327: #pragma omp parallel for private(ig, i) HYPRE_SMP_SCHEDULE

[...]

2338: #pragma omp parallel for private(ig, i) HYPRE_SMP_SCHEDULE

[...]

2354: #pragma omp parallel for private(ig, i, jS, j, jj) HYPRE_SMP_SCHEDULE

[...]

2393:       if (num_procs > 1)

2394:       {

2395:          comm_handle = hypre_ParCSRCommHandleCreate(12, comm_pkg,

2396: 		CF_marker_offd, int_buf_data);

2397:

2398:          hypre_ParCSRCommHandleDestroy(comm_handle);

2399:       }

2400:

2401:       index = 0;

2402:       for (i = 0; i < num_sends; i++)

2403:       {

2404:          start = hypre_ParCSRCommPkgSendMapStart(comm_pkg, i);

2405:          for (j=start; j < hypre_ParCSRCommPkgSendMapStart(comm_pkg, i+1); j++)

2406:          {

2407:             elmt = hypre_ParCSRCommPkgSendMapElmt(comm_pkg,j);

2408:             if (!int_buf_data[index] && CF_marker[elmt] > 0)

2409:             {

2410:                CF_marker[elmt] = 0;

2411:                index++;

2412:             }

2413:             else

2414:             {

2415:                int_buf_data[index++] = CF_marker[elmt];

2416:             }

2417:          }

2418:       }

2419:

2420:       if (num_procs > 1)

2421:       {

2422:          comm_handle = hypre_ParCSRCommHandleCreate(11, comm_pkg, int_buf_data,

2423:         	CF_marker_offd);

2424:

2425:          hypre_ParCSRCommHandleDestroy(comm_handle);

[...]

2435: #pragma omp parallel for private(ig, i, jS, j) HYPRE_SMP_SCHEDULE

[...]

2492:       for (i = 0; i < num_sends; i++)

2493:       {

2494:         start = hypre_ParCSRCommPkgSendMapStart(comm_pkg, i);

2495:         for (j = start; j < hypre_ParCSRCommPkgSendMapStart(comm_pkg, i+1); j++)

2496:                 int_buf_data[index++]

2497:                  = CF_marker[hypre_ParCSRCommPkgSendMapElmt(comm_pkg,j)];

2498:       }

2499:

2500:       if (num_procs > 1)

2501:       {

2502:       comm_handle = hypre_ParCSRCommHandleCreate(11, comm_pkg, int_buf_data,

2503:         CF_marker_offd);

2504:

2505:       hypre_ParCSRCommHandleDestroy(comm_handle);

[...]

2513:     prefix_sum_workspace = hypre_TAlloc(HYPRE_Int, 2*(hypre_NumThreads() + 1));

2514:

2515: #ifdef HYPRE_USING_OPENMP

2516: #pragma omp parallel private(ig,i)

[...]

2581:      HYPRE_Int *temp = graph_array;

2582:      graph_array = graph_array2;

2583:      graph_array2 = temp;

[...]

2589:      hypre_TFree(prefix_sum_workspace);

[...]

2608:    hypre_TFree(measure_array);

2609:    hypre_TFree(graph_array);

2610:    hypre_TFree(graph_array2);

2611:    hypre_TFree(graph_array_offd2);

2612:    if (num_cols_offd) hypre_TFree(graph_array_offd);

2613:    hypre_TFree(buf_data);

2614:    hypre_TFree(int_buf_data);

2615:    hypre_TFree(CF_marker_offd);

2616:    /*if (num_procs > 1) hypre_CSRMatrixDestroy(S_ext);*/

2617:

2618:    *CF_marker_ptr   = CF_marker;

[...]

2624:    return (ierr);

0x420090 SUB	SP, SP, #352

0x420094 STR	D8, [SP, #240]

0x420098 STP	X29, X30, [SP, #256]

0x42009c STP	X28, X27, [SP, #272]

0x4200a0 STP	X26, X25, [SP, #288]

0x4200a4 STP	X24, X23, [SP, #304]

0x4200a8 STP	X22, X21, [SP, #320]

0x4200ac STP	X20, X19, [SP, #336]

0x4200b0 ADD	X29, SP, #256

0x4200b4 LDR	X8, [X0]

0x4200b8 LDP	X26, X27, [X0, #56]

0x4200bc LDR	X22, [X0, #112]

0x4200c0 ORR	X28, XZR, X4

0x4200c4 ORR	X25, XZR, X3

0x4200c8 ORR	X20, XZR, X1

0x4200cc CMP	X3, #3

0x4200d0 STP	X2, X8, [SP, #64]

0x4200d4 LDP	X8, X9, [X26]

0x4200d8 ORR	X19, XZR, X0

0x4200dc STUR	X8, [X29, #504]

0x4200e0 STUR	X9, [X29, #480]

0x4200e4 LDR	X8, [X27]

0x4200e8 STUR	X8, [X29, #472]

0x4200ec LDR	X8, [X26, #16]

0x4200f0 STP	XZR, X8, [X29, #960]

0x4200f4 B.NE	420100

0x4200f8 BL	4a47b0

0x4200fc FMOV	D8, D0

0x420100 LDR	X21, [SP, #72]

0x420104 ADD	X1, SP, #112

0x420108 ORR	X0, XZR, X21

0x42010c BL	4a3b70

0x420110 ORR	X0, XZR, X21

0x420114 ADD	X1, SP, #120

0x420118 BL	4a3ba0

0x42011c CBNZ	X22, 420134

0x420120 LDR	X22, [X20, #112]

0x420124 CBNZ	X22, 420134

0x420128 ORR	X0, XZR, X20

0x42012c BL	47d700

0x420130 LDR	X22, [X20, #112]

0x420134 LDR	X21, [X22, #8]

0x420138 LDR	X8, [X22, #24]

0x42013c MOVZ	W1, #8

0x420140 LDR	X0, [X8, X21,LSL #3]

0x420144 BL	4a2570

0x420148 LDR	X8, [X22, #24]

0x42014c ORR	X23, XZR, X0

0x420150 MOVZ	W1, #8

0x420154 LDR	X0, [X8, X21,LSL #3]

0x420158 BL	4a2570

0x42015c LDR	X8, [X27, #24]

0x420160 LDR	X9, [X26, #8]

0x420164 ORR	X24, XZR, X0

0x420168 STUR	X8, [X29, #448]

0x42016c STUR	X9, [X29, #480]

0x420170 CBZ	X8, 42017c

0x420174 LDR	X9, [X27, #8]

0x420178 STUR	X9, [X29, #464]

0x42017c LDUR	X9, [X29, #456]

0x420180 MOVZ	W1, #8

0x420184 ADD	X0, X9, X8

0x420188 BL	4a2570

0x42018c LDP	X9, X8, [X29, #960]

0x420190 STUR	X0, [X29, #424]

0x420194 MOVZ	W1, #8

0x420198 ADD	X0, X9, X8

0x42019c BL	4a2570

0x4201a0 STR	X0, [SP, #96]

0x4201a4 ADRP	X0,

0x4201a8 ADD	X0, X0, #416

0x4201ac ADRP	X2, 4201ac

0x4201b0 ADD	X2, X2, #3200

0x4201b4 SUB	X3, X29, #40

0x4201b8 SUB	X4, X29, #56

0x4201bc ADD	X5, SP, #96

0x4201c0 SUB	X6, X29, #48

0x4201c4 MOVZ	W1, #4

0x4201c8 BL	40f670

0x4201cc ADRP	X0,

0x4201d0 ADD	X0, X0, #488

0x4201d4 ADRP	X2, 4201d4

0x4201d8 ADD	X2, X2, #3552

0x4201dc SUB	X3, X29, #64

0x4201e0 SUB	X4, X29, #88

0x4201e4 SUB	X5, X29, #56

0x4201e8 ADD	X6, SP, #96

0x4201ec MOVZ	W1, #4

0x4201f0 BL	40f670

0x4201f4 LDR	X8, [SP, #112]

0x4201f8 CMP	X8, #2

0x4201fc B.LT	420220

0x420200 LDUR	X8, [X29, #424]

0x420204 LDUR	X9, [X29, #456]

0x420208 ORR	X1, XZR, X22

0x42020c ORR	X3, XZR, X24

0x420210 MOVZ	W0, #2

0x420214 ADD	X2, X8, X9,LSL #3

0x420218 BL	47cbc0

0x42021c ORR	X20, XZR, X0

0x420220 ADRP	X0,

0x420224 ADD	X0, X0, #560

0x420228 ADRP	X2, 420228

0x42022c ADD	X2, X2, #3856

0x420230 SUB	X3, X29, #8

0x420234 SUB	X4, X29, #56

0x420238 ADD	X5, SP, #96

0x42023c SUB	X6, X29, #32

0x420240 MOVZ	W1, #4

0x420244 BL	40f670

0x420248 ADRP	X0,

0x42024c ADD	X0, X0, #632

0x420250 ADRP	X2, 421250

0x420254 ADD	X2, X2, #64

0x420258 SUB	X3, X29, #56

0x42025c SUB	X4, X29, #88

0x420260 ADD	X5, SP, #96

0x420264 MOVZ	W1, #3

0x420268 BL	40f670

0x42026c LDR	X0, [SP, #96]

0x420270 BL	4a2670

0x420274 LDR	X8, [SP, #112]

0x420278 STR	XZR, [SP, #96]

0x42027c CMP	X8, #1

0x420280 B.LE	42028c

0x420284 ORR	X0, XZR, X20

0x420288 BL	47cfa0

0x42028c LDR	X20, [SP, #64]

0x420290 CMP	X21, #1

0x420294 B.LT	4203c4

0x420298 LDR	X9, [X22, #24]

0x42029c LDUR	X10, [X29, #424]

0x4202a0 ORR	X14, XZR, XZR

0x4202a4 ORR	X8, XZR, XZR

0x4202a8 ADD	X11, X24, #16

0x4202ac LDR	X12, [X9]

0x4202b0 B	4202d0

0x4202b4 HINT	#0

0x4202b8 HINT	#0

0x4202bc HINT	#0

(420) 0x4202c0 ORR	X13, XZR, X14

  (421) 0x4202c4 ORR	X14, XZR, X13

  (421) 0x4202c8 CMP	X8, X21

  (421) 0x4202cc B.EQ	4203c4

  (421) 0x4202d0 ADD	X8, X8, #1

  (421) 0x4202d4 ORR	X15, XZR, X12

  (421) 0x4202d8 LDR	X12, [X9, X8,LSL #3]

  (421) 0x4202dc CMP	X12, X15

  (421) 0x4202e0 B.LE	4202c0

  (421) 0x4202e4 LDR	X16, [X22, #32]

  (421) 0x4202e8 ADD	X13, X14, X12

  (421) 0x4202ec SUB	W17, W12, W15

  (421) 0x4202f0 ANDS	X0, X17, #4160

  (421) 0x4202f4 SUB	X13, X13, X15

  (421) 0x4202f8 ORR	X17, XZR, X14

  (421) 0x4202fc ORR	X18, XZR, X15

  (421) 0x420300 B.EQ	420330

  (421) 0x420304 ORR	X17, XZR, X14

  (421) 0x420308 ORR	X18, XZR, X15

    (423) 0x42030c LDR	X1, [X16, X18,LSL #3]

    (423) 0x420310 LDR	D0, [X24, X17,LSL #3]

    (423) 0x420314 ADD	X17, X17, #1

    (423) 0x420318 ADD	X18, X18, #1

    (423) 0x42031c SUBS	X0, X0, #1

    (423) 0x420320 LDR	D1, [X10, X1,LSL #3]

    (423) 0x420324 FADD	D0, D0, D1

    (423) 0x420328 STR	D0, [X10, X1,LSL #3]

    (423) 0x42032c B.NE	42030c

  (421) 0x420330 ORN	X0, XZR, X15

  (421) 0x420334 ADD	X0, X12, X0

  (421) 0x420338 CMP	X0, #3

  (421) 0x42033c B.CC	4202c4

  (421) 0x420340 ADD	X14, X14, X12

  (421) 0x420344 ADD	X16, X16, X18,LSL #3

  (421) 0x420348 ADD	X16, X16, #16

  (421) 0x42034c SUB	X14, X14, X17

  (421) 0x420350 SUB	X14, X14, X15

  (421) 0x420354 ADD	X15, X11, X17,LSL #3

  (421) 0x420358 HINT	#0

  (421) 0x42035c HINT	#0

    (422) 0x420360 LDUR	X17, [X16, #496]

    (422) 0x420364 LDUR	D0, [X15, #496]

    (422) 0x420368 SUBS	X14, X14, #4

    (422) 0x42036c LDR	D1, [X10, X17,LSL #3]

    (422) 0x420370 FADD	D0, D0, D1

    (422) 0x420374 STR	D0, [X10, X17,LSL #3]

    (422) 0x420378 LDUR	X17, [X16, #504]

    (422) 0x42037c LDUR	D0, [X15, #504]

    (422) 0x420380 LDR	D1, [X10, X17,LSL #3]

    (422) 0x420384 FADD	D0, D0, D1

    (422) 0x420388 STR	D0, [X10, X17,LSL #3]

    (422) 0x42038c LDR	X17, [X16]

    (422) 0x420390 LDR	D0, [X15]

    (422) 0x420394 LDR	D1, [X10, X17,LSL #3]

    (422) 0x420398 FADD	D0, D0, D1

    (422) 0x42039c STR	D0, [X10, X17,LSL #3]

    (422) 0x4203a0 LDR	X17, [X16, #8]

    (422) 0x4203a4 LDR	D0, [X15, #8]

    (422) 0x4203a8 ADD	X16, X16, #32

    (422) 0x4203ac ADD	X15, X15, #32

    (422) 0x4203b0 LDR	D1, [X10, X17,LSL #3]

    (422) 0x4203b4 FADD	D0, D0, D1

    (422) 0x4203b8 STR	D0, [X10, X17,LSL #3]

    (422) 0x4203bc B.NE	420360

  (421) 0x4203c0 B	4202c4

0x4203c4 LDUR	X8, [X29, #448]

0x4203c8 CMP	X8, #1

0x4203cc B.LT	420430

0x4203d0 LDUR	X9, [X29, #456]

0x4203d4 LDUR	X10, [X29, #424]

0x4203d8 ADD	X8, X8, X9

0x4203dc ADD	X0, X10, X9,LSL #3

0x4203e0 ADD	X10, X9, #1

0x4203e4 CMP	X8, X10

0x4203e8 CSINC	X8, X8, X9, #12

0x4203ec SUB	X8, X8, X9

0x4203f0 UBFM	X2, X8, #61, #60

0x4203f4 RDVL	X8, #1

0x4203f8 CMP	X8, #17

0x4203fc B.CS	42040c

0x420400 ORR	W1, WZR, WZR

0x420404 BL	40f7d0

0x420408 B	420430

0x42040c WHILELO	P0.B, XZR, X2

0x420410 ORR	X8, XZR, XZR

0x420414 DUP	Z0.B, #0

0x420418 HINT	#0

0x42041c HINT	#0

(419) 0x420420 ST1B	{Z0.B}, P0, [X0, X8]

(419) 0x420424 INCP	X8, P0.B

(419) 0x420428 WHILELO	P0.B, X8, X2

(419) 0x42042c B.MI	420420

0x420430 CMP	X20, #4

0x420434 B.EQ	420440

0x420438 CMP	X20, #2

0x42043c B.NE	420498

0x420440 LDUR	X1, [X29, #424]

0x420444 ORR	X0, XZR, X19

0x420448 MOVZ	W2, #1

0x42044c BL	426080

0x420450 LDUR	X0, [X29, #448]

0x420454 CBZ	X0, 4204b0

0x420458 MOVZ	W1, #8

0x42045c BL	4a2570

0x420460 LDUR	X8, [X29, #448]

0x420464 STUR	X0, [X29, #408]

0x420468 CMP	X8, #1

0x42046c B.LT	4204b8

0x420470 ORR	X9, XZR, XZR

0x420474 HINT	#0

0x420478 HINT	#0

0x42047c HINT	#0

(418) 0x420480 STR	X9, [X0, X9,LSL #3]

(418) 0x420484 ADD	X9, X9, #1

(418) 0x420488 LDUR	X8, [X29, #448]

(418) 0x42048c CMP	X9, X8

(418) 0x420490 B.LT	420480

0x420494 B	4204b8

0x420498 LDUR	X1, [X29, #424]

0x42049c ORR	X0, XZR, X19

0x4204a0 ORR	X2, XZR, XZR

0x4204a4 BL	426080

0x4204a8 LDUR	X0, [X29, #448]

0x4204ac CBNZ	X0, 420458

0x4204b0 ORR	X8, XZR, XZR

0x4204b4 STUR	XZR, [X29, #408]

0x4204b8 LDUR	X0, [X29, #456]

0x4204bc MOVZ	W1, #8

0x4204c0 STUR	X8, [X29, #392]

0x4204c4 BL	4a2570

0x4204c8 CMP	X20, #1

0x4204cc STUR	X0, [X29, #416]

0x4204d0 B.NE	420580

0x4204d4 LDUR	X8, [X29, #456]

0x4204d8 LDR	X9, [X28]

0x4204dc CMP	X8, #1

0x4204e0 STUR	X9, [X29, #440]

0x4204e4 B.LT	42062c

0x4204e8 LDUR	X11, [X29, #472]

0x4204ec LDUR	X12, [X29, #424]

0x4204f0 LDUR	X13, [X29, #504]

0x4204f4 ORR	X8, XZR, XZR

0x4204f8 ORR	X10, XZR, XZR

0x4204fc FMOV	D0, #1.0000000

0x420500 MOVN	X14, #0

0x420504 B	42051c

(417) 0x420508 STR	XZR, [X12, X10,LSL #3]

(417) 0x42050c LDUR	X15, [X29, #456]

(417) 0x420510 ADD	X10, X10, #1

(417) 0x420514 CMP	X10, X15

(417) 0x420518 B.GE	420630

(417) 0x42051c ADD	X15, X11, X10,LSL #3

(417) 0x420520 LDP	X15, X16, [X15]

(417) 0x420524 CMP	X16, X15

(417) 0x420528 B.GT	420568

(417) 0x42052c LDR	X15, [X9, X10,LSL #3]

(417) 0x420530 CMN	X15, #3

(417) 0x420534 B.EQ	420508

(417) 0x420538 CMN	X15, #2

(417) 0x42053c B.EQ	42054c

(417) 0x420540 CMN	X15, #1

(417) 0x420544 B.EQ	420568

(417) 0x420548 B	42056c

(417) 0x42054c LDR	D1, [X12, X10,LSL #3]

(417) 0x420550 FCMP	D1, D0

(417) 0x420554 B.GE	420568

(417) 0x420558 ADD	X15, X13, X10,LSL #3

(417) 0x42055c LDP	X15, X16, [X15]

(417) 0x420560 CMP	X16, X15

(417) 0x420564 B.LE	420578

(417) 0x420568 STR	XZR, [X9, X10,LSL #3]

(417) 0x42056c STR	X10, [X0, X8,LSL #3]

(417) 0x420570 ADD	X8, X8, #1

(417) 0x420574 B	42050c

(417) 0x420578 STR	X14, [X9, X10,LSL #3]

(417) 0x42057c B	42050c

0x420580 LDUR	X0, [X29, #456]

0x420584 MOVZ	W1, #8

0x420588 BL	4a2570

0x42058c LDUR	X8, [X29, #456]

0x420590 STUR	X0, [X29, #440]

0x420594 CMP	X8, #1

0x420598 B.LT	420680

0x42059c SUB	X10, X20, #3

0x4205a0 ORR	X8, XZR, XZR

0x4205a4 ORR	X9, XZR, XZR

0x4205a8 CMP	X10, #2

0x4205ac MOVN	X10, #2

0x4205b0 CSINC	X10, X10, XZR, #2

0x4205b4 B	4205dc

0x4205b8 HINT	#0

0x4205bc HINT	#0

(415) 0x4205c0 LDUR	X11, [X29, #416]

(415) 0x4205c4 STR	X9, [X11, X8,LSL #3]

(415) 0x4205c8 ADD	X8, X8, #1

(415) 0x4205cc LDUR	X11, [X29, #456]

(415) 0x4205d0 ADD	X9, X9, #1

(415) 0x4205d4 CMP	X9, X11

(415) 0x4205d8 B.GE	420630

  (416) 0x4205dc UBFM	X11, X9, #61, #60

  (416) 0x4205e0 STR	XZR, [X0, X11]

  (416) 0x4205e4 LDUR	X12, [X29, #504]

  (416) 0x4205e8 ADD	X11, X12, X11

  (416) 0x4205ec LDP	X11, X12, [X11]

  (416) 0x4205f0 CMP	X12, X11

  (416) 0x4205f4 B.NE	4205c0

  (416) 0x4205f8 LDUR	X11, [X29, #472]

  (416) 0x4205fc ADD	X11, X11, X9,LSL #3

  (416) 0x420600 LDP	X11, X12, [X11]

  (416) 0x420604 CMP	X12, X11

  (416) 0x420608 B.NE	4205c0

  (416) 0x42060c STR	X10, [X0, X9,LSL #3]

  (416) 0x420610 LDUR	X11, [X29, #424]

  (416) 0x420614 STR	XZR, [X11, X9,LSL #3]

  (416) 0x420618 LDUR	X11, [X29, #456]

  (416) 0x42061c ADD	X9, X9, #1

  (416) 0x420620 CMP	X9, X11

  (416) 0x420624 B.LT	4205dc

0x420628 B	420630

0x42062c ORR	X8, XZR, XZR

0x420630 LDUR	X0, [X29, #448]

0x420634 STUR	X8, [X29, #400]

0x420638 CBZ	X0, 420690

0x42063c MOVZ	W1, #8

0x420640 BL	4a2570

0x420644 LDUR	X8, [X29, #448]

0x420648 STUR	X0, [X29, #432]

0x42064c CMP	X8, #1

0x420650 B.LT	420674

0x420654 ORR	X8, XZR, XZR

0x420658 HINT	#0

0x42065c HINT	#0

(414) 0x420660 STR	XZR, [X0, X8,LSL #3]

(414) 0x420664 ADD	X8, X8, #1

(414) 0x420668 LDUR	X9, [X29, #448]

(414) 0x42066c CMP	X8, X9

(414) 0x420670 B.LT	420660

0x420674 CMP	X21, #1

0x420678 B.GE	42069c

0x42067c B	4207a4

0x420680 ORR	X8, XZR, XZR

0x420684 LDUR	X0, [X29, #448]

0x420688 STUR	XZR, [X29, #400]

0x42068c CBNZ	X0, 42063c

0x420690 STUR	XZR, [X29, #432]

0x420694 CMP	X21, #1

0x420698 B.LT	4207a4

0x42069c LDR	X9, [X22, #24]

0x4206a0 LDUR	X10, [X29, #424]

0x4206a4 ORR	X14, XZR, XZR

0x4206a8 ORR	X8, XZR, XZR

0x4206ac ADD	X11, X24, #16

0x4206b0 LDR	X12, [X9]

0x4206b4 B	4206d0

0x4206b8 HINT	#0

0x4206bc HINT	#0

(410) 0x4206c0 ORR	X13, XZR, X14

  (411) 0x4206c4 ORR	X14, XZR, X13

  (411) 0x4206c8 CMP	X8, X21

  (411) 0x4206cc B.EQ	4207a4

  (411) 0x4206d0 ADD	X8, X8, #1

  (411) 0x4206d4 ORR	X15, XZR, X12

  (411) 0x4206d8 LDR	X12, [X9, X8,LSL #3]

  (411) 0x4206dc CMP	X12, X15

  (411) 0x4206e0 B.LE	4206c0

  (411) 0x4206e4 LDR	X16, [X22, #32]

  (411) 0x4206e8 ADD	X13, X14, X12

  (411) 0x4206ec SUB	W17, W12, W15

  (411) 0x4206f0 ANDS	X0, X17, #4160

  (411) 0x4206f4 SUB	X13, X13, X15

  (411) 0x4206f8 ORR	X17, XZR, X14

  (411) 0x4206fc ORR	X18, XZR, X15

  (411) 0x420700 B.EQ	420728

  (411) 0x420704 ORR	X17, XZR, X14

  (411) 0x420708 ORR	X18, XZR, X15

    (413) 0x42070c LDR	X1, [X16, X18,LSL #3]

    (413) 0x420710 ADD	X18, X18, #1

    (413) 0x420714 SUBS	X0, X0, #1

    (413) 0x420718 LDR	D0, [X10, X1,LSL #3]

    (413) 0x42071c STR	D0, [X24, X17,LSL #3]

    (413) 0x420720 ADD	X17, X17, #1

    (413) 0x420724 B.NE	42070c

  (411) 0x420728 ORN	X0, XZR, X15

  (411) 0x42072c ADD	X0, X12, X0

  (411) 0x420730 CMP	X0, #3

  (411) 0x420734 B.CC	4206c4

  (411) 0x420738 ADD	X14, X14, X12

  (411) 0x42073c ADD	X16, X16, X18,LSL #3

  (411) 0x420740 ADD	X16, X16, #16

  (411) 0x420744 SUB	X14, X14, X17

  (411) 0x420748 SUB	X14, X14, X15

  (411) 0x42074c ADD	X15, X11, X17,LSL #3

  (411) 0x420750 HINT	#0

  (411) 0x420754 HINT	#0

  (411) 0x420758 HINT	#0

  (411) 0x42075c HINT	#0

    (412) 0x420760 LDUR	X17, [X16, #496]

    (412) 0x420764 SUBS	X14, X14, #4

    (412) 0x420768 LDR	D0, [X10, X17,LSL #3]

    (412) 0x42076c STUR	D0, [X15, #496]

    (412) 0x420770 LDUR	X17, [X16, #504]

    (412) 0x420774 LDR	D0, [X10, X17,LSL #3]

    (412) 0x420778 STUR	D0, [X15, #504]

    (412) 0x42077c LDR	X17, [X16]

    (412) 0x420780 LDR	D0, [X10, X17,LSL #3]

    (412) 0x420784 STR	D0, [X15]

    (412) 0x420788 LDR	X17, [X16, #8]

    (412) 0x42078c ADD	X16, X16, #32

    (412) 0x420790 LDR	D0, [X10, X17,LSL #3]

    (412) 0x420794 STR	D0, [X15, #8]

    (412) 0x420798 ADD	X15, X15, #32

    (412) 0x42079c B.NE	420760

  (411) 0x4207a0 B	4206c4

0x4207a4 LDR	X8, [SP, #112]

0x4207a8 CMP	X8, #1

0x4207ac B.LE	4207d0

0x4207b0 LDUR	X8, [X29, #424]

0x4207b4 LDUR	X9, [X29, #456]

0x4207b8 ORR	X1, XZR, X22

0x4207bc ORR	X2, XZR, X24

0x4207c0 MOVZ	W0, #1

0x4207c4 ADD	X3, X8, X9,LSL #3

0x4207c8 BL	47cbc0

0x4207cc BL	47cfa0

0x4207d0 CMP	X25, #3

0x4207d4 B.NE	4207f0

0x4207d8 BL	4a47b0

0x4207dc LDR	X1, [SP, #120]

0x4207e0 FSUB	D0, D0, S8

0x4207e4 ADRP	X0,

0x4207e8 ADD	X0, X0, #3832

0x4207ec BL	4a2780

0x4207f0 LDUR	X0, [X29, #456]

0x4207f4 MOVZ	W1, #8

0x4207f8 STR	X28, [SP, #56]

0x4207fc BL	4a2570

0x420800 STP	XZR, X0, [SP, #80]

0x420804 LDUR	X0, [X29, #448]

0x420808 CBZ	X0, 420818

0x42080c MOVZ	W1, #8

0x420810 BL	4a2570

0x420814 STR	X0, [SP, #80]

0x420818 ADRP	X3,

0x42081c ADRP	X4,

0x420820 SUB	X0, X29, #112

0x420824 ADD	X1, SP, #128

0x420828 LDR	X3, [X3, #4000]

0x42082c LDR	X4, [X4, #4032]

0x420830 LDR	X5, [SP, #72]

0x420834 MOVZ	W2, #1

0x420838 BL	4a43b0

0x42083c LDR	X8, [SP, #128]

0x420840 CBZ	X8, 420be4

0x420844 ORR	X26, XZR, XZR

0x420848 AND	X27, X21, #8127

0x42084c SUB	X28, X29, #56

0x420850 SUB	X19, X29, #80

0x420854 SUB	X25, X29, #48

0x420858 SUB	X20, X29, #40

0x42085c B	42090c

    (402) 0x420860 ADD	X26, X26, #1

    (402) 0x420864 BL	4a46e0

    (402) 0x420868 UBFM	X8, X0, #60, #59

    (402) 0x42086c ADD	X0, X8, #16

    (402) 0x420870 BL	4a2500

    (402) 0x420874 ADD	X8, SP, #80

    (402) 0x420878 STR	X0, [SP, #104]

    (402) 0x42087c SUB	X3, X29, #112

    (402) 0x420880 SUB	X4, X29, #120

    (402) 0x420884 SUB	X5, X29, #96

    (402) 0x420888 STR	X8, [SP, #40]

    (402) 0x42088c ADD	X8, SP, #88

    (402) 0x420890 SUB	X6, X29, #72

    (402) 0x420894 SUB	X7, X29, #88

    (402) 0x420898 ADRP	X0,

    (402) 0x42089c ADD	X0, X0, #944

    (402) 0x4208a0 STR	X8, [SP, #32]

    (402) 0x4208a4 ADD	X8, SP, #104

    (402) 0x4208a8 MOVZ	W1, #11

    (402) 0x4208ac ADRP	X2, 4218ac

    (402) 0x4208b0 ADD	X2, X2, #1840

    (402) 0x4208b4 STP	X28, X8, [SP, #16]

    (402) 0x4208b8 SUB	X8, X29, #104

    (402) 0x4208bc STP	X8, X19, [SP]

    (402) 0x4208c0 BL	40f670

    (402) 0x4208c4 LDP	X8, X11, [X29, #920]

    (402) 0x4208c8 LDP	X9, X10, [SP, #80]

    (402) 0x4208cc LDR	X0, [SP, #104]

    (402) 0x4208d0 STP	X9, X10, [X29, #920]

    (402) 0x4208d4 STP	X8, X11, [SP, #80]

    (402) 0x4208d8 BL	4a2670

    (402) 0x4208dc STR	XZR, [SP, #104]

    (402) 0x4208e0 ADRP	X3,

    (402) 0x4208e4 ADRP	X4,

    (402) 0x4208e8 SUB	X0, X29, #112

    (402) 0x4208ec ADD	X1, SP, #128

    (402) 0x4208f0 LDR	X3, [X3, #4000]

    (402) 0x4208f4 LDR	X4, [X4, #4032]

    (402) 0x4208f8 LDR	X5, [SP, #72]

    (402) 0x4208fc MOVZ	W2, #1

    (402) 0x420900 BL	4a43b0

    (402) 0x420904 LDR	X8, [SP, #128]

    (402) 0x420908 CBZ	X8, 420be4

    (402) 0x42090c LDR	X8, [SP, #64]

    (402) 0x420910 CBZ	X8, 420918

    (402) 0x420914 CBZ	X26, 420a90

    (402) 0x420918 SUB	X3, X29, #112

    (402) 0x42091c SUB	X4, X29, #96

    (402) 0x420920 SUB	X5, X29, #88

    (402) 0x420924 SUB	X6, X29, #72

    (402) 0x420928 ADRP	X0,

    (402) 0x42092c ADD	X0, X0, #704

    (402) 0x420930 MOVZ	W1, #4

    (402) 0x420934 ADRP	X2, 421934

    (402) 0x420938 ADD	X2, X2, #336

    (402) 0x42093c BL	40f670

    (402) 0x420940 SUB	X3, X29, #120

    (402) 0x420944 SUB	X4, X29, #104

    (402) 0x420948 SUB	X5, X29, #88

    (402) 0x42094c SUB	X6, X29, #56

    (402) 0x420950 SUB	X7, X29, #80

    (402) 0x420954 ADRP	X0,

    (402) 0x420958 ADD	X0, X0, #776

    (402) 0x42095c MOVZ	W1, #5

    (402) 0x420960 ADRP	X2, 421960

    (402) 0x420964 ADD	X2, X2, #704

    (402) 0x420968 BL	40f670

    (402) 0x42096c SUB	X3, X29, #112

    (402) 0x420970 SUB	X4, X29, #96

    (402) 0x420974 SUB	X5, X29, #88

    (402) 0x420978 SUB	X6, X29, #8

    (402) 0x42097c STP	X28, X19, [SP, #24]

    (402) 0x420980 STP	X20, X25, [SP, #8]

    (402) 0x420984 SUB	X7, X29, #32

    (402) 0x420988 SUB	X8, X29, #72

    (402) 0x42098c ADRP	X0,

    (402) 0x420990 ADD	X0, X0, #848

    (402) 0x420994 STR	X8, [SP]

    (402) 0x420998 MOVZ	W1, #10

    (402) 0x42099c ADRP	X2, 42199c

    (402) 0x4209a0 ADD	X2, X2, #960

    (402) 0x4209a4 BL	40f670

    (402) 0x4209a8 LDR	X8, [SP, #112]

    (402) 0x4209ac CMP	X8, #1

    (402) 0x4209b0 B.LE	4209cc

    (402) 0x4209b4 LDUR	X2, [X29, #432]

    (402) 0x4209b8 ORR	X1, XZR, X22

    (402) 0x4209bc ORR	X3, XZR, X23

    (402) 0x4209c0 MOVZ	W0, #12

    (402) 0x4209c4 BL	47cbc0

    (402) 0x4209c8 BL	47cfa0

    (402) 0x4209cc CMP	X21, #1

    (402) 0x4209d0 B.LT	420a6c

    (402) 0x4209d4 LDR	X10, [X22, #24]

    (402) 0x4209d8 ORR	X8, XZR, XZR

    (402) 0x4209dc ORR	X9, XZR, XZR

    (402) 0x4209e0 LDR	X11, [X10]

    (402) 0x4209e4 B	4209f4

      (407) 0x4209e8 ORR	X11, XZR, X14

      (407) 0x4209ec CMP	X9, X21

      (407) 0x4209f0 B.EQ	420a6c

      (407) 0x4209f4 ADD	X9, X9, #1

      (407) 0x4209f8 LDR	X14, [X10, X9,LSL #3]

      (407) 0x4209fc CMP	X11, X14

      (407) 0x420a00 B.GE	4209e8

      (407) 0x420a04 LDR	X12, [X22, #32]

      (407) 0x420a08 LDUR	X13, [X29, #440]

      (407) 0x420a0c B	420a38

0x420a10 HINT	#0

0x420a14 HINT	#0

0x420a18 HINT	#0

0x420a1c HINT	#0

        (408) 0x420a20 STR	X15, [X23, X8,LSL #3]

        (408) 0x420a24 LDR	X14, [X10, X9,LSL #3]

        (408) 0x420a28 ADD	X11, X11, #1

        (408) 0x420a2c ADD	X8, X8, #1

        (408) 0x420a30 CMP	X11, X14

        (408) 0x420a34 B.GE	4209e8

        (408) 0x420a38 LDR	X14, [X12, X11,LSL #3]

        (408) 0x420a3c LDR	X16, [X23, X8,LSL #3]

        (408) 0x420a40 LDR	X15, [X13, X14,LSL #3]

        (408) 0x420a44 CMP	X16, #0

        (408) 0x420a48 CCMP	X15, #1, #8, #0

        (408) 0x420a4c B.LT	420a20

        (408) 0x420a50 STR	XZR, [X13, X14,LSL #3]

        (408) 0x420a54 LDR	X14, [X10, X9,LSL #3]

        (408) 0x420a58 ADD	X11, X11, #1

        (408) 0x420a5c ADD	X8, X8, #1

        (408) 0x420a60 CMP	X11, X14

        (408) 0x420a64 B.LT	420a38

      (407) 0x420a68 B	4209e8

    (402) 0x420a6c LDR	X8, [SP, #112]

    (402) 0x420a70 CMP	X8, #1

    (402) 0x420a74 B.LE	420a90

    (402) 0x420a78 LDUR	X3, [X29, #432]

    (402) 0x420a7c ORR	X1, XZR, X22

    (402) 0x420a80 ORR	X2, XZR, X23

    (402) 0x420a84 MOVZ	W0, #11

    (402) 0x420a88 BL	47cbc0

    (402) 0x420a8c BL	47cfa0

    (402) 0x420a90 SUB	X3, X29, #112

    (402) 0x420a94 SUB	X4, X29, #96

    (402) 0x420a98 SUB	X5, X29, #88

    (402) 0x420a9c SUB	X6, X29, #72

    (402) 0x420aa0 STP	X25, X19, [SP, #16]

    (402) 0x420aa4 SUB	X7, X29, #8

    (402) 0x420aa8 SUB	X8, X29, #32

    (402) 0x420aac STP	X8, X20, [SP]

    (402) 0x420ab0 ADRP	X0,

    (402) 0x420ab4 ADD	X0, X0, #920

    (402) 0x420ab8 MOVZ	W1, #9

    (402) 0x420abc ADRP	X2, 421abc

    (402) 0x420ac0 ADD	X2, X2, #1424

    (402) 0x420ac4 BL	40f670

    (402) 0x420ac8 CMP	X21, #1

    (402) 0x420acc B.LT	420b24

  (406) 0x420ad0 LDR	X8, [X22, #24]

  (406) 0x420ad4 LDUR	X9, [X29, #440]

  (406) 0x420ad8 CMP	X21, #1

  (406) 0x420adc LDR	X10, [X8]

  (406) 0x420ae0 B.NE	420b4c

  (406) 0x420ae4 ORR	X11, XZR, XZR

  (406) 0x420ae8 ORR	X12, XZR, XZR

  (406) 0x420aec TBZ	W21, #0, 420b24

  (406) 0x420af0 ADD	X12, X12, #1

  (406) 0x420af4 LDR	X13, [X8, X12,LSL #3]

  (406) 0x420af8 CMP	X10, X13

  (406) 0x420afc B.GE	420b24

  (406) 0x420b00 LDR	X13, [X22, #32]

  (406) 0x420b04 ADD	X11, X23, X11,LSL #3

    (409) 0x420b08 LDR	X14, [X13, X10,LSL #3]

    (409) 0x420b0c ADD	X10, X10, #1

    (409) 0x420b10 LDR	X14, [X9, X14,LSL #3]

    (409) 0x420b14 STR	X14, [X11], #8

    (409) 0x420b18 LDR	X14, [X8, X12,LSL #3]

    (409) 0x420b1c CMP	X10, X14

    (409) 0x420b20 B.LT	420b08

    (402) 0x420b24 LDR	X8, [SP, #112]

    (402) 0x420b28 CMP	X8, #1

    (402) 0x420b2c B.LE	420860

    (402) 0x420b30 LDUR	X3, [X29, #432]

    (402) 0x420b34 ORR	X1, XZR, X22

    (402) 0x420b38 ORR	X2, XZR, X23

    (402) 0x420b3c MOVZ	W0, #11

    (402) 0x420b40 BL	47cbc0

    (402) 0x420b44 BL	47cfa0

    (402) 0x420b48 B	420860

(403) 0x420b4c ORR	X11, XZR, XZR

(403) 0x420b50 ORR	X12, XZR, XZR

(403) 0x420b54 B	420b68

0x420b58 HINT	#0

0x420b5c HINT	#0

(403) 0x420b60 CMP	X12, X27

(403) 0x420b64 B.EQ	420aec

(403) 0x420b68 ORR	X14, X12, #4096

(403) 0x420b6c LDR	X13, [X8, X14,LSL #3]

(403) 0x420b70 CMP	X10, X13

(403) 0x420b74 B.GE	420ba0

(403) 0x420b78 LDR	X15, [X22, #32]

(403) 0x420b7c HINT	#0

  (405) 0x420b80 LDR	X13, [X15, X10,LSL #3]

  (405) 0x420b84 ADD	X10, X10, #1

  (405) 0x420b88 LDR	X13, [X9, X13,LSL #3]

  (405) 0x420b8c STR	X13, [X23, X11,LSL #3]

  (405) 0x420b90 ADD	X11, X11, #1

  (405) 0x420b94 LDR	X13, [X8, X14,LSL #3]

  (405) 0x420b98 CMP	X10, X13

  (405) 0x420b9c B.LT	420b80

(403) 0x420ba0 ADD	X12, X12, #2

(403) 0x420ba4 LDR	X10, [X8, X12,LSL #3]

(403) 0x420ba8 CMP	X13, X10

(403) 0x420bac B.GE	420b60

(403) 0x420bb0 LDR	X14, [X22, #32]

(403) 0x420bb4 HINT	#0

(403) 0x420bb8 HINT	#0

(403) 0x420bbc HINT	#0

  (404) 0x420bc0 LDR	X10, [X14, X13,LSL #3]

  (404) 0x420bc4 ADD	X13, X13, #1

  (404) 0x420bc8 LDR	X10, [X9, X10,LSL #3]

  (404) 0x420bcc STR	X10, [X23, X11,LSL #3]

  (404) 0x420bd0 ADD	X11, X11, #1

  (404) 0x420bd4 LDR	X10, [X8, X12,LSL #3]

  (404) 0x420bd8 CMP	X13, X10

  (404) 0x420bdc B.LT	420bc0

(403) 0x420be0 B	420b60

0x420be4 LDUR	X0, [X29, #424]

0x420be8 BL	4a2670

0x420bec LDUR	X0, [X29, #416]

0x420bf0 STUR	XZR, [X29, #424]

0x420bf4 BL	4a2670

0x420bf8 LDR	X0, [SP, #88]

0x420bfc STUR	XZR, [X29, #416]

0x420c00 BL	4a2670

0x420c04 LDR	X0, [SP, #80]

0x420c08 STR	XZR, [SP, #88]

0x420c0c BL	4a2670

0x420c10 LDUR	X8, [X29, #448]

0x420c14 STR	XZR, [SP, #80]

0x420c18 CBZ	X8, 420c28

0x420c1c LDUR	X0, [X29, #408]

0x420c20 BL	4a2670

0x420c24 STUR	XZR, [X29, #408]

0x420c28 ORR	X0, XZR, X24

0x420c2c BL	4a2670

0x420c30 ORR	X0, XZR, X23

0x420c34 BL	4a2670

0x420c38 LDUR	X0, [X29, #432]

0x420c3c BL	4a2670

0x420c40 LDUR	X8, [X29, #440]

0x420c44 LDR	X9, [SP, #56]

0x420c48 STR	X8, [X9]

0x420c4c ORR	X0, XZR, XZR

0x420c50 LDR	D8, [SP, #240]

0x420c54 LDP	X20, X19, [SP, #336]

0x420c58 LDP	X22, X21, [SP, #320]

0x420c5c LDP	X24, X23, [SP, #304]

0x420c60 LDP	X26, X25, [SP, #288]

0x420c64 LDP	X28, X27, [SP, #272]

0x420c68 LDP	X29, X30, [SP, #256]

0x420c6c ADD	SP, SP, #352

0x420c70 RET

0x420c74 HINT	#0

0x420c78 HINT	#0

0x420c7c HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	par_coarsen.c:1980-2624
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_coarsen.c:1980-1997,2058-2086,2100-2106,2113,2126-2132,2139,2145,2154-2170,2176-2179,2186-2205,2211-2212,2219-2223,2230-2255,2262-2291,2305-2307,2320,2327,2338,2354,2393-2425,2435,2492-2505,2513-2516,2581-2583,2589,2608-2618,2624.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 44.00 to 5.00 cycles (8.80x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 21% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 44.00 to 4.41 cycles (9.99x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 44.00 to 18.50 cycles (2.38x speedup).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary function is loading 680 bytes. The binary function is storing 368 bytes.

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	353
loop length	1412
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

41.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	37.00	37.00	44.00	44.00	44.00	44.00	1.25	1.25	1.25	1.25	37.83	37.50	37.67	18.00	18.00
cycles	37.00	37.00	44.00	44.00	44.00	44.00	1.25	1.25	1.25	1.25	37.83	37.50	37.67	18.00	18.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	41.25
Overall L1	44.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 44.00 cycles. At this rate:

16% of peak load performance is reached (15.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (8.36 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 420090

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #352	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D8, [SP, #240]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X26, X27, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X22, [X0, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X28, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X3, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STP X2, X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X9, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP XZR, X8, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.NE 420100 <hypre_BoomerAMGCoarsenPMIS+0x70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 4a47b0 <time_getWallclockSeconds>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMOV D8, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR X21, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a3b70 <hypre_MPI_Comm_size>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, SP, #120	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a3ba0 <hypre_MPI_Comm_rank>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBNZ X22, 420134 <hypre_BoomerAMGCoarsenPMIS+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X22, [X20, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X22, 420134 <hypre_BoomerAMGCoarsenPMIS+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 47d700 <hypre_MatvecCommPkgCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X22, [X20, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X22, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X22, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X22, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X27, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X26, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X24, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X9, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBZ X8, 42017c <hypre_BoomerAMGCoarsenPMIS+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X27, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X9, X8, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X0, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADRP X0, <4db1a4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #416	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, 4201ac <hypre_BoomerAMGCoarsenPMIS+0x11c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #3200	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f670 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X0, <4db1cc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #488	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, 4201d4 <hypre_BoomerAMGCoarsenPMIS+0x144>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #3552	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #88	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X5, X29, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f670 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 420220 <hypre_BoomerAMGCoarsenPMIS+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X1, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X3, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X8, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 47cbc0 <hypre_ParCSRCommHandleCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4db220>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #560	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, 420228 <hypre_BoomerAMGCoarsenPMIS+0x198>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #3856	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f670 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X0, <4db248>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #632	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, 421250 <.omp_outlined..15+0x100>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #88	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f670 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 42028c <hypre_BoomerAMGCoarsenPMIS+0x1fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 47cfa0 <hypre_ParCSRCommHandleDestroy>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X20, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4203c4 <hypre_BoomerAMGCoarsenPMIS+0x334>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X22, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X14, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X24, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4202d0 <hypre_BoomerAMGCoarsenPMIS+0x240>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 420430 <hypre_BoomerAMGCoarsenPMIS+0x3a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X10, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSINC X8, X8, X9, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X8, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X2, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RDVL X8, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X8, #17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 42040c <hypre_BoomerAMGCoarsenPMIS+0x37c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f7d0 <@plt_start@+0x370>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 420430 <hypre_BoomerAMGCoarsenPMIS+0x3a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
WHILELO P0.B, XZR, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z0.B, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
HINT #0
HINT #0
CMP X20, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 420440 <hypre_BoomerAMGCoarsenPMIS+0x3b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 420498 <hypre_BoomerAMGCoarsenPMIS+0x408>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X1, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 426080 <hypre_BoomerAMGIndepSetInit>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X0, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X0, 4204b0 <hypre_BoomerAMGCoarsenPMIS+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X0, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4204b8 <hypre_BoomerAMGCoarsenPMIS+0x428>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
B 4204b8 <hypre_BoomerAMGCoarsenPMIS+0x428>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X1, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 426080 <hypre_BoomerAMGIndepSetInit>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X0, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X0, 420458 <hypre_BoomerAMGCoarsenPMIS+0x3c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR XZR, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X0, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STUR X0, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.NE 420580 <hypre_BoomerAMGCoarsenPMIS+0x4f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STUR X9, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.LT 42062c <hypre_BoomerAMGCoarsenPMIS+0x59c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X11, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X12, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X13, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D0, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVN X14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42051c <hypre_BoomerAMGCoarsenPMIS+0x48c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X0, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X0, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 420680 <hypre_BoomerAMGCoarsenPMIS+0x5f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X10, X20, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MOVN X10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC X10, X10, XZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4205dc <hypre_BoomerAMGCoarsenPMIS+0x54c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
B 420630 <hypre_BoomerAMGCoarsenPMIS+0x5a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X0, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBZ X0, 420690 <hypre_BoomerAMGCoarsenPMIS+0x600>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X0, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 420674 <hypre_BoomerAMGCoarsenPMIS+0x5e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
CMP X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 42069c <hypre_BoomerAMGCoarsenPMIS+0x60c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 4207a4 <hypre_BoomerAMGCoarsenPMIS+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X0, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR XZR, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBNZ X0, 42063c <hypre_BoomerAMGCoarsenPMIS+0x5ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STUR XZR, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4207a4 <hypre_BoomerAMGCoarsenPMIS+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X22, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X14, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X24, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4206d0 <hypre_BoomerAMGCoarsenPMIS+0x640>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4207d0 <hypre_BoomerAMGCoarsenPMIS+0x740>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X1, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X8, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 47cbc0 <hypre_ParCSRCommHandleCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 47cfa0 <hypre_ParCSRCommHandleDestroy>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X25, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 4207f0 <hypre_BoomerAMGCoarsenPMIS+0x760>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 4a47b0 <time_getWallclockSeconds>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FSUB D0, D0, S8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ADRP X0, <4a77e4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3832	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2780 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X0, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X28, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP XZR, X0, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X0, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X0, 420818 <hypre_BoomerAMGCoarsenPMIS+0x788>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADRP X3, <4df818>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X4, <4df81c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X0, X29, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X3, [X3, #4000]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X4, #4032]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a43b0 <hypre_MPI_Allreduce>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X8, 420be4 <hypre_BoomerAMGCoarsenPMIS+0xb54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X26, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND X27, X21, #8127	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X28, X29, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X19, X29, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X25, X29, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X20, X29, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42090c <hypre_BoomerAMGCoarsenPMIS+0x87c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDUR X0, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X0, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR XZR, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR XZR, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBZ X8, 420c28 <hypre_BoomerAMGCoarsenPMIS+0xb98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X0, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STUR XZR, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X0, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X0, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D8, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #352	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Source file and lines	par_coarsen.c:1980-2624
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 44.00 to 5.00 cycles (8.80x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 44.00 to 18.50 cycles (2.38x speedup).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary function is loading 680 bytes. The binary function is storing 368 bytes.

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	353
loop length	1412
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

41.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	37.00	37.00	44.00	44.00	44.00	44.00	1.25	1.25	1.25	1.25	37.83	37.50	37.67	18.00	18.00
cycles	37.00	37.00	44.00	44.00	44.00	44.00	1.25	1.25	1.25	1.25	37.83	37.50	37.67	18.00	18.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	41.25
Overall L1	44.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 44.00 cycles. At this rate:

16% of peak load performance is reached (15.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (8.36 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 420090

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #352	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D8, [SP, #240]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X26, X27, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X22, [X0, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X28, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X3, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STP X2, X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X9, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP XZR, X8, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.NE 420100 <hypre_BoomerAMGCoarsenPMIS+0x70>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 4a47b0 <time_getWallclockSeconds>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMOV D8, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR X21, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a3b70 <hypre_MPI_Comm_size>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, SP, #120	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a3ba0 <hypre_MPI_Comm_rank>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBNZ X22, 420134 <hypre_BoomerAMGCoarsenPMIS+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X22, [X20, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X22, 420134 <hypre_BoomerAMGCoarsenPMIS+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 47d700 <hypre_MatvecCommPkgCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X22, [X20, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X21, [X22, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X22, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X22, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X27, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X26, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X24, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X9, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBZ X8, 42017c <hypre_BoomerAMGCoarsenPMIS+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X27, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X9, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X9, X8, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X0, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADRP X0, <4db1a4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #416	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, 4201ac <hypre_BoomerAMGCoarsenPMIS+0x11c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #3200	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f670 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X0, <4db1cc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #488	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, 4201d4 <hypre_BoomerAMGCoarsenPMIS+0x144>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #3552	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #88	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X5, X29, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f670 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 420220 <hypre_BoomerAMGCoarsenPMIS+0x190>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X1, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X3, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X8, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 47cbc0 <hypre_ParCSRCommHandleCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4db220>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #560	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, 420228 <hypre_BoomerAMGCoarsenPMIS+0x198>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #3856	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X6, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f670 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X0, <4db248>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #632	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, 421250 <.omp_outlined..15+0x100>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X3, X29, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X4, X29, #88	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f670 <@plt_start@+0x210>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 42028c <hypre_BoomerAMGCoarsenPMIS+0x1fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 47cfa0 <hypre_ParCSRCommHandleDestroy>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X20, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4203c4 <hypre_BoomerAMGCoarsenPMIS+0x334>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X22, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X14, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X24, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4202d0 <hypre_BoomerAMGCoarsenPMIS+0x240>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 420430 <hypre_BoomerAMGCoarsenPMIS+0x3a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X10, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSINC X8, X8, X9, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X8, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X2, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RDVL X8, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X8, #17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 42040c <hypre_BoomerAMGCoarsenPMIS+0x37c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f7d0 <@plt_start@+0x370>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 420430 <hypre_BoomerAMGCoarsenPMIS+0x3a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
WHILELO P0.B, XZR, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z0.B, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
HINT #0
HINT #0
CMP X20, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 420440 <hypre_BoomerAMGCoarsenPMIS+0x3b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 420498 <hypre_BoomerAMGCoarsenPMIS+0x408>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X1, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 426080 <hypre_BoomerAMGIndepSetInit>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X0, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X0, 4204b0 <hypre_BoomerAMGCoarsenPMIS+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X0, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4204b8 <hypre_BoomerAMGCoarsenPMIS+0x428>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
B 4204b8 <hypre_BoomerAMGCoarsenPMIS+0x428>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X1, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 426080 <hypre_BoomerAMGIndepSetInit>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X0, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X0, 420458 <hypre_BoomerAMGCoarsenPMIS+0x3c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR XZR, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X0, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STUR X0, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.NE 420580 <hypre_BoomerAMGCoarsenPMIS+0x4f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STUR X9, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.LT 42062c <hypre_BoomerAMGCoarsenPMIS+0x59c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X11, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X12, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X13, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D0, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVN X14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42051c <hypre_BoomerAMGCoarsenPMIS+0x48c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X0, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X0, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 420680 <hypre_BoomerAMGCoarsenPMIS+0x5f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X10, X20, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MOVN X10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC X10, X10, XZR, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4205dc <hypre_BoomerAMGCoarsenPMIS+0x54c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
B 420630 <hypre_BoomerAMGCoarsenPMIS+0x5a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X0, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBZ X0, 420690 <hypre_BoomerAMGCoarsenPMIS+0x600>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X0, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 420674 <hypre_BoomerAMGCoarsenPMIS+0x5e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
CMP X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 42069c <hypre_BoomerAMGCoarsenPMIS+0x60c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 4207a4 <hypre_BoomerAMGCoarsenPMIS+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X0, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR XZR, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBNZ X0, 42063c <hypre_BoomerAMGCoarsenPMIS+0x5ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STUR XZR, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X21, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4207a4 <hypre_BoomerAMGCoarsenPMIS+0x714>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X22, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X14, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X24, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4206d0 <hypre_BoomerAMGCoarsenPMIS+0x640>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4207d0 <hypre_BoomerAMGCoarsenPMIS+0x740>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X1, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X8, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 47cbc0 <hypre_ParCSRCommHandleCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 47cfa0 <hypre_ParCSRCommHandleDestroy>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X25, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 4207f0 <hypre_BoomerAMGCoarsenPMIS+0x760>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
BL 4a47b0 <time_getWallclockSeconds>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FSUB D0, D0, S8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
ADRP X0, <4a77e4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3832	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2780 <hypre_printf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X0, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X28, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STP XZR, X0, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X0, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X0, 420818 <hypre_BoomerAMGCoarsenPMIS+0x788>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADRP X3, <4df818>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X4, <4df81c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X0, X29, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X3, [X3, #4000]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X4, #4032]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a43b0 <hypre_MPI_Allreduce>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X8, 420be4 <hypre_BoomerAMGCoarsenPMIS+0xb54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X26, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND X27, X21, #8127	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X28, X29, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X19, X29, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X25, X29, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X20, X29, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42090c <hypre_BoomerAMGCoarsenPMIS+0x87c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDUR X0, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X0, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR XZR, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR XZR, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR XZR, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBZ X8, 420c28 <hypre_BoomerAMGCoarsenPMIS+0xb98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X0, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STUR XZR, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X0, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X0, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X0, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D8, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X20, X19, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #352	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼hypre_BoomerAMGCoarsenPMIS–	0.02	0.01
▼Loop 415 - par_coarsen.c:2232-2243 - exec–	0.01	0.19
○Loop 416 - par_coarsen.c:2232-2240 - exec	0.01	0.2
○Loop 414 - par_coarsen.c:2254-2255 - exec	0	0
▼Loop 410 - par_coarsen.c:2262-2268 - exec–	0	0
▼Loop 411 - par_coarsen.c:2262-2268 - exec–	0	0
○Loop 412 - par_coarsen.c:2265-2268 - exec	0	0
○Loop 413 - par_coarsen.c:2265-2268 - exec	0	0
○Loop 418 - par_coarsen.c:2191-2192 - exec	0	0
▼Loop 420 - par_coarsen.c:2159-2164 - exec–	0	0
▼Loop 421 - par_coarsen.c:2159-2164 - exec–	0	0
○Loop 423 - par_coarsen.c:2162-2164 - exec	0	0
○Loop 422 - par_coarsen.c:2162-2164 - exec	0	0
○Loop 417 - par_coarsen.c:2203-2223 - exec	0	0
▼Loop 403 - par_coarsen.c:2305-2589 - exec–	0	0
○Loop 404 - par_coarsen.c:2495-2497 - exec	0	0
▼Loop 406 - par_coarsen.c:2305-2589 - exec–	0	0
○Loop 409 - par_coarsen.c:2495-2497 - exec	0	0
▼Loop 402 - par_coarsen.c:2305-2589 - exec–	0	0
▼Loop 407 - par_coarsen.c:2402-2415 - exec–	0	0
○Loop 408 - par_coarsen.c:2405-2415 - exec	0	0
○Loop 405 - par_coarsen.c:2495-2497 - exec	0	0
○Loop 419 - par_coarsen.c:2170-2170 - exec	0	0

Report Configuration

Code clean check

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

Arithmetic intensity

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Front-end

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Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code