OV - exec - Function .omp_outlined..7#0x4977a0

	Function: .omp_outlined..7#0x4977a0	Module: exec	Source: csr_matop.c:380-560 [...]	Coverage: 0.38%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c: 380 - 560

--------------------------------------------------------------------------------

380:   return idx%dim1*dim2 + idx/dim1;

[...]

463: #pragma omp parallel

464: #endif

465:    {

466:    HYPRE_Int num_threads = hypre_NumActiveThreads();

467:    HYPRE_Int my_thread_num = hypre_GetThreadNum();

468:

469:    HYPRE_Int iBegin = hypre_CSRMatrixGetLoadBalancedPartitionBegin(A);

470:    HYPRE_Int iEnd = hypre_CSRMatrixGetLoadBalancedPartitionEnd(A);

471:    hypre_assert(iBegin <= iEnd);

472:    hypre_assert(iBegin >= 0 && iBegin <= num_rowsA);

473:    hypre_assert(iEnd >= 0 && iEnd <= num_rowsA);

474:

475:    HYPRE_Int i, j;

476:    memset(bucket + my_thread_num*num_colsA, 0, sizeof(HYPRE_Int)*num_colsA);

[...]

483:    for (j = A_i[iBegin]; j < A_i[iEnd]; ++j) {

484:      HYPRE_Int idx = A_j[j];

485:      bucket[my_thread_num*num_colsA + idx]++;

[...]

493: #pragma omp barrier

494: #endif

495:

496:    for (i = my_thread_num*num_colsA + 1; i < (my_thread_num + 1)*num_colsA; ++i) {

497:      HYPRE_Int transpose_i = transpose_idx(i, num_threads, num_colsA);

498:      HYPRE_Int transpose_i_minus_1 = transpose_idx(i - 1, num_threads, num_colsA);

499:

500:      bucket[transpose_i] += bucket[transpose_i_minus_1];

501:    }

502:

503: #ifdef HYPRE_USING_OPENMP

504: #pragma omp barrier

505: #pragma omp master

506: #endif

507:    {

508:      for (i = 1; i < num_threads; ++i) {

509:        HYPRE_Int j0 = num_colsA*i - 1, j1 = num_colsA*(i + 1) - 1;

510:        HYPRE_Int transpose_j0 = transpose_idx(j0, num_threads, num_colsA);

511:        HYPRE_Int transpose_j1 = transpose_idx(j1, num_threads, num_colsA);

512:

513:        bucket[transpose_j1] += bucket[transpose_j0];

514:      }

515:    }

516: #ifdef HYPRE_USING_OPENMP

517: #pragma omp barrier

518: #endif

519:

520:    if (my_thread_num > 0) {

521:      HYPRE_Int transpose_i0 = transpose_idx(num_colsA*my_thread_num - 1, num_threads, num_colsA);

522:      HYPRE_Int offset = bucket[transpose_i0];

523:

524:      for (i = my_thread_num*num_colsA; i < (my_thread_num + 1)*num_colsA - 1; ++i) {

525:        HYPRE_Int transpose_i = transpose_idx(i, num_threads, num_colsA);

526:

527:        bucket[transpose_i] += offset;

528:      }

529:    }

530:

531: #ifdef HYPRE_USING_OPENMP

532: #pragma omp barrier

[...]

539:    if (data) {

540:       for (i = iEnd - 1; i >= iBegin; --i) {

541:         for (j = A_i[i + 1] - 1; j >= A_i[i]; --j) {

542:           HYPRE_Int idx = A_j[j];

543:           --bucket[my_thread_num*num_colsA + idx];

544:

545:           HYPRE_Int offset = bucket[my_thread_num*num_colsA + idx];

546:

547:           AT_data[offset] = A_data[j];

548:           AT_j[offset] = i;

549:         }

550:       }

551:    }

552:    else {

553:       for (i = iEnd - 1; i >= iBegin; --i) {

554:         for (j = A_i[i + 1] - 1; j >= A_i[i]; --j) {

555:           HYPRE_Int idx = A_j[j];

556:           --bucket[my_thread_num*num_colsA + idx];

557:

558:           HYPRE_Int offset = bucket[my_thread_num*num_colsA + idx];

559:

560:           AT_j[offset] = i;

0x4977a0 SUB	SP, SP, #112

0x4977a4 STP	X29, X30, [SP, #16]

0x4977a8 STP	X28, X27, [SP, #32]

0x4977ac STP	X26, X25, [SP, #48]

0x4977b0 STP	X24, X23, [SP, #64]

0x4977b4 STP	X22, X21, [SP, #80]

0x4977b8 STP	X20, X19, [SP, #96]

0x4977bc ADD	X29, SP, #16

0x4977c0 ORR	X25, XZR, X7

0x4977c4 STR	X6, [SP, #8]

0x4977c8 ORR	X19, XZR, X5

0x4977cc ORR	X24, XZR, X4

0x4977d0 ORR	X28, XZR, X3

0x4977d4 ORR	X22, XZR, X2

0x4977d8 ORR	X27, XZR, X0

0x4977dc BL	4a4700

0x4977e0 ORR	X26, XZR, X0

0x4977e4 BL	4a4720

0x4977e8 ORR	X20, XZR, X0

0x4977ec LDR	X0, [X22]

0x4977f0 BL	4997d0

0x4977f4 ORR	X21, XZR, X0

0x4977f8 LDR	X0, [X22]

0x4977fc BL	499860

0x497800 ADRP	X23,

0x497804 ORR	X22, XZR, X0

0x497808 CMP	X21, X0

0x49780c LDR	X23, [X23, #3824]

0x497810 B.LE	497844

0x497814 LDR	X0, [X23]

0x497818 ADRP	X1,

0x49781c ADD	X1, X1, #675

0x497820 ADRP	X2,

0x497824 ADD	X2, X2, #3881

0x497828 BL	4a2830

0x49782c ORR	X3, XZR, XZR

0x497830 ADRP	X0,

0x497834 ADD	X0, X0, #3416

0x497838 MOVZ	W1, #471

0x49783c MOVZ	W2, #1

0x497840 BL	4a5070

0x497844 TBNZ	X21, #63, 497854

0x497848 LDR	X8, [X28]

0x49784c CMP	X21, X8

0x497850 B.LE	497888

0x497854 LDR	X0, [X23]

0x497858 ADRP	X1,

0x49785c ADD	X1, X1, #675

0x497860 ADRP	X2,

0x497864 ADD	X2, X2, #3896

0x497868 BL	4a2830

0x49786c ORR	X3, XZR, XZR

0x497870 ADRP	X0,

0x497874 ADD	X0, X0, #3416

0x497878 MOVZ	W1, #472

0x49787c MOVZ	W2, #1

0x497880 BL	4a5070

0x497884 LDR	X8, [X28]

0x497888 TBNZ	X22, #63, 497894

0x49788c CMP	X22, X8

0x497890 B.LE	4978c4

0x497894 LDR	X0, [X23]

0x497898 ADRP	X1,

0x49789c ADD	X1, X1, #675

0x4978a0 ADRP	X2,

0x4978a4 ADD	X2, X2, #3931

0x4978a8 BL	4a2830

0x4978ac ORR	X3, XZR, XZR

0x4978b0 ADRP	X0,

0x4978b4 ADD	X0, X0, #3416

0x4978b8 MOVZ	W1, #473

0x4978bc MOVZ	W2, #1

0x4978c0 BL	4a5070

0x4978c4 LDR	X9, [X19]

0x4978c8 LDR	X8, [X24]

0x4978cc MADD	X10, X20, X9, XZR

0x4978d0 UBFM	X2, X9, #61, #60

0x4978d4 ADD	X0, X8, X10,LSL #3

0x4978d8 RDVL	X8, #1

0x4978dc CMP	X8, #17

0x4978e0 B.CS	4978f0

0x4978e4 ORR	W1, WZR, WZR

0x4978e8 BL	40f7d0

0x4978ec B	497910

0x4978f0 WHILELO	P0.B, XZR, X2

0x4978f4 ORR	X8, XZR, XZR

0x4978f8 DUP	Z0.B, #0

0x4978fc HINT	#0

(1610) 0x497900 ST1B	{Z0.B}, P0, [X0, X8]

(1610) 0x497904 INCP	X8, P0.B

(1610) 0x497908 WHILELO	P0.B, X8, X2

(1610) 0x49790c B.MI	497900

0x497910 LDR	X8, [SP, #8]

0x497914 LDR	X8, [X8]

0x497918 LDR	X9, [X8, X21,LSL #3]

0x49791c LDR	X10, [X8, X22,LSL #3]

0x497920 CMP	X9, X10

0x497924 B.GE	497968

0x497928 LDR	X10, [X25]

0x49792c LDR	X11, [X24]

0x497930 HINT	#0

0x497934 HINT	#0

0x497938 HINT	#0

0x49793c HINT	#0

(1618) 0x497940 LDR	X12, [X10, X9,LSL #3]

(1618) 0x497944 LDR	X13, [X19]

(1618) 0x497948 ADD	X9, X9, #1

(1618) 0x49794c MADD	X12, X20, X13, X12

(1618) 0x497950 LDR	X13, [X11, X12,LSL #3]

(1618) 0x497954 ADD	X13, X13, #1

(1618) 0x497958 STR	X13, [X11, X12,LSL #3]

(1618) 0x49795c LDR	X12, [X8, X22,LSL #3]

(1618) 0x497960 CMP	X9, X12

(1618) 0x497964 B.LT	497940

0x497968 LDR	W27, [X27]

0x49796c ADRP	X0,

0x497970 ADD	X0, X0, #304

0x497974 ORR	W1, WZR, W27

0x497978 BL	40f4b0

0x49797c LDR	X9, [X19]

0x497980 ADD	X28, X20, #1

0x497984 MADD	X10, X9, X20, XZR

0x497988 MADD	X8, X9, X28, XZR

0x49798c ADD	X11, X10, #1

0x497990 CMP	X11, X8

0x497994 B.GE	4979e0

0x497998 LDR	X8, [X24]

0x49799c HINT	#0

(1617) 0x4979a0 SDIV	X12, X11, X26

(1617) 0x4979a4 MSUB	X13, X26, X12, X11

(1617) 0x4979a8 MADD	X12, X9, X13, X12

(1617) 0x4979ac SDIV	X13, X10, X26

(1617) 0x4979b0 MSUB	X10, X13, X26, X10

(1617) 0x4979b4 MADD	X9, X9, X10, X13

(1617) 0x4979b8 LDR	X10, [X8, X12,LSL #3]

(1617) 0x4979bc LDR	X9, [X8, X9,LSL #3]

(1617) 0x4979c0 ADD	X9, X10, X9

(1617) 0x4979c4 ORR	X10, XZR, X11

(1617) 0x4979c8 ADD	X11, X11, #1

(1617) 0x4979cc STR	X9, [X8, X12,LSL #3]

(1617) 0x4979d0 LDR	X9, [X19]

(1617) 0x4979d4 MADD	X12, X9, X28, XZR

(1617) 0x4979d8 CMP	X11, X12

(1617) 0x4979dc B.LT	4979a0

0x4979e0 LDR	X23, [X29, #96]

0x4979e4 ORR	W1, WZR, W27

0x4979e8 ADRP	X0,

0x4979ec ADD	X0, X0, #328

0x4979f0 BL	40f4b0

0x4979f4 ORR	W1, WZR, W27

0x4979f8 ADRP	X0,

0x4979fc ADD	X0, X0, #352

0x497a00 BL	40f9f0

0x497a04 CBZ	W0, 497a78

0x497a08 CMP	X26, #2

0x497a0c B.LT	497a68

0x497a10 LDR	X8, [X24]

0x497a14 MOVZ	W9, #1

0x497a18 HINT	#0

0x497a1c HINT	#0

(1616) 0x497a20 LDR	X10, [X19]

(1616) 0x497a24 MADD	X11, X10, X9, XZR

(1616) 0x497a28 ADD	X9, X9, #1

(1616) 0x497a2c MADD	X12, X10, X9, XZR

(1616) 0x497a30 CMP	X26, X9

(1616) 0x497a34 SUB	X11, X11, #1

(1616) 0x497a38 SUB	X12, X12, #1

(1616) 0x497a3c SDIV	X13, X11, X26

(1616) 0x497a40 MSUB	X11, X13, X26, X11

(1616) 0x497a44 SDIV	X14, X12, X26

(1616) 0x497a48 MSUB	X12, X14, X26, X12

(1616) 0x497a4c MADD	X11, X10, X11, X13

(1616) 0x497a50 MADD	X10, X10, X12, X14

(1616) 0x497a54 LDR	X11, [X8, X11,LSL #3]

(1616) 0x497a58 LDR	X12, [X8, X10,LSL #3]

(1616) 0x497a5c ADD	X11, X12, X11

(1616) 0x497a60 STR	X11, [X8, X10,LSL #3]

(1616) 0x497a64 B.NE	497a20

0x497a68 ORR	W1, WZR, W27

0x497a6c ADRP	X0,

0x497a70 ADD	X0, X0, #352

0x497a74 BL	40f920

0x497a78 LDR	X8, [X29, #120]

0x497a7c ORR	W1, WZR, W27

0x497a80 ADRP	X0,

0x497a84 ADD	X0, X0, #376

0x497a88 STR	X8, [SP]

0x497a8c BL	40f4b0

0x497a90 CMP	X20, #1

0x497a94 B.LT	497af4

0x497a98 LDR	X10, [X19]

0x497a9c MOVN	X9, #0

0x497aa0 MADD	X8, X10, X20, XZR

0x497aa4 MADD	X11, X10, X28, X9

0x497aa8 CMP	X8, X11

0x497aac B.GE	497af4

0x497ab0 SUB	X11, X8, #1

0x497ab4 SDIV	X12, X11, X26

0x497ab8 MSUB	X11, X12, X26, X11

0x497abc MADD	X12, X10, X11, X12

0x497ac0 LDR	X11, [X24]

0x497ac4 LDR	X12, [X11, X12,LSL #3]

(1615) 0x497ac8 SDIV	X13, X8, X26

(1615) 0x497acc MSUB	X14, X26, X13, X8

(1615) 0x497ad0 ADD	X8, X8, #1

(1615) 0x497ad4 MADD	X10, X10, X14, X13

(1615) 0x497ad8 LDR	X13, [X11, X10,LSL #3]

(1615) 0x497adc ADD	X13, X13, X12

(1615) 0x497ae0 STR	X13, [X11, X10,LSL #3]

(1615) 0x497ae4 LDR	X10, [X19]

(1615) 0x497ae8 MADD	X13, X10, X28, X9

(1615) 0x497aec CMP	X8, X13

(1615) 0x497af0 B.LT	497ac8

0x497af4 ORR	W1, WZR, W27

0x497af8 ADRP	X0,

0x497afc ADD	X0, X0, #400

0x497b00 BL	40f4b0

0x497b04 LDR	X8, [X23]

0x497b08 CBZ	X8, 497bc4

0x497b0c CMP	X22, X21

0x497b10 B.LE	497c5c

0x497b14 LDP	X11, X10, [X29, #104]

0x497b18 LDR	X8, [SP, #8]

0x497b1c LDR	X13, [X25]

0x497b20 SUB	X13, X13, #8

0x497b24 LDR	X8, [X8]

0x497b28 LDR	X12, [X10]

0x497b2c LDR	X10, [X11]

0x497b30 LDR	X11, [SP]

0x497b34 LDR	X9, [X24]

0x497b38 LDR	X11, [X11]

0x497b3c LDR	X14, [X8, X22,LSL #3]

0x497b40 SUB	X12, X12, #8

0x497b44 SUB	X22, X22, #1

0x497b48 LDR	X15, [X8, X22,LSL #3]

0x497b4c CMP	X14, X15

0x497b50 B.GT	497b80

0x497b54 HINT	#0

0x497b58 HINT	#0

0x497b5c HINT	#0

  (1614) 0x497b60 ORR	X14, XZR, X15

  (1614) 0x497b64 CMP	X22, X21

  (1614) 0x497b68 B.LE	497c5c

  (1614) 0x497b6c SUB	X22, X22, #1

  (1614) 0x497b70 LDR	X15, [X8, X22,LSL #3]

  (1614) 0x497b74 CMP	X14, X15

  (1614) 0x497b78 B.LE	497b60

(1613) 0x497b7c HINT	#0

(1613) 0x497b80 LDR	X15, [X13, X14,LSL #3]

(1613) 0x497b84 LDR	X16, [X19]

(1613) 0x497b88 LDR	D0, [X12, X14,LSL #3]

(1613) 0x497b8c SUB	X14, X14, #1

(1613) 0x497b90 MADD	X16, X20, X16, X15

(1613) 0x497b94 LDR	X17, [X9, X16,LSL #3]

(1613) 0x497b98 SUB	X17, X17, #1

(1613) 0x497b9c STR	X17, [X9, X16,LSL #3]

(1613) 0x497ba0 LDR	X16, [X19]

(1613) 0x497ba4 MADD	X15, X20, X16, X15

(1613) 0x497ba8 LDR	X15, [X9, X15,LSL #3]

(1613) 0x497bac STR	D0, [X10, X15,LSL #3]

(1613) 0x497bb0 STR	X22, [X11, X15,LSL #3]

(1613) 0x497bb4 LDR	X15, [X8, X22,LSL #3]

(1613) 0x497bb8 CMP	X14, X15

(1613) 0x497bbc B.GT	497b80

(1613) 0x497bc0 B	497b60

0x497bc4 CMP	X22, X21

0x497bc8 B.LE	497c5c

0x497bcc LDP	X10, X8, [SP]

0x497bd0 LDR	X11, [X25]

0x497bd4 LDR	X9, [X24]

0x497bd8 SUB	X11, X11, #8

0x497bdc LDR	X8, [X8]

0x497be0 LDR	X10, [X10]

0x497be4 LDR	X12, [X8, X22,LSL #3]

0x497be8 SUB	X22, X22, #1

0x497bec LDR	X13, [X8, X22,LSL #3]

0x497bf0 CMP	X12, X13

0x497bf4 B.GT	497c20

0x497bf8 HINT	#0

0x497bfc HINT	#0

  (1612) 0x497c00 ORR	X12, XZR, X13

  (1612) 0x497c04 CMP	X22, X21

  (1612) 0x497c08 B.LE	497c5c

  (1612) 0x497c0c SUB	X22, X22, #1

  (1612) 0x497c10 LDR	X13, [X8, X22,LSL #3]

  (1612) 0x497c14 CMP	X12, X13

  (1612) 0x497c18 B.LE	497c00

(1611) 0x497c1c HINT	#0

(1611) 0x497c20 LDR	X13, [X11, X12,LSL #3]

(1611) 0x497c24 LDR	X14, [X19]

(1611) 0x497c28 SUB	X12, X12, #1

(1611) 0x497c2c MADD	X14, X20, X14, X13

(1611) 0x497c30 LDR	X15, [X9, X14,LSL #3]

(1611) 0x497c34 SUB	X15, X15, #1

(1611) 0x497c38 STR	X15, [X9, X14,LSL #3]

(1611) 0x497c3c LDR	X14, [X19]

(1611) 0x497c40 MADD	X13, X20, X14, X13

(1611) 0x497c44 LDR	X13, [X9, X13,LSL #3]

(1611) 0x497c48 STR	X22, [X10, X13,LSL #3]

(1611) 0x497c4c LDR	X13, [X8, X22,LSL #3]

(1611) 0x497c50 CMP	X12, X13

(1611) 0x497c54 B.GT	497c20

(1611) 0x497c58 B	497c00

0x497c5c LDP	X20, X19, [SP, #96]

0x497c60 LDP	X22, X21, [SP, #80]

0x497c64 LDP	X24, X23, [SP, #64]

0x497c68 LDP	X26, X25, [SP, #48]

0x497c6c LDP	X28, X27, [SP, #32]

0x497c70 LDP	X29, X30, [SP, #16]

0x497c74 ADD	SP, SP, #112

0x497c78 RET

0x497c7c HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	csr_matop.c:380-560
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:380,463-476,483-485,493-532,539-560.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 28.25 to 2.00 cycles (14.12x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 22% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 28.25 to 10.00 cycles (2.83x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 28.25 to 8.50 cycles (3.32x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 460 bytes. The binary function is storing 112 bytes.

General properties

nb instructions	205
loop length	820
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

23.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	18.00	18.00	28.25	28.25	28.25	28.25	0.50	0.50	0.00	0.00	19.33	19.33	19.33	4.00	4.00
cycles	18.00	18.00	28.25	28.25	28.25	28.25	0.50	0.50	0.00	0.00	19.33	19.33	19.33	4.00	4.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	23.88
Overall L1	28.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 28.25 cycles. At this rate:

16% of peak load performance is reached (16.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (3.96 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4977a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X6, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X24, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X28, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X27, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a4700 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X26, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a4720 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4997d0 <hypre_CSRMatrixGetLoadBalancedPartitionBegin>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 499860 <hypre_CSRMatrixGetLoadBalancedPartitionEnd>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X23, <4df800>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X21, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X23, [X23, #3824]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.LE 497844 <.omp_outlined..7+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X1, <4b6818>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, #675	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, <4b7820>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #3881	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2830 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4b7830>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3416	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #471	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a5070 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
TBNZ X21, #63, 497854 <.omp_outlined..7+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X21, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 497888 <.omp_outlined..7+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X1, <4b6858>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, #675	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, <4b7860>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #3896	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2830 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4b7870>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3416	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #472	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a5070 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
TBNZ X22, #63, 497894 <.omp_outlined..7+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X22, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4978c4 <.omp_outlined..7+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X1, <4b6898>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, #675	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, <4b78a0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #3931	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2830 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4b78b0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3416	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #473	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a5070 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X10, X20, X9, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X2, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X8, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RDVL X8, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X8, #17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 4978f0 <.omp_outlined..7+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f7d0 <@plt_start@+0x370>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 497910 <.omp_outlined..7+0x170>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
WHILELO P0.B, XZR, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z0.B, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
HINT #0
LDR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X8, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 497968 <.omp_outlined..7+0x1c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
HINT #0
HINT #0
HINT #0
HINT #0
LDR W27, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <4df96c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X28, X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X10, X9, X20, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X8, X9, X28, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X11, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4979e0 <.omp_outlined..7+0x240>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
HINT #0
LDR X23, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4df9e8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #328	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4df9f8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #352	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f9f0 <@plt_start@+0x590>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W0, 497a78 <.omp_outlined..7+0x2d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X26, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 497a68 <.omp_outlined..7+0x2c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4dfa6c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #352	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f920 <@plt_start@+0x4c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4dfa80>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #376	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 497af4 <.omp_outlined..7+0x354>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X8, X10, X20, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X11, X10, X28, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X8, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 497af4 <.omp_outlined..7+0x354>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X11, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV X12, X11, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
MSUB X11, X12, X26, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X12, X10, X11, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X11, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X11, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4dfaf8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X8, 497bc4 <.omp_outlined..7+0x424>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X22, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 497c5c <.omp_outlined..7+0x4bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X13, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X8, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X12, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X22, X22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X15, [X8, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 497b80 <.omp_outlined..7+0x3e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
CMP X22, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 497c5c <.omp_outlined..7+0x4bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X10, X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X11, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X11, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X8, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X22, X22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X13, [X8, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X12, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 497c20 <.omp_outlined..7+0x480>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
LDP X20, X19, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Source file and lines	csr_matop.c:380-560
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:380,463-476,483-485,493-532,539-560.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 28.25 to 8.50 cycles (3.32x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 460 bytes. The binary function is storing 112 bytes.

General properties

nb instructions	205
loop length	820
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

23.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	18.00	18.00	28.25	28.25	28.25	28.25	0.50	0.50	0.00	0.00	19.33	19.33	19.33	4.00	4.00
cycles	18.00	18.00	28.25	28.25	28.25	28.25	0.50	0.50	0.00	0.00	19.33	19.33	19.33	4.00	4.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	23.88
Overall L1	28.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 28.25 cycles. At this rate:

16% of peak load performance is reached (16.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (3.96 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4977a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X6, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X24, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X28, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X27, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a4700 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X26, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a4720 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4997d0 <hypre_CSRMatrixGetLoadBalancedPartitionBegin>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 499860 <hypre_CSRMatrixGetLoadBalancedPartitionEnd>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X23, <4df800>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X21, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X23, [X23, #3824]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.LE 497844 <.omp_outlined..7+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X1, <4b6818>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, #675	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, <4b7820>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #3881	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2830 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4b7830>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3416	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #471	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a5070 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
TBNZ X21, #63, 497854 <.omp_outlined..7+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X21, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 497888 <.omp_outlined..7+0xe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X1, <4b6858>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, #675	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, <4b7860>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #3896	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2830 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4b7870>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3416	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #472	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a5070 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
TBNZ X22, #63, 497894 <.omp_outlined..7+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X22, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4978c4 <.omp_outlined..7+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X0, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X1, <4b6898>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, #675	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, <4b78a0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #3931	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2830 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4b78b0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #3416	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #473	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a5070 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X10, X20, X9, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X2, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X8, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RDVL X8, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X8, #17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CS 4978f0 <.omp_outlined..7+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, WZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f7d0 <@plt_start@+0x370>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 497910 <.omp_outlined..7+0x170>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
WHILELO P0.B, XZR, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
DUP Z0.B, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50
HINT #0
LDR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X8, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 497968 <.omp_outlined..7+0x1c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
HINT #0
HINT #0
HINT #0
HINT #0
LDR W27, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <4df96c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X28, X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X10, X9, X20, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X8, X9, X28, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X11, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X11, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4979e0 <.omp_outlined..7+0x240>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
HINT #0
LDR X23, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4df9e8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #328	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4df9f8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #352	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f9f0 <@plt_start@+0x590>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W0, 497a78 <.omp_outlined..7+0x2d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X26, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 497a68 <.omp_outlined..7+0x2c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4dfa6c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #352	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f920 <@plt_start@+0x4c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4dfa80>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #376	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 497af4 <.omp_outlined..7+0x354>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X8, X10, X20, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X11, X10, X28, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP X8, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 497af4 <.omp_outlined..7+0x354>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB X11, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV X12, X11, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
MSUB X11, X12, X26, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X12, X10, X11, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X11, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X11, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4dfaf8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X8, 497bc4 <.omp_outlined..7+0x424>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X22, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 497c5c <.omp_outlined..7+0x4bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X10, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X13, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X8, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X12, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X22, X22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X15, [X8, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X14, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 497b80 <.omp_outlined..7+0x3e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
CMP X22, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 497c5c <.omp_outlined..7+0x4bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X10, X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X11, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X11, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X8, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X22, X22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X13, [X8, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X12, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 497c20 <.omp_outlined..7+0x480>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
LDP X20, X19, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..7#0x4977a0–	0.38	0.14
▼Loop 1613 - csr_matop.c:540-548 - exec–	0.28	0.09
○Loop 1614 - csr_matop.c:540-541 - exec	0	0.01
○Loop 1610 - csr_matop.c:476-476 - exec	0.06	0.02
○Loop 1617 - csr_matop.c:380-500 - exec	0.02	0.01
○Loop 1615 - csr_matop.c:380-527 - exec	0.02	0
○Loop 1618 - csr_matop.c:483-485 - exec	0	0
▼Loop 1611 - csr_matop.c:553-560 - exec–	0	0
○Loop 1612 - csr_matop.c:553-554 - exec	0	0
○Loop 1616 - csr_matop.c:380-513 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code