OV - exec - Function .omp_outlined..30#0x475180

	Function: .omp_outlined..30#0x475180	Module: exec	Source: ams.c:3662-3682	Coverage: 31.12%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 3662 - 3682

--------------------------------------------------------------------------------

3662: #pragma omp parallel for private(i,ii,jj,res) HYPRE_SMP_SCHEDULE

3663: #endif

3664:       for (i = 0; i < n; i++)

3665:       {

3666:          /*-----------------------------------------------------------

3667:           * If diagonal is nonzero, relax point i; otherwise, skip it.

3668:           *-----------------------------------------------------------*/

3669:          if (A_diag_data[A_diag_i[i]] != zero)

3670:          {

3671:             res = f_data[i];

3672:             for (jj = A_diag_i[i]; jj < A_diag_i[i+1]; jj++)

3673:             {

3674:                ii = A_diag_j[jj];

3675:                res -= A_diag_data[jj] * Vtemp_data[ii];

3676:             }

3677:             for (jj = A_offd_i[i]; jj < A_offd_i[i+1]; jj++)

3678:             {

3679:                ii = A_offd_j[jj];

3680:                res -= A_offd_data[jj] * Vext_data[ii];

3681:             }

3682:             u_data[i] += (relax_weight*res)/l1_norms[i];

0x475180 SUB	SP, SP, #160

0x475184 STP	X29, X30, [SP, #64]

0x475188 STP	X28, X27, [SP, #80]

0x47518c STP	X26, X25, [SP, #96]

0x475190 STP	X24, X23, [SP, #112]

0x475194 STP	X22, X21, [SP, #128]

0x475198 STP	X20, X19, [SP, #144]

0x47519c ADD	X29, SP, #64

0x4751a0 LDR	X8, [X2]

0x4751a4 SUBS	X19, X8, #1

0x4751a8 B.LT	475254

0x4751ac LDR	X8, [X29, #152]

0x4751b0 LDP	X10, X9, [X29, #128]

0x4751b4 LDP	X12, X11, [X29, #112]

0x4751b8 MOVZ	W2, #34

0x4751bc LDP	X14, X13, [X29, #96]

0x4751c0 LDR	X15, [X6]

0x4751c4 SUB	X6, X29, #24

0x4751c8 LDR	W1, [X0]

0x4751cc ADRP	X0,

0x4751d0 ADD	X0, X0, #896

0x4751d4 LDR	X21, [X3]

0x4751d8 SUB	X3, X29, #28

0x4751dc LDR	X22, [X4]

0x4751e0 SUB	X4, X29, #8

0x4751e4 LDR	X24, [X7]

0x4751e8 MOVZ	W7, #1

0x4751ec LDR	X8, [X8]

0x4751f0 LDR	X25, [X14]

0x4751f4 LDR	X26, [X13]

0x4751f8 LDR	X27, [X12]

0x4751fc LDR	X28, [X11]

0x475200 LDR	X20, [X10]

0x475204 MOVZ	W10, #1

0x475208 LDR	X23, [X9]

0x47520c STR	X5, [SP, #24]

0x475210 SUB	X5, X29, #16

0x475214 STP	X19, XZR, [X29, #1008]

0x475218 STUR	WZR, [X29, #484]

0x47521c STR	W1, [SP, #32]

0x475220 STUR	X10, [X29, #488]

0x475224 STR	X10, [SP]

0x475228 STP	X8, X15, [SP, #8]

0x47522c BL	40fa80

0x475230 LDP	X8, X9, [X29, #1008]

0x475234 CMP	X8, X19

0x475238 CSEL	X10, X8, X19, #11

0x47523c CMP	X9, X10

0x475240 B.LE	475274

  (1274) 0x475244 LDR	W1, [SP, #32]

  (1274) 0x475248 ADRP	X0,

  (1274) 0x47524c ADD	X0, X0, #920

  (1274) 0x475250 BL	40f990

  (1274) 0x475254 LDP	X20, X19, [SP, #144]

  (1274) 0x475258 LDP	X22, X21, [SP, #128]

  (1274) 0x47525c LDP	X24, X23, [SP, #112]

  (1274) 0x475260 LDP	X26, X25, [SP, #96]

  (1274) 0x475264 LDP	X28, X27, [SP, #80]

  (1274) 0x475268 LDP	X29, X30, [SP, #64]

  (1274) 0x47526c ADD	SP, SP, #160

  (1274) 0x475270 RET

  (1274) 0x475274 LDP	X3, X2, [SP, #16]

  (1274) 0x475278 LDR	X8, [X29, #144]

  (1274) 0x47527c LDR	X4, [SP, #8]

  (1274) 0x475280 ADD	X10, X10, #1

  (1274) 0x475284 ADD	X11, X24, #16

  (1274) 0x475288 ADD	X12, X21, #16

  (1274) 0x47528c ADD	X13, X27, #16

  (1274) 0x475290 ADD	X14, X28, #16

  (1274) 0x475294 LDR	D0, [X2]

  (1274) 0x475298 B	4752cc

0x47529c HINT	#0

  (1274) 0x4752a0 LDR	D1, [X8]

  (1274) 0x4752a4 FMUL	D0, D0, D1

  (1274) 0x4752a8 LDR	D1, [X4, X9,LSL #3]

  (1274) 0x4752ac FDIV	D0, D0, D1

  (1274) 0x4752b0 LDR	D1, [X23, X9,LSL #3]

  (1274) 0x4752b4 FADD	D0, D1, D0

  (1274) 0x4752b8 STR	D0, [X23, X9,LSL #3]

  (1274) 0x4752bc LDR	D0, [X2]

  (1274) 0x4752c0 ORR	X9, XZR, X15

  (1274) 0x4752c4 CMP	X15, X10

  (1274) 0x4752c8 B.EQ	475244

  (1274) 0x4752cc LDR	X16, [X22, X9,LSL #3]

  (1274) 0x4752d0 LDR	D1, [X21, X16,LSL #3]

  (1274) 0x4752d4 FCMP	D1, D0

  (1274) 0x4752d8 B.EQ	475340

  (1274) 0x4752dc LDR	D0, [X3, X9,LSL #3]

  (1274) 0x4752e0 ADD	X15, X9, #1

  (1274) 0x4752e4 LDR	X17, [X22, X15,LSL #3]

  (1274) 0x4752e8 CMP	X17, X16

  (1274) 0x4752ec B.LE	4753b8

  (1274) 0x4752f0 SUB	W18, W17, W16

  (1274) 0x4752f4 ANDS	X0, X18, #4160

  (1274) 0x4752f8 B.EQ	475354

  (1274) 0x4752fc ORR	X18, XZR, X16

    (1278) 0x475300 LDR	X1, [X24, X18,LSL #3]

    (1278) 0x475304 LDR	D1, [X21, X18,LSL #3]

    (1278) 0x475308 ADD	X18, X18, #1

    (1278) 0x47530c SUBS	X0, X0, #1

    (1278) 0x475310 LDR	D2, [X25, X1,LSL #3]

    (1278) 0x475314 FMSUB	D0, D1, D2, D0

    (1278) 0x475318 B.NE	475300

  (1274) 0x47531c ORN	X16, XZR, X16

  (1274) 0x475320 ADD	X16, X17, X16

  (1274) 0x475324 CMP	X16, #3

  (1274) 0x475328 B.CS	475368

  (1274) 0x47532c B	4753b8

0x475330 HINT	#0

0x475334 HINT	#0

0x475338 HINT	#0

0x47533c HINT	#0

(1273) 0x475340 ADD	X15, X9, #1

(1273) 0x475344 ORR	X9, XZR, X15

(1273) 0x475348 CMP	X15, X10

(1273) 0x47534c B.NE	4752cc

(1273) 0x475350 B	475244

  (1274) 0x475354 ORR	X18, XZR, X16

  (1274) 0x475358 ORN	X16, XZR, X16

  (1274) 0x47535c ADD	X16, X17, X16

  (1274) 0x475360 CMP	X16, #3

  (1274) 0x475364 B.CC	4753b8

  (1274) 0x475368 SUB	X16, X17, X18

  (1274) 0x47536c UBFM	X18, X18, #61, #60

  (1274) 0x475370 ADD	X17, X11, X18

  (1274) 0x475374 ADD	X18, X12, X18

  (1274) 0x475378 HINT	#0

  (1274) 0x47537c HINT	#0

    (1277) 0x475380 LDP	X0, X1, [X17, #1008]

    (1277) 0x475384 LDP	D2, D3, [X18, #1008]

    (1277) 0x475388 SUBS	X16, X16, #4

    (1277) 0x47538c LDR	D1, [X25, X0,LSL #3]

    (1277) 0x475390 FMSUB	D0, D2, D1, D0

    (1277) 0x475394 LDR	D1, [X25, X1,LSL #3]

    (1277) 0x475398 FMSUB	D0, D3, D1, D0

    (1277) 0x47539c LDP	X0, X1, [X17], #32

    (1277) 0x4753a0 LDR	D2, [X25, X0,LSL #3]

    (1277) 0x4753a4 LDP	D1, D3, [X18], #32

    (1277) 0x4753a8 FMSUB	D0, D1, D2, D0

    (1277) 0x4753ac LDR	D1, [X25, X1,LSL #3]

    (1277) 0x4753b0 FMSUB	D0, D3, D1, D0

    (1277) 0x4753b4 B.NE	475380

  (1274) 0x4753b8 LDR	X17, [X26, X9,LSL #3]

  (1274) 0x4753bc LDR	X16, [X26, X15,LSL #3]

  (1274) 0x4753c0 CMP	X16, X17

  (1274) 0x4753c4 B.LE	4752a0

  (1274) 0x4753c8 SUB	W18, W16, W17

  (1274) 0x4753cc ANDS	X0, X18, #4160

  (1274) 0x4753d0 B.EQ	475410

  (1274) 0x4753d4 ORR	X18, XZR, X17

  (1274) 0x4753d8 HINT	#0

  (1274) 0x4753dc HINT	#0

    (1276) 0x4753e0 LDR	X1, [X27, X18,LSL #3]

    (1276) 0x4753e4 LDR	D1, [X28, X18,LSL #3]

    (1276) 0x4753e8 ADD	X18, X18, #1

    (1276) 0x4753ec SUBS	X0, X0, #1

    (1276) 0x4753f0 LDR	D2, [X20, X1,LSL #3]

    (1276) 0x4753f4 FMSUB	D0, D1, D2, D0

    (1276) 0x4753f8 B.NE	4753e0

  (1274) 0x4753fc ORN	X17, XZR, X17

  (1274) 0x475400 ADD	X17, X16, X17

  (1274) 0x475404 CMP	X17, #3

  (1274) 0x475408 B.CC	4752a0

  (1274) 0x47540c B	475424

  (1274) 0x475410 ORR	X18, XZR, X17

  (1274) 0x475414 ORN	X17, XZR, X17

  (1274) 0x475418 ADD	X17, X16, X17

  (1274) 0x47541c CMP	X17, #3

  (1274) 0x475420 B.CC	4752a0

  (1274) 0x475424 SUB	X16, X16, X18

  (1274) 0x475428 UBFM	X18, X18, #61, #60

  (1274) 0x47542c ADD	X17, X13, X18

  (1274) 0x475430 ADD	X18, X14, X18

  (1274) 0x475434 HINT	#0

  (1274) 0x475438 HINT	#0

  (1274) 0x47543c HINT	#0

    (1275) 0x475440 LDP	X0, X1, [X17, #1008]

    (1275) 0x475444 LDP	D2, D3, [X18, #1008]

    (1275) 0x475448 SUBS	X16, X16, #4

    (1275) 0x47544c LDR	D1, [X20, X0,LSL #3]

    (1275) 0x475450 FMSUB	D0, D2, D1, D0

    (1275) 0x475454 LDR	D1, [X20, X1,LSL #3]

    (1275) 0x475458 FMSUB	D0, D3, D1, D0

    (1275) 0x47545c LDP	X0, X1, [X17], #32

    (1275) 0x475460 LDR	D2, [X20, X0,LSL #3]

    (1275) 0x475464 LDP	D1, D3, [X18], #32

    (1275) 0x475468 FMSUB	D0, D1, D2, D0

    (1275) 0x47546c LDR	D1, [X20, X1,LSL #3]

    (1275) 0x475470 FMSUB	D0, D3, D1, D0

    (1275) 0x475474 B.NE	475440

  (1274) 0x475478 B	4752a0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	ams.c:3662-3682
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662-3682.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your function, you can lower the cost of an iteration from 10.50 to 2.63 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 10.50 to 0.50 cycles (21.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 172 bytes. The binary function is storing 160 bytes.

General properties

nb instructions	54
loop length	216
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	10.50	10.17	10.33	6.50	6.50
cycles	1.50	1.50	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	10.50	10.17	10.33	6.50	6.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.13
Overall L1	10.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.50 cycles. At this rate:

17% of peak load performance is reached (16.38 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
31% of peak store performance is reached (15.24 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 475180

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS X19, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 475254 <.omp_outlined..30+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X10, X9, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X12, X11, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X14, X13, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X15, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X6, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <4de1cc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #896	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X21, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X3, X29, #28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X22, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X4, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X24, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X20, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X23, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X5, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR WZR, [X29, #484]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W1, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X10, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X10, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X8, X15, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40fa80 <@plt_start@+0x620>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X8, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X10, X8, X19, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 475274 <.omp_outlined..30+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0

Source file and lines	ams.c:3662-3682
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c:3662-3682.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 10.50 to 0.50 cycles (21.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 172 bytes. The binary function is storing 160 bytes.

General properties

nb instructions	54
loop length	216
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	10.50	10.17	10.33	6.50	6.50
cycles	1.50	1.50	4.00	4.00	4.00	4.00	0.00	0.00	0.00	0.00	10.50	10.17	10.33	6.50	6.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.13
Overall L1	10.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.50 cycles. At this rate:

17% of peak load performance is reached (16.38 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
31% of peak store performance is reached (15.24 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 475180

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS X19, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 475254 <.omp_outlined..30+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X10, X9, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X12, X11, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X14, X13, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X15, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X6, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <4de1cc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #896	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X21, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X3, X29, #28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X22, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X4, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X24, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X27, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X20, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X23, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X5, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SUB X5, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, XZR, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR WZR, [X29, #484]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W1, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X10, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X10, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X8, X15, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 40fa80 <@plt_start@+0x620>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X9, [X29, #1008]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CMP X8, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X10, X8, X19, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 475274 <.omp_outlined..30+0xf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..30#0x475180–	31.12	11.76
▼Loop 1273 - ams.c:3662-3682 - exec–	0	0
▼Loop 1274 - ams.c:3662-3682 - exec–	2.3	0.75
○Loop 1277 - ams.c:3672-3675 - exec	26.24	8.59
○Loop 1278 - ams.c:3672-3675 - exec	2.58	0.84
○Loop 1276 - ams.c:3677-3680 - exec	0	0
○Loop 1275 - ams.c:3677-3680 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code