OV - exec - Function .omp_outlined..22#0x435ca0

	Function: .omp_outlined..22#0x435ca0	Module: exec	Source: par_multi_interp.c:1737-1881 [...]	Coverage: 4.45%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1737 - 1881

--------------------------------------------------------------------------------

1737: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa,tmp_array,tmp_array_offd)

[...]

1747:              if (n_fine)

1748:              {    tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); }

1749:              tmp_marker_offd = NULL;

1750:              if (num_cols_offd)

1751:              {    tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); }

1752:              tmp_array = NULL;

1753:              if (n_coarse)

1754:              {    tmp_array = hypre_CTAlloc(HYPRE_Int,n_coarse); }

1755:              tmp_array_offd = NULL;

1756:              if (new_num_cols_offd > n_coarse_offd)

1757:              {    tmp_array_offd = hypre_CTAlloc(HYPRE_Int,new_num_cols_offd); }

1758:              else

1759:              {    tmp_array_offd = hypre_CTAlloc(HYPRE_Int,n_coarse_offd);}

1760:              for (i=0; i < n_fine; i++)

1761:              {    tmp_marker[i] = -1; }

1762:              for (i=0; i < num_cols_offd; i++)

1763:              {    tmp_marker_offd[i] = -1; }

1764:

1765:              /* Compute this thread's range of pass_length */

1766:              my_thread_num = hypre_GetThreadNum();

1767:              num_threads = hypre_NumActiveThreads();

1768:              thread_start = pass_pointer[pass] + (pass_length/num_threads)*my_thread_num;

1769:              if (my_thread_num == num_threads-1)

1770:              {  thread_stop = pass_pointer[pass] + pass_length; }

1771:              else

1772:              {  thread_stop = pass_pointer[pass] + (pass_length/num_threads)*(my_thread_num+1); }

1773:

1774:              for (i=thread_start; i < thread_stop; i++)

1775:              {

1776:                 i1 = pass_array[i];

1777:                 sum_C = 0;

1778:                 sum_N = 0;

1779:                 j_start = P_diag_start[i1];

1780:                 j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1781:                 cnt = P_diag_i[i1];

1782:                 for (j=j_start; j < j_end; j++)

1783:                 {

1784:                    k1 = P_diag_pass[pass][j];

1785:                tmp_array[k1] = cnt;

1786:                P_diag_data[cnt] = 0;

1787:                P_diag_j[cnt++] = k1;

1788:                 }

1789:                 j_start = P_offd_start[i1];

1790:                 j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1791:                 cnt_offd = P_offd_i[i1];

1792:                 for (j=j_start; j < j_end; j++)

1793:                 {

1794:                    k1 = P_offd_pass[pass][j];

1795:                tmp_array_offd[k1] = cnt_offd;

1796:                P_offd_data[cnt_offd] = 0;

1797:                P_offd_j[cnt_offd++] = k1;

1798:                 }

1799:                 for (j=S_diag_i[i1]; j < S_diag_i[i1+1]; j++)

1800:                 {

1801:                j1 = S_diag_j[j];

1802:                if (assigned[j1] == pass-1)

1803:                   tmp_marker[j1] = i1;

1804:                 }

1805:                 for (j=S_offd_i[i1]; j < S_offd_i[i1+1]; j++)

1806:                 {

1807:                j1 = S_offd_j[j];

1808:                if (assigned_offd[j1] == pass-1)

1809:                   tmp_marker_offd[j1] = i1;

1810:                 }

1811:                 for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1812:                 {

1813:                j1 = A_diag_j[j];

1814:                if (tmp_marker[j1] == i1)

1815:                {

1816:                   for (k=P_diag_i[j1]; k < P_diag_i[j1+1]; k++)

1817:                   {

1818:                  k1 = P_diag_j[k];

1819:                      alfa = A_diag_data[j]*P_diag_data[k];

1820:                      P_diag_data[tmp_array[k1]] += alfa;

1821:                      sum_C += alfa;

1822:                      sum_N += alfa;

1823:                       }

1824:                   for (k=P_offd_i[j1]; k < P_offd_i[j1+1]; k++)

1825:                   {

1826:                  k1 = P_offd_j[k];

1827:                      alfa = A_diag_data[j]*P_offd_data[k];

1828:                      P_offd_data[tmp_array_offd[k1]] += alfa;

1829:                      sum_C += alfa;

1830:                      sum_N += alfa;

1831:                       }

1832:                    }

1833:                    else

1834:                    {

1835:                       if (CF_marker[j1] != -3 &&

1836:                 (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1837:                  sum_N += A_diag_data[j];

1838:                    }

1839:                 }

1840:                 for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

1841:                 {

1842:                if (col_offd_S_to_A)

1843:                   j1 = map_A_to_S[A_offd_j[j]];

1844:                else

1845:                   j1 = A_offd_j[j];

1846:

1847:                if (j1 > -1 && tmp_marker_offd[j1] == i1)

1848:                {

1849:                   j_start = Pext_start[j1];

1850:                   j_end = j_start+Pext_i[j1+1];

1851:                   for (k=j_start; k < j_end; k++)

1852:                   {

1853:                  k1 = Pext_pass[pass][k];

1854:                      alfa = A_offd_data[j]*Pext_data[k];

1855:                  if (k1 < 0)

1856:                         P_diag_data[tmp_array[-k1-1]] += alfa;

1857:                  else

1858:                         P_offd_data[tmp_array_offd[k1]] += alfa;

1859:                      sum_C += alfa;

1860:                      sum_N += alfa;

1861:                       }

1862:                    }

1863:                    else

1864:                    {

1865:                       if (CF_marker_offd[j1] != -3 &&

1866:                 (num_functions == 1 || dof_func_offd[j1] == dof_func[i1]))

1867:                  sum_N += A_offd_data[j];

1868:                    }

1869:                 }

1870:                 diagonal = A_diag_data[A_diag_i[i1]];

1871:                 if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1872:

1873:                 for (j=P_diag_i[i1]; j < P_diag_i[i1+1]; j++)

1874:                P_diag_data[j] *= alfa;

1875:                 for (j=P_offd_i[i1]; j < P_offd_i[i1+1]; j++)

1876:                P_offd_data[j] *= alfa;

1877:              }

1878:              hypre_TFree(tmp_marker);

1879:              hypre_TFree(tmp_marker_offd);

1880:              hypre_TFree(tmp_array);

1881:              hypre_TFree(tmp_array_offd);

0x435ca0 SUB	SP, SP, #496

0x435ca4 STP	X29, X30, [SP, #400]

0x435ca8 STP	X28, X27, [SP, #416]

0x435cac STP	X26, X25, [SP, #432]

0x435cb0 STP	X24, X23, [SP, #448]

0x435cb4 STP	X22, X21, [SP, #464]

0x435cb8 STP	X20, X19, [SP, #480]

0x435cbc ADD	X29, SP, #400

0x435cc0 LDR	X8, [X29, #376]

0x435cc4 STUR	X7, [X29, #464]

0x435cc8 LDR	X0, [X2]

0x435ccc ORR	X22, XZR, X6

0x435cd0 ORR	X26, XZR, X5

0x435cd4 ORR	X21, XZR, X4

0x435cd8 STR	X8, [SP, #144]

0x435cdc ORR	X24, XZR, X3

0x435ce0 ORR	X25, XZR, X2

0x435ce4 LDR	X8, [X29, #368]

0x435ce8 STR	X8, [SP, #136]

0x435cec LDR	X8, [X29, #360]

0x435cf0 STR	X8, [SP, #128]

0x435cf4 LDR	X8, [X29, #352]

0x435cf8 STR	X8, [SP, #120]

0x435cfc LDR	X8, [X29, #344]

0x435d00 STR	X8, [SP, #112]

0x435d04 LDR	X8, [X29, #336]

0x435d08 STR	X8, [SP, #104]

0x435d0c LDR	X8, [X29, #328]

0x435d10 STR	X8, [SP, #96]

0x435d14 LDR	X8, [X29, #320]

0x435d18 STR	X8, [SP, #88]

0x435d1c LDR	X8, [X29, #312]

0x435d20 STR	X8, [SP, #80]

0x435d24 LDP	X8, X9, [X29, #296]

0x435d28 STP	X8, X9, [X29, #984]

0x435d2c LDP	X8, X9, [X29, #280]

0x435d30 STP	X8, X9, [X29, #920]

0x435d34 LDR	X8, [X29, #272]

0x435d38 STR	X8, [SP, #72]

0x435d3c LDR	X8, [X29, #264]

0x435d40 STR	X8, [SP, #168]

0x435d44 LDP	X8, X9, [X29, #248]

0x435d48 STP	X8, X9, [X29, #960]

0x435d4c LDP	X8, X9, [X29, #232]

0x435d50 STP	X8, X9, [X29, #944]

0x435d54 LDP	X9, X8, [X29, #216]

0x435d58 STUR	X8, [X29, #424]

0x435d5c LDR	X8, [X29, #208]

0x435d60 STP	X8, X9, [X29, #880]

0x435d64 LDR	X8, [X29, #200]

0x435d68 STUR	X8, [X29, #360]

0x435d6c LDR	X8, [X29, #192]

0x435d70 STR	X8, [SP, #160]

0x435d74 LDP	X9, X8, [X29, #176]

0x435d78 STUR	X8, [X29, #496]

0x435d7c LDR	X8, [X29, #168]

0x435d80 STP	X8, X9, [X29, #856]

0x435d84 LDR	X8, [X29, #160]

0x435d88 STUR	X8, [X29, #384]

0x435d8c LDR	X8, [X29, #152]

0x435d90 STR	X8, [SP, #152]

0x435d94 LDP	X9, X8, [X29, #136]

0x435d98 LDP	X28, X27, [X29, #96]

0x435d9c STUR	X8, [X29, #488]

0x435da0 LDR	X8, [X29, #128]

0x435da4 STP	X8, X9, [X29, #840]

0x435da8 LDP	X23, X8, [X29, #112]

0x435dac STUR	X8, [X29, #392]

0x435db0 CBZ	X0, 435dec

0x435db4 MOVZ	W1, #8

0x435db8 BL	4a2570

0x435dbc ORR	X19, XZR, X0

0x435dc0 LDR	X0, [X24]

0x435dc4 CBZ	X0, 435df8

0x435dc8 MOVZ	W1, #8

0x435dcc BL	4a2570

0x435dd0 ORR	X20, XZR, X0

0x435dd4 LDR	X0, [X21]

0x435dd8 CBZ	X0, 435e04

0x435ddc MOVZ	W1, #8

0x435de0 BL	4a2570

0x435de4 ORR	X21, XZR, X0

0x435de8 B	435e08

0x435dec ORR	X19, XZR, XZR

0x435df0 LDR	X0, [X24]

0x435df4 CBNZ	X0, 435dc8

0x435df8 ORR	X20, XZR, XZR

0x435dfc LDR	X0, [X21]

0x435e00 CBNZ	X0, 435ddc

0x435e04 ORR	X21, XZR, XZR

0x435e08 LDR	X8, [X26]

0x435e0c LDR	X9, [X22]

0x435e10 MOVZ	W1, #8

0x435e14 CMP	X8, X9

0x435e18 CSEL	X0, X8, X9, #12

0x435e1c BL	4a2570

0x435e20 LDR	X8, [X25]

0x435e24 ORR	X22, XZR, X0

0x435e28 CMP	X8, #1

0x435e2c B.LT	435e54

0x435e30 ORR	X8, XZR, XZR

0x435e34 MOVN	X9, #0

0x435e38 HINT	#0

0x435e3c HINT	#0

(1182) 0x435e40 STR	X9, [X19, X8,LSL #3]

(1182) 0x435e44 ADD	X8, X8, #1

(1182) 0x435e48 LDR	X10, [X25]

(1182) 0x435e4c CMP	X8, X10

(1182) 0x435e50 B.LT	435e40

0x435e54 LDR	X8, [X24]

0x435e58 CMP	X8, #1

0x435e5c B.LT	435e7c

0x435e60 ORR	X8, XZR, XZR

0x435e64 MOVN	X9, #0

(1181) 0x435e68 STR	X9, [X20, X8,LSL #3]

(1181) 0x435e6c ADD	X8, X8, #1

(1181) 0x435e70 LDR	X10, [X24]

(1181) 0x435e74 CMP	X8, X10

(1181) 0x435e78 B.LT	435e68

0x435e7c BL	4a4720

0x435e80 ORR	X24, XZR, X0

0x435e84 BL	4a4700

0x435e88 LDR	X8, [X27]

0x435e8c SUB	X11, X0, #1

0x435e90 CMP	X24, X11

0x435e94 SDIV	X10, X8, X0

0x435e98 MADD	X9, X10, X24, XZR

0x435e9c ADD	X10, X10, X9

0x435ea0 CSEL	X11, X8, X10, #0

0x435ea4 CMP	X9, X11

0x435ea8 B.GE	4367d8

0x435eac LDUR	X8, [X29, #464]

0x435eb0 LDR	X13, [X28]

0x435eb4 LDP	X10, X14, [SP, #152]

0x435eb8 LDR	X12, [X8]

0x435ebc LDR	X15, [X10]

0x435ec0 LDP	X8, X10, [X29, #1000]

0x435ec4 LDR	X14, [X14]

0x435ec8 LDR	X8, [X8]

0x435ecc LDR	X12, [X12, X13,LSL #3]

0x435ed0 LDR	X13, [X23]

0x435ed4 LDR	X10, [X10]

0x435ed8 STUR	X13, [X29, #400]

0x435edc LDUR	X13, [X29, #392]

0x435ee0 ADD	X27, X9, X12

0x435ee4 LDUR	X9, [X29, #456]

0x435ee8 ADD	X11, X11, X12

0x435eec LDR	X12, [X13]

0x435ef0 LDR	X9, [X9]

0x435ef4 LDUR	X13, [X29, #328]

0x435ef8 LDR	X4, [X13]

0x435efc LDUR	X13, [X29, #336]

0x435f00 LDR	X2, [X13]

0x435f04 LDUR	X13, [X29, #384]

0x435f08 LDR	X13, [X13]

0x435f0c STP	X13, X12, [X29, #896]

0x435f10 LDUR	X13, [X29, #344]

0x435f14 LDR	X13, [X13]

0x435f18 STUR	X13, [X29, #464]

0x435f1c LDUR	X13, [X29, #352]

0x435f20 LDR	X3, [X13]

0x435f24 LDUR	X13, [X29, #360]

0x435f28 LDR	X5, [X13]

0x435f2c LDUR	X13, [X29, #368]

0x435f30 LDR	X6, [X13]

0x435f34 LDUR	X13, [X29, #376]

0x435f38 LDR	X23, [X13]

0x435f3c LDUR	X13, [X29, #424]

0x435f40 LDR	X24, [X13]

0x435f44 LDUR	X13, [X29, #432]

0x435f48 LDR	X25, [X13]

0x435f4c LDUR	X13, [X29, #440]

0x435f50 LDR	X26, [X13]

0x435f54 LDUR	X13, [X29, #448]

0x435f58 LDR	X13, [X13]

0x435f5c STP	X11, X13, [X29, #880]

0x435f60 STR	X9, [SP, #64]

0x435f64 ADD	X11, X15, #8

0x435f68 LDUR	X9, [X29, #472]

0x435f6c LDR	X9, [X9]

0x435f70 STUR	X9, [X29, #360]

0x435f74 LDUR	X9, [X29, #480]

0x435f78 STR	X15, [SP, #56]

0x435f7c LDR	X30, [X9]

0x435f80 ADD	X9, X8, #8

0x435f84 STP	X9, X11, [SP, #32]

0x435f88 LDR	X9, [SP, #168]

0x435f8c ADD	X11, X14, #8

0x435f90 LDR	X9, [X9]

0x435f94 STUR	X9, [X29, #352]

0x435f98 ADD	X9, X10, #8

0x435f9c STR	X14, [SP, #48]

0x435fa0 STP	X9, X11, [SP, #16]

0x435fa4 ADD	X11, X8, #16

0x435fa8 ADD	X9, X10, #16

0x435fac STP	X9, X11, [SP]

0x435fb0 STUR	X4, [X29, #456]

0x435fb4 STP	X3, X2, [X29, #848]

0x435fb8 STP	X6, X5, [X29, #832]

0x435fbc STP	X24, X23, [SP, #192]

0x435fc0 STP	X26, X25, [SP, #176]

0x435fc4 B	435fd8

  (1169) 0x435fc8 LDUR	X9, [X29, #368]

  (1169) 0x435fcc ADD	X27, X27, #1

  (1169) 0x435fd0 CMP	X27, X9

  (1169) 0x435fd4 B.GE	4367d8

  (1169) 0x435fd8 LDUR	X9, [X29, #400]

  (1169) 0x435fdc LDR	X11, [X9, X27,LSL #3]

  (1169) 0x435fe0 LDUR	X9, [X29, #392]

  (1169) 0x435fe4 ADD	X12, X11, #1

  (1169) 0x435fe8 LDR	X9, [X9, X11,LSL #3]

  (1169) 0x435fec LDR	X16, [X4, X11,LSL #3]

  (1169) 0x435ff0 LDR	X0, [X4, X12,LSL #3]

  (1169) 0x435ff4 ADD	X13, X0, X9

  (1169) 0x435ff8 SUB	X13, X13, X16

  (1169) 0x435ffc CMP	X9, X13

  (1169) 0x436000 B.GE	4360ac

  (1169) 0x436004 SUB	W18, W0, W16

  (1169) 0x436008 ADD	X15, X16, #1

  (1169) 0x43600c TBZ	W18, #0, 436034

  (1169) 0x436010 LDR	X18, [X28]

  (1169) 0x436014 LDR	X14, [SP, #56]

  (1169) 0x436018 STR	XZR, [X8, X16,LSL #3]

  (1169) 0x43601c LDR	X18, [X2, X18,LSL #3]

  (1169) 0x436020 LDR	X18, [X18, X9,LSL #3]

  (1169) 0x436024 ADD	X9, X9, #1

  (1169) 0x436028 STR	X16, [X21, X18,LSL #3]

  (1169) 0x43602c STR	X18, [X14, X16,LSL #3]

  (1169) 0x436030 ORR	X16, XZR, X15

  (1169) 0x436034 CMP	X0, X15

  (1169) 0x436038 B.EQ	4360ac

  (1169) 0x43603c LDR	X14, [SP, #40]

  (1169) 0x436040 UBFM	X15, X16, #61, #60

  (1169) 0x436044 ADD	X0, X14, X15

  (1169) 0x436048 LDR	X14, [SP, #32]

  (1169) 0x43604c ADD	X1, X14, X15

  (1169) 0x436050 HINT	#0

  (1169) 0x436054 HINT	#0

  (1169) 0x436058 HINT	#0

  (1169) 0x43605c HINT	#0

    (1176) 0x436060 LDR	X15, [X28]

    (1176) 0x436064 UBFM	X18, X9, #61, #60

    (1176) 0x436068 ADD	X9, X9, #2

    (1176) 0x43606c CMP	X13, X9

    (1176) 0x436070 LDR	X15, [X2, X15,LSL #3]

    (1176) 0x436074 LDR	X15, [X15, X18]

    (1176) 0x436078 STR	X16, [X21, X15,LSL #3]

    (1176) 0x43607c STP	XZR, XZR, [X1, #1016]

    (1176) 0x436080 STUR	X15, [X0, #504]

    (1176) 0x436084 ADD	X1, X1, #16

    (1176) 0x436088 LDR	X15, [X28]

    (1176) 0x43608c LDR	X15, [X2, X15,LSL #3]

    (1176) 0x436090 ADD	X15, X15, X18

    (1176) 0x436094 ADD	X18, X16, #1

    (1176) 0x436098 ADD	X16, X16, #2

    (1176) 0x43609c LDR	X15, [X15, #8]

    (1176) 0x4360a0 STR	X18, [X21, X15,LSL #3]

    (1176) 0x4360a4 STR	X15, [X0], #16

    (1176) 0x4360a8 B.NE	436060

  (1169) 0x4360ac LDUR	X9, [X29, #384]

  (1169) 0x4360b0 LDUR	X14, [X29, #464]

  (1169) 0x4360b4 LDR	X9, [X9, X11,LSL #3]

  (1169) 0x4360b8 LDR	X0, [X14, X12,LSL #3]

  (1169) 0x4360bc LDR	X16, [X14, X11,LSL #3]

  (1169) 0x4360c0 ADD	X13, X0, X9

  (1169) 0x4360c4 SUB	X13, X13, X16

  (1169) 0x4360c8 CMP	X9, X13

  (1169) 0x4360cc B.GE	43616c

  (1169) 0x4360d0 SUB	W18, W0, W16

  (1169) 0x4360d4 ADD	X15, X16, #1

  (1169) 0x4360d8 TBZ	W18, #0, 436100

  (1169) 0x4360dc LDR	X18, [X28]

  (1169) 0x4360e0 LDR	X14, [SP, #48]

  (1169) 0x4360e4 STR	XZR, [X10, X16,LSL #3]

  (1169) 0x4360e8 LDR	X18, [X3, X18,LSL #3]

  (1169) 0x4360ec LDR	X18, [X18, X9,LSL #3]

  (1169) 0x4360f0 ADD	X9, X9, #1

  (1169) 0x4360f4 STR	X16, [X22, X18,LSL #3]

  (1169) 0x4360f8 STR	X18, [X14, X16,LSL #3]

  (1169) 0x4360fc ORR	X16, XZR, X15

  (1169) 0x436100 CMP	X0, X15

  (1169) 0x436104 B.EQ	43616c

  (1169) 0x436108 LDR	X14, [SP, #24]

  (1169) 0x43610c UBFM	X15, X16, #61, #60

  (1169) 0x436110 ADD	X0, X14, X15

  (1169) 0x436114 LDR	X14, [SP, #16]

  (1169) 0x436118 ADD	X1, X14, X15

  (1169) 0x43611c HINT	#0

    (1175) 0x436120 LDR	X15, [X28]

    (1175) 0x436124 UBFM	X18, X9, #61, #60

    (1175) 0x436128 ADD	X9, X9, #2

    (1175) 0x43612c CMP	X13, X9

    (1175) 0x436130 LDR	X15, [X3, X15,LSL #3]

    (1175) 0x436134 LDR	X15, [X15, X18]

    (1175) 0x436138 STR	X16, [X22, X15,LSL #3]

    (1175) 0x43613c STP	XZR, XZR, [X1, #1016]

    (1175) 0x436140 STUR	X15, [X0, #504]

    (1175) 0x436144 ADD	X1, X1, #16

    (1175) 0x436148 LDR	X15, [X28]

    (1175) 0x43614c LDR	X15, [X3, X15,LSL #3]

    (1175) 0x436150 ADD	X15, X15, X18

    (1175) 0x436154 ADD	X18, X16, #1

    (1175) 0x436158 ADD	X16, X16, #2

    (1175) 0x43615c LDR	X15, [X15, #8]

    (1175) 0x436160 STR	X18, [X22, X15,LSL #3]

    (1175) 0x436164 STR	X15, [X0], #16

    (1175) 0x436168 B.NE	436120

  (1169) 0x43616c LDR	X9, [X5, X11,LSL #3]

  (1169) 0x436170 LDR	X13, [X5, X12,LSL #3]

  (1169) 0x436174 B	436184

0x436178 HINT	#0

0x43617c HINT	#0

    (1174) 0x436180 ADD	X9, X9, #1

    (1174) 0x436184 CMP	X9, X13

    (1174) 0x436188 B.GE	4361c0

    (1174) 0x43618c LDR	X15, [X6, X9,LSL #3]

    (1174) 0x436190 LDR	X18, [X28]

    (1174) 0x436194 LDR	X16, [X23, X15,LSL #3]

    (1174) 0x436198 SUB	X18, X18, #1

    (1174) 0x43619c CMP	X16, X18

    (1174) 0x4361a0 B.NE	436180

    (1174) 0x4361a4 STR	X11, [X19, X15,LSL #3]

    (1174) 0x4361a8 LDR	X13, [X5, X12,LSL #3]

    (1174) 0x4361ac B	436180

0x4361b0 HINT	#0

0x4361b4 HINT	#0

0x4361b8 HINT	#0

0x4361bc HINT	#0

  (1169) 0x4361c0 LDR	X9, [X24, X11,LSL #3]

  (1169) 0x4361c4 LDR	X13, [X24, X12,LSL #3]

  (1169) 0x4361c8 B	4361d0

    (1173) 0x4361cc ADD	X9, X9, #1

    (1173) 0x4361d0 CMP	X9, X13

    (1173) 0x4361d4 B.GE	436200

    (1173) 0x4361d8 LDR	X15, [X25, X9,LSL #3]

    (1173) 0x4361dc LDR	X18, [X28]

    (1173) 0x4361e0 LDR	X16, [X26, X15,LSL #3]

    (1173) 0x4361e4 SUB	X18, X18, #1

    (1173) 0x4361e8 CMP	X16, X18

    (1173) 0x4361ec B.NE	4361cc

    (1173) 0x4361f0 STR	X11, [X20, X15,LSL #3]

    (1173) 0x4361f4 LDR	X13, [X24, X12,LSL #3]

    (1173) 0x4361f8 B	4361cc

0x4361fc HINT	#0

  (1169) 0x436200 LDUR	X9, [X29, #376]

  (1169) 0x436204 MOVI	D2, #0

  (1169) 0x436208 LDR	X13, [X9, X11,LSL #3]

  (1169) 0x43620c LDR	X16, [X9, X12,LSL #3]

  (1169) 0x436210 ADD	X7, X13, #1

  (1169) 0x436214 STP	X13, X27, [X29, #936]

  (1169) 0x436218 CMP	X7, X16

  (1169) 0x43621c B.GE	4364a0

  (1169) 0x436220 LDUR	X13, [X29, #408]

  (1169) 0x436224 LDR	X9, [SP, #72]

  (1169) 0x436228 MOVI	D1, #0

  (1169) 0x43622c MOVI	D2, #0

  (1169) 0x436230 LDR	X6, [X13]

  (1169) 0x436234 LDUR	X13, [X29, #416]

  (1169) 0x436238 LDR	X9, [X9]

  (1169) 0x43623c LDR	X26, [X13]

  (1169) 0x436240 LDP	X15, X13, [SP, #160]

  (1169) 0x436244 LDR	X23, [X13]

  (1169) 0x436248 LDR	X13, [SP, #152]

  (1169) 0x43624c LDR	X17, [X15]

  (1169) 0x436250 LDR	X25, [X13]

  (1169) 0x436254 LDP	X13, X15, [X29, #1000]

  (1169) 0x436258 LDR	X27, [X15]

  (1169) 0x43625c LDR	X13, [X13]

  (1169) 0x436260 ADD	X14, X25, #8

  (1169) 0x436264 ADD	X15, X13, #8

  (1169) 0x436268 STP	X14, X15, [X29, #984]

  (1169) 0x43626c ADD	X14, X27, #8

  (1169) 0x436270 ADD	X15, X17, #8

  (1169) 0x436274 STP	X15, X14, [X29, #952]

  (1169) 0x436278 ORR	X14, XZR, X17

  (1169) 0x43627c LDUR	X17, [X29, #464]

  (1169) 0x436280 LDR	X5, [SP, #64]

  (1169) 0x436284 B	4362ac

    (1170) 0x436288 LDR	D3, [X23, X7,LSL #3]

    (1170) 0x43628c FADD	D1, D1, D3

    (1170) 0x436290 HINT	#0

    (1170) 0x436294 HINT	#0

    (1170) 0x436298 HINT	#0

    (1170) 0x43629c HINT	#0

    (1170) 0x4362a0 ADD	X7, X7, #1

    (1170) 0x4362a4 CMP	X7, X16

    (1170) 0x4362a8 B.EQ	4364c0

    (1170) 0x4362ac LDR	X0, [X5, X7,LSL #3]

    (1170) 0x4362b0 LDR	X15, [X19, X0,LSL #3]

    (1170) 0x4362b4 CMP	X15, X11

    (1170) 0x4362b8 B.NE	4362e8

    (1170) 0x4362bc ADD	X1, X0, #1

    (1170) 0x4362c0 LDR	X24, [X4, X0,LSL #3]

    (1170) 0x4362c4 LDR	X2, [X4, X1,LSL #3]

    (1170) 0x4362c8 CMP	X2, X24

    (1170) 0x4362cc B.LE	4363bc

    (1170) 0x4362d0 SUB	W15, W2, W24

    (1170) 0x4362d4 ADD	X3, X24, #1

    (1170) 0x4362d8 TBNZ	W15, #0, 436310

    (1170) 0x4362dc CMP	X2, X3

    (1170) 0x4362e0 B.NE	436344

    (1170) 0x4362e4 B	4363bc

    (1170) 0x4362e8 LDR	X15, [X9, X0,LSL #3]

    (1170) 0x4362ec CMN	X15, #3

    (1170) 0x4362f0 B.EQ	4362a0

    (1170) 0x4362f4 CMP	X6, #1

    (1170) 0x4362f8 B.EQ	436288

    (1170) 0x4362fc LDR	X15, [X26, X11,LSL #3]

    (1170) 0x436300 LDR	X18, [X26, X0,LSL #3]

    (1170) 0x436304 CMP	X15, X18

    (1170) 0x436308 B.EQ	436288

    (1170) 0x43630c B	4362a0

    (1170) 0x436310 LDR	X15, [X25, X24,LSL #3]

    (1170) 0x436314 LDR	D0, [X23, X7,LSL #3]

    (1170) 0x436318 LDR	D3, [X13, X24,LSL #3]

    (1170) 0x43631c ORR	X24, XZR, X3

    (1170) 0x436320 FMUL	D0, D0, D3

    (1170) 0x436324 LDR	X15, [X21, X15,LSL #3]

    (1170) 0x436328 LDR	D3, [X13, X15,LSL #3]

    (1170) 0x43632c FADD	D2, D2, D0

    (1170) 0x436330 FADD	D1, D1, D0

    (1170) 0x436334 FADD	D3, D0, D3

    (1170) 0x436338 STR	D3, [X13, X15,LSL #3]

    (1170) 0x43633c CMP	X2, X3

    (1170) 0x436340 B.EQ	4363bc

    (1170) 0x436344 LDUR	X18, [X29, #480]

    (1170) 0x436348 UBFM	X15, X24, #61, #60

    (1170) 0x43634c SUB	X2, X2, X24

    (1170) 0x436350 ADD	X3, X18, X15

    (1170) 0x436354 LDUR	X18, [X29, #472]

    (1170) 0x436358 ADD	X4, X18, X15

    (1170) 0x43635c HINT	#0

      (1172) 0x436360 LDUR	X15, [X4, #504]

      (1172) 0x436364 LDR	D0, [X23, X7,LSL #3]

      (1172) 0x436368 LDUR	D3, [X3, #504]

      (1172) 0x43636c SUBS	X2, X2, #2

      (1172) 0x436370 FMUL	D0, D0, D3

      (1172) 0x436374 LDR	X15, [X21, X15,LSL #3]

      (1172) 0x436378 LDR	D3, [X13, X15,LSL #3]

      (1172) 0x43637c FADD	D2, D2, D0

      (1172) 0x436380 FADD	D1, D1, D0

      (1172) 0x436384 FADD	D3, D0, D3

      (1172) 0x436388 STR	D3, [X13, X15,LSL #3]

      (1172) 0x43638c LDR	X15, [X4], #16

      (1172) 0x436390 LDR	D0, [X23, X7,LSL #3]

      (1172) 0x436394 LDR	D3, [X3], #16

      (1172) 0x436398 FMUL	D0, D0, D3

      (1172) 0x43639c LDR	X15, [X21, X15,LSL #3]

      (1172) 0x4363a0 LDR	D3, [X13, X15,LSL #3]

      (1172) 0x4363a4 FADD	D2, D2, D0

      (1172) 0x4363a8 FADD	D1, D1, D0

      (1172) 0x4363ac FADD	D3, D0, D3

      (1172) 0x4363b0 STR	D3, [X13, X15,LSL #3]

      (1172) 0x4363b4 B.NE	436360

    (1170) 0x4363b8 LDUR	X4, [X29, #456]

    (1170) 0x4363bc LDR	X3, [X17, X0,LSL #3]

    (1170) 0x4363c0 LDR	X0, [X17, X1,LSL #3]

    (1170) 0x4363c4 CMP	X0, X3

    (1170) 0x4363c8 B.LE	4362a0

    (1170) 0x4363cc SUB	W15, W0, W3

    (1170) 0x4363d0 ADD	X1, X3, #1

    (1170) 0x4363d4 TBNZ	W15, #0, 4363e4

    (1170) 0x4363d8 CMP	X0, X1

    (1170) 0x4363dc B.EQ	4362a0

    (1170) 0x4363e0 B	436418

    (1170) 0x4363e4 LDR	X15, [X14, X3,LSL #3]

    (1170) 0x4363e8 LDR	D0, [X23, X7,LSL #3]

    (1170) 0x4363ec LDR	D3, [X27, X3,LSL #3]

    (1170) 0x4363f0 ORR	X3, XZR, X1

    (1170) 0x4363f4 FMUL	D0, D0, D3

    (1170) 0x4363f8 LDR	X15, [X22, X15,LSL #3]

    (1170) 0x4363fc LDR	D3, [X27, X15,LSL #3]

    (1170) 0x436400 FADD	D2, D2, D0

    (1170) 0x436404 FADD	D1, D1, D0

    (1170) 0x436408 FADD	D3, D0, D3

    (1170) 0x43640c STR	D3, [X27, X15,LSL #3]

    (1170) 0x436410 CMP	X0, X1

    (1170) 0x436414 B.EQ	4362a0

    (1170) 0x436418 LDUR	X18, [X29, #448]

    (1170) 0x43641c UBFM	X15, X3, #61, #60

    (1170) 0x436420 SUB	X0, X0, X3

    (1170) 0x436424 ADD	X1, X18, X15

    (1170) 0x436428 LDUR	X18, [X29, #440]

    (1170) 0x43642c ADD	X2, X18, X15

    (1170) 0x436430 HINT	#0

    (1170) 0x436434 HINT	#0

    (1170) 0x436438 HINT	#0

    (1170) 0x43643c HINT	#0

      (1171) 0x436440 LDUR	X15, [X2, #504]

      (1171) 0x436444 LDR	D0, [X23, X7,LSL #3]

      (1171) 0x436448 LDUR	D3, [X1, #504]

      (1171) 0x43644c SUBS	X0, X0, #2

      (1171) 0x436450 FMUL	D0, D0, D3

      (1171) 0x436454 LDR	X15, [X22, X15,LSL #3]

      (1171) 0x436458 LDR	D3, [X27, X15,LSL #3]

      (1171) 0x43645c FADD	D2, D2, D0

      (1171) 0x436460 FADD	D1, D1, D0

      (1171) 0x436464 FADD	D3, D0, D3

      (1171) 0x436468 STR	D3, [X27, X15,LSL #3]

      (1171) 0x43646c LDR	X15, [X2], #16

      (1171) 0x436470 LDR	D0, [X23, X7,LSL #3]

      (1171) 0x436474 LDR	D3, [X1], #16

      (1171) 0x436478 FMUL	D0, D0, D3

      (1171) 0x43647c LDR	X15, [X22, X15,LSL #3]

      (1171) 0x436480 LDR	D3, [X27, X15,LSL #3]

      (1171) 0x436484 FADD	D2, D2, D0

      (1171) 0x436488 FADD	D1, D1, D0

      (1171) 0x43648c FADD	D3, D0, D3

      (1171) 0x436490 STR	D3, [X27, X15,LSL #3]

      (1171) 0x436494 B.NE	436440

    (1170) 0x436498 B	4362a0

0x43649c HINT	#0

  (1169) 0x4364a0 MOVI	D1, #0

  (1169) 0x4364a4 LDUR	X13, [X29, #360]

  (1169) 0x4364a8 LDR	X9, [X13, X11,LSL #3]

  (1169) 0x4364ac LDR	X13, [X13, X12,LSL #3]

  (1169) 0x4364b0 CMP	X9, X13

  (1169) 0x4364b4 B.LT	4364e8

  (1169) 0x4364b8 B	436678

0x4364bc HINT	#0

  (1169) 0x4364c0 LDP	X3, X2, [X29, #848]

  (1169) 0x4364c4 LDP	X6, X5, [X29, #832]

  (1169) 0x4364c8 LDP	X24, X23, [SP, #192]

  (1169) 0x4364cc LDP	X26, X25, [SP, #176]

  (1169) 0x4364d0 LDUR	X27, [X29, #432]

  (1169) 0x4364d4 LDUR	X13, [X29, #360]

  (1169) 0x4364d8 LDR	X9, [X13, X11,LSL #3]

  (1169) 0x4364dc LDR	X13, [X13, X12,LSL #3]

  (1169) 0x4364e0 CMP	X9, X13

  (1169) 0x4364e4 B.GE	436678

(1166) 0x4364e8 LDR	X15, [SP, #80]

(1166) 0x4364ec LDR	X1, [X28]

(1166) 0x4364f0 LDR	X16, [X15]

(1166) 0x4364f4 LDR	X15, [SP, #88]

(1166) 0x4364f8 LDR	X6, [X15]

(1166) 0x4364fc LDR	X15, [SP, #136]

(1166) 0x436500 LDR	X7, [X15]

(1166) 0x436504 LDUR	X15, [X29, #408]

(1166) 0x436508 LDR	X23, [X15]

(1166) 0x43650c LDR	X15, [SP, #144]

(1166) 0x436510 LDR	X14, [X15]

(1166) 0x436514 LDUR	X15, [X29, #416]

(1166) 0x436518 STUR	X14, [X29, #480]

(1166) 0x43651c LDR	X14, [X15]

(1166) 0x436520 STUR	X14, [X29, #472]

(1166) 0x436524 LDP	X18, X15, [SP, #112]

(1166) 0x436528 LDR	X27, [X15]

(1166) 0x43652c LDR	X15, [SP, #96]

(1166) 0x436530 LDR	X3, [X18]

(1166) 0x436534 LDR	X18, [SP, #128]

(1166) 0x436538 LDR	X0, [X15]

(1166) 0x43653c LDR	X15, [SP, #104]

(1166) 0x436540 LDR	X2, [X18]

(1166) 0x436544 LDR	X15, [X15]

(1166) 0x436548 ADD	X4, X15, #8

(1166) 0x43654c B	436574

0x436550 HINT	#0

0x436554 HINT	#0

0x436558 HINT	#0

0x43655c HINT	#0

  (1167) 0x436560 LDR	D3, [X27, X9,LSL #3]

  (1167) 0x436564 FADD	D1, D1, D3

  (1167) 0x436568 ADD	X9, X9, #1

  (1167) 0x43656c CMP	X9, X13

  (1167) 0x436570 B.EQ	436660

  (1167) 0x436574 ADD	X15, X6, X9,LSL #3

  (1167) 0x436578 CBZ	X30, 436584

  (1167) 0x43657c LDR	X15, [X15]

  (1167) 0x436580 ADD	X15, X16, X15,LSL #3

  (1167) 0x436584 LDR	X15, [X15]

  (1167) 0x436588 TBNZ	X15, #63, 436620

  (1167) 0x43658c LDR	X18, [X20, X15,LSL #3]

  (1167) 0x436590 CMP	X18, X11

  (1167) 0x436594 B.NE	436620

  (1167) 0x436598 LDR	X18, [X4, X15,LSL #3]

  (1167) 0x43659c CMP	X18, #1

  (1167) 0x4365a0 B.LT	436568

  (1167) 0x4365a4 LDR	X5, [X0, X15,LSL #3]

  (1167) 0x4365a8 ORR	X14, XZR, X20

  (1167) 0x4365ac ORR	X17, XZR, X30

  (1167) 0x4365b0 LDR	X15, [X3, X1,LSL #3]

  (1167) 0x4365b4 ADD	X25, X18, X5

  (1167) 0x4365b8 LDP	X20, X18, [X29, #1000]

  (1167) 0x4365bc LDR	X18, [X18]

  (1167) 0x4365c0 LDR	X30, [X20]

    (1168) 0x4365c4 LDR	X20, [X15, X5,LSL #3]

    (1168) 0x4365c8 LDR	D0, [X27, X9,LSL #3]

    (1168) 0x4365cc LDR	D3, [X2, X5,LSL #3]

    (1168) 0x4365d0 ADD	X5, X5, #1

    (1168) 0x4365d4 ORN	X26, XZR, X20

    (1168) 0x4365d8 ADD	X24, X22, X20,LSL #3

    (1168) 0x4365dc CMP	X20, #0

    (1168) 0x4365e0 ADD	X26, X21, X26,LSL #3

    (1168) 0x4365e4 FMUL	D0, D0, D3

    (1168) 0x4365e8 CSEL	X20, X26, X24, #11

    (1168) 0x4365ec CSEL	X24, X30, X18, #11

    (1168) 0x4365f0 CMP	X5, X25

    (1168) 0x4365f4 LDR	X20, [X20]

    (1168) 0x4365f8 FADD	D2, D2, D0

    (1168) 0x4365fc FADD	D1, D1, D0

    (1168) 0x436600 LDR	D3, [X24, X20,LSL #3]

    (1168) 0x436604 FADD	D3, D0, D3

    (1168) 0x436608 STR	D3, [X24, X20,LSL #3]

    (1168) 0x43660c B.LT	4365c4

  (1167) 0x436610 ORR	X20, XZR, X14

  (1167) 0x436614 ORR	X30, XZR, X17

  (1167) 0x436618 B	436568

0x43661c HINT	#0

  (1167) 0x436620 LDR	X18, [X7, X15,LSL #3]

  (1167) 0x436624 CMN	X18, #3

  (1167) 0x436628 B.EQ	436568

  (1167) 0x43662c CMP	X23, #1

  (1167) 0x436630 B.EQ	436560

  (1167) 0x436634 LDUR	X14, [X29, #480]

  (1167) 0x436638 LDR	X15, [X14, X15,LSL #3]

  (1167) 0x43663c LDUR	X14, [X29, #472]

  (1167) 0x436640 LDR	X18, [X14, X11,LSL #3]

  (1167) 0x436644 CMP	X15, X18

  (1167) 0x436648 B.EQ	436560

  (1167) 0x43664c B	436568

0x436650 HINT	#0

0x436654 HINT	#0

0x436658 HINT	#0

0x43665c HINT	#0

(1166) 0x436660 LDUR	X4, [X29, #456]

(1166) 0x436664 LDP	X3, X2, [X29, #848]

(1166) 0x436668 LDP	X6, X5, [X29, #832]

(1166) 0x43666c LDP	X24, X23, [SP, #192]

(1166) 0x436670 LDP	X26, X25, [SP, #176]

(1166) 0x436674 LDUR	X27, [X29, #432]

  (1169) 0x436678 LDUR	X13, [X29, #424]

  (1169) 0x43667c LDUR	X9, [X29, #352]

  (1169) 0x436680 LDR	D3, [X9, X13,LSL #3]

  (1169) 0x436684 FMUL	D2, D2, D3

  (1169) 0x436688 FCMP	D2, #0

  (1169) 0x43668c B.EQ	436698

  (1169) 0x436690 FNEG	D0, D1

  (1169) 0x436694 FDIV	D0, D0, D2

  (1169) 0x436698 LDR	X13, [X4, X11,LSL #3]

  (1169) 0x43669c LDR	X9, [X4, X12,LSL #3]

  (1169) 0x4366a0 CMP	X9, X13

  (1169) 0x4366a4 B.LE	436734

  (1169) 0x4366a8 SUB	W15, W9, W13

  (1169) 0x4366ac ANDS	X16, X15, #4160

  (1169) 0x4366b0 B.EQ	4366ec

  (1169) 0x4366b4 ORR	X15, XZR, X13

  (1169) 0x4366b8 HINT	#0

  (1169) 0x4366bc HINT	#0

    (1180) 0x4366c0 LDR	D1, [X8, X15,LSL #3]

    (1180) 0x4366c4 SUBS	X16, X16, #1

    (1180) 0x4366c8 FMUL	D1, D0, D1

    (1180) 0x4366cc STR	D1, [X8, X15,LSL #3]

    (1180) 0x4366d0 ADD	X15, X15, #1

    (1180) 0x4366d4 B.NE	4366c0

  (1169) 0x4366d8 ORN	X13, XZR, X13

  (1169) 0x4366dc ADD	X13, X9, X13

  (1169) 0x4366e0 CMP	X13, #3

  (1169) 0x4366e4 B.CS	436700

  (1169) 0x4366e8 B	436734

  (1169) 0x4366ec ORR	X15, XZR, X13

  (1169) 0x4366f0 ORN	X13, XZR, X13

  (1169) 0x4366f4 ADD	X13, X9, X13

  (1169) 0x4366f8 CMP	X13, #3

  (1169) 0x4366fc B.CC	436734

  (1169) 0x436700 LDR	X13, [SP, #8]

  (1169) 0x436704 SUB	X9, X9, X15

  (1169) 0x436708 ADD	X13, X13, X15,LSL #3

    (1179) 0x43670c LDP	D1, D2, [X13, #1008]

    (1179) 0x436710 SUBS	X9, X9, #4

    (1179) 0x436714 FMUL	D2, D0, D2

    (1179) 0x436718 FMUL	D1, D0, D1

    (1179) 0x43671c STP	D1, D2, [X13, #1008]

    (1179) 0x436720 LDP	D1, D2, [X13]

    (1179) 0x436724 FMUL	D2, D0, D2

    (1179) 0x436728 FMUL	D1, D0, D1

    (1179) 0x43672c STP	D1, D2, [X13], #32

    (1179) 0x436730 B.NE	43670c

  (1169) 0x436734 LDUR	X9, [X29, #464]

  (1169) 0x436738 LDR	X11, [X9, X11,LSL #3]

  (1169) 0x43673c LDR	X9, [X9, X12,LSL #3]

  (1169) 0x436740 CMP	X9, X11

  (1169) 0x436744 B.LE	435fc8

  (1169) 0x436748 SUB	W12, W9, W11

  (1169) 0x43674c ANDS	X13, X12, #4160

  (1169) 0x436750 B.EQ	43678c

  (1169) 0x436754 ORR	X12, XZR, X11

  (1169) 0x436758 HINT	#0

  (1169) 0x43675c HINT	#0

    (1178) 0x436760 LDR	D1, [X10, X12,LSL #3]

    (1178) 0x436764 SUBS	X13, X13, #1

    (1178) 0x436768 FMUL	D1, D0, D1

    (1178) 0x43676c STR	D1, [X10, X12,LSL #3]

    (1178) 0x436770 ADD	X12, X12, #1

    (1178) 0x436774 B.NE	436760

  (1169) 0x436778 ORN	X11, XZR, X11

  (1169) 0x43677c ADD	X11, X9, X11

  (1169) 0x436780 CMP	X11, #3

  (1169) 0x436784 B.CC	435fc8

  (1169) 0x436788 B	4367a0

  (1169) 0x43678c ORR	X12, XZR, X11

  (1169) 0x436790 ORN	X11, XZR, X11

  (1169) 0x436794 ADD	X11, X9, X11

  (1169) 0x436798 CMP	X11, #3

  (1169) 0x43679c B.CC	435fc8

  (1169) 0x4367a0 LDR	X11, [SP]

  (1169) 0x4367a4 SUB	X9, X9, X12

  (1169) 0x4367a8 ADD	X11, X11, X12,LSL #3

    (1177) 0x4367ac LDP	D1, D2, [X11, #1008]

    (1177) 0x4367b0 SUBS	X9, X9, #4

    (1177) 0x4367b4 FMUL	D2, D0, D2

    (1177) 0x4367b8 FMUL	D1, D0, D1

    (1177) 0x4367bc STP	D1, D2, [X11, #1008]

    (1177) 0x4367c0 LDP	D1, D2, [X11]

    (1177) 0x4367c4 FMUL	D2, D0, D2

    (1177) 0x4367c8 FMUL	D1, D0, D1

    (1177) 0x4367cc STP	D1, D2, [X11], #32

    (1177) 0x4367d0 B.NE	4367ac

  (1169) 0x4367d4 B	435fc8

0x4367d8 ORR	X0, XZR, X19

0x4367dc BL	4a2670

0x4367e0 ORR	X0, XZR, X20

0x4367e4 BL	4a2670

0x4367e8 ORR	X0, XZR, X21

0x4367ec BL	4a2670

0x4367f0 ORR	X0, XZR, X22

0x4367f4 LDP	X20, X19, [SP, #480]

0x4367f8 LDP	X22, X21, [SP, #464]

0x4367fc LDP	X24, X23, [SP, #448]

0x436800 LDP	X26, X25, [SP, #432]

0x436804 LDP	X28, X27, [SP, #416]

0x436808 LDP	X29, X30, [SP, #400]

0x43680c ADD	SP, SP, #496

0x436810 B	4a2670

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	par_multi_interp.c:1737-1881
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1737,1747-1881.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 22% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 46.00 to 10.00 cycles (4.60x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 46.00 to 4.50 cycles (10.22x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 840 bytes. The binary function is storing 576 bytes.

General properties

nb instructions	225
loop length	900
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

25.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	10.00	10.00	14.00	14.00	14.00	14.00	0.00	0.00	0.00	0.00	46.00	46.00	46.00	25.00	25.00
cycles	10.00	10.00	14.00	14.00	14.00	14.00	0.00	0.00	0.00	0.00	46.00	46.00	46.00	25.00	25.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	25.63
Overall L1	46.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 46.00 cycles. At this rate:

19% of peak load performance is reached (18.26 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.52 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 435ca0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #496	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X7, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X22, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X26, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X24, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X8, X9, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X8, X9, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X8, X9, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X8, X9, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X9, X8, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X8, X9, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X9, X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X8, X9, [X29, #856]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X9, X8, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X8, X9, [X29, #840]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X23, X8, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBZ X0, 435dec <.omp_outlined..22+0x14c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X0, 435df8 <.omp_outlined..22+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X0, 435e04 <.omp_outlined..22+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 435e08 <.omp_outlined..22+0x168>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X0, 435dc8 <.omp_outlined..22+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X0, 435ddc <.omp_outlined..22+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X21, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X0, X8, X9, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 435e54 <.omp_outlined..22+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 435e7c <.omp_outlined..22+0x1dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a4720 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X24, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a4700 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X11, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X24, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SDIV X10, X8, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
MADD X9, X10, X24, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X10, X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X11, X8, X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4367d8 <.omp_outlined..22+0xb38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X10, X14, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X8, X10, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X12, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X13, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X13, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X27, X9, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X13, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X13, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X13, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X13, X12, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X13, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X13, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X13, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X13, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X13, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X13, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X13, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X24, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X13, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X13, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X13, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X11, X13, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X9, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X11, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X9, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X9, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X15, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X30, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X9, X11, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X9, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X9, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X14, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X9, X11, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X11, X8, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X9, X11, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X4, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X3, X2, [X29, #848]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X6, X5, [X29, #832]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 435fd8 <.omp_outlined..22+0x338>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X20, X19, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #496	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a2670 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	par_multi_interp.c:1737-1881
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1737,1747-1881.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 46.00 to 4.50 cycles (10.22x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 840 bytes. The binary function is storing 576 bytes.

General properties

nb instructions	225
loop length	900
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

25.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	10.00	10.00	14.00	14.00	14.00	14.00	0.00	0.00	0.00	0.00	46.00	46.00	46.00	25.00	25.00
cycles	10.00	10.00	14.00	14.00	14.00	14.00	0.00	0.00	0.00	0.00	46.00	46.00	46.00	25.00	25.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	25.63
Overall L1	46.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 46.00 cycles. At this rate:

19% of peak load performance is reached (18.26 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.52 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 435ca0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #496	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #400	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X7, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X22, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X26, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X24, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X29, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X8, X9, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X8, X9, [X29, #920]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X8, X9, [X29, #960]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X8, X9, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X9, X8, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X8, X9, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X9, X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X8, X9, [X29, #856]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X9, X8, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X8, X9, [X29, #840]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X23, X8, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CBZ X0, 435dec <.omp_outlined..22+0x14c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X0, 435df8 <.omp_outlined..22+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X0, 435e04 <.omp_outlined..22+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X21, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 435e08 <.omp_outlined..22+0x168>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X0, 435dc8 <.omp_outlined..22+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X0, 435ddc <.omp_outlined..22+0x13c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X21, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSEL X0, X8, X9, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 435e54 <.omp_outlined..22+0x1b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 435e7c <.omp_outlined..22+0x1dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a4720 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X24, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a4700 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X11, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X24, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SDIV X10, X8, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
MADD X9, X10, X24, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X10, X10, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X11, X8, X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4367d8 <.omp_outlined..22+0xb38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X10, X14, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X8, X10, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X12, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X13, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X13, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X27, X9, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X9, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X13, [X29, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X13, [X29, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X13, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X13, X12, [X29, #896]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X13, [X29, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X13, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X13, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X13, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X13, [X29, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X13, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X13, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X24, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X13, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X13, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X13, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X11, X13, [X29, #880]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X9, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X11, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X9, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X9, [X29, #360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X9, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X15, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X30, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X9, X11, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X9, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X9, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X14, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X9, X11, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X11, X8, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X9, X11, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X4, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X3, X2, [X29, #848]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X6, X5, [X29, #832]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 435fd8 <.omp_outlined..22+0x338>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X20, X19, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #496	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a2670 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼.omp_outlined..22#0x435ca0–	4.45	1.68
○Loop 1182 - par_multi_interp.c:1760-1761 - exec	3.33	1.09
▼Loop 1166 - par_multi_interp.c:1774-1876 - exec–	0	0
▼Loop 1169 - par_multi_interp.c:1774-1876 - exec–	0.15	0.05
▼Loop 1170 - par_multi_interp.c:1811-1837 - exec–	0.61	0.2
○Loop 1172 - par_multi_interp.c:1816-1822 - exec	0.04	0.01
○Loop 1171 - par_multi_interp.c:1824-1830 - exec	0	0
○Loop 1174 - par_multi_interp.c:1799-1803 - exec	0.29	0.1
○Loop 1176 - par_multi_interp.c:1782-1787 - exec	0.02	0.01
○Loop 1177 - par_multi_interp.c:1875-1876 - exec	0	0
○Loop 1180 - par_multi_interp.c:1873-1874 - exec	0	0.01
○Loop 1175 - par_multi_interp.c:1792-1797 - exec	0	0
○Loop 1173 - par_multi_interp.c:1805-1809 - exec	0	0.01
○Loop 1178 - par_multi_interp.c:1875-1876 - exec	0	0
○Loop 1179 - par_multi_interp.c:1873-1874 - exec	0	0.01
▼Loop 1167 - par_multi_interp.c:1840-1867 - exec–	0	0
○Loop 1168 - par_multi_interp.c:1851-1860 - exec	0	0
○Loop 1181 - par_multi_interp.c:1762-1763 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code