OV - exec - Function .omp_outlined..20#0x465590

	Function: .omp_outlined..20#0x465590	Module: exec	Source: par_strength.c:1668-2230 [...]	Coverage: 1.67%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 1668 - 2230

--------------------------------------------------------------------------------

1668: #pragma omp parallel private(i1,i2,i3,jj1,jj2,index)

1669: #endif

1670:    {

1671:       HYPRE_Int my_thread_num = hypre_GetThreadNum();

1672:

1673:       HYPRE_Int i1_begin, i1_end;

1674:       hypre_GetSimpleThreadPartition(&i1_begin, &i1_end, num_cols_diag_S);

1675:

1676:       HYPRE_Int *C_temp_diag_j = NULL, *C_temp_offd_j = NULL;

1677:       HYPRE_Int *C_temp_diag_data = NULL, *C_temp_offd_data = NULL;

1678:

1679:       if (num_paths > 1)

1680:       {

1681:          C_temp_diag_j = C_temp_diag_j_array + num_coarse*my_thread_num;

1682:          C_temp_offd_j = C_temp_offd_j_array + num_cols_offd_C*my_thread_num;

1683:

1684:          C_temp_diag_data = C_temp_diag_data_array + num_coarse*my_thread_num;

1685:          C_temp_offd_data = C_temp_offd_data_array + num_cols_offd_C*my_thread_num;

1686:       }

1687:

1688:       HYPRE_Int *S_marker = NULL, *S_marker_offd = NULL;

1689:       if (num_coarse) S_marker = S_marker_array + num_coarse*my_thread_num;

1690:       if (num_cols_offd_C) S_marker_offd = S_marker_offd_array + num_cols_offd_C*my_thread_num;

1691:       for (i1 = 0; i1 < num_coarse; i1++)

1692:       {

1693:          S_marker[i1] = -1;

1694:       }

1695:       for (i1 = 0; i1 < num_cols_offd_C; i1++)

1696:       {

1697:          S_marker_offd[i1] = -1;

[...]

1705:       HYPRE_Int num_nonzeros_diag = 0;

1706:       HYPRE_Int num_nonzeros_offd = 0;

1707:

1708:       HYPRE_Int ic_begin = num_coarse_prefix_sum[my_thread_num];

1709:       HYPRE_Int ic_end = num_coarse_prefix_sum[my_thread_num + 1];

1710:       HYPRE_Int ic;

1711:

1712:       if (num_paths == 1)

1713:       {

1714:          for (ic = ic_begin; ic < ic_end; ic++)

[...]

1720:              HYPRE_Int i1 = coarse_to_fine[ic];

1721:

1722:              HYPRE_Int jj_row_begin_diag = num_nonzeros_diag;

1723:              HYPRE_Int jj_row_begin_offd = num_nonzeros_offd;

1724:

1725:              C_diag_i[ic] = num_nonzeros_diag;

1726:              if (num_cols_offd_C)

1727:              {

1728:                 C_offd_i[ic] = num_nonzeros_offd;

1729:              }

1730:

1731:              for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++)

1732:              {

1733:                  i2 = S_diag_j[jj1];

1734:                  if (CF_marker[i2] > 0)

1735:                  {

1736:                     index = fine_to_coarse[i2];

1737:                     if (S_marker[index] < jj_row_begin_diag)

1738:                     {

1739:                        S_marker[index] = num_nonzeros_diag;

1740:                        num_nonzeros_diag++;

1741:                     }

1742:                  }

1743:                  for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++)

1744:                  {

1745:                     i3 = S_diag_j[jj2];

1746:                     if (CF_marker[i3] > 0)

1747:                     {

1748:                        index = fine_to_coarse[i3];

1749:                        if (index != ic && S_marker[index] < jj_row_begin_diag)

1750:                        {

1751:                           S_marker[index] = num_nonzeros_diag;

1752:                           num_nonzeros_diag++;

1753:                        }

1754:                     }

1755:                  }

1756:                  for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++)

1757:                  {

1758:                     i3 = S_offd_j[jj2];

1759:                     if (CF_marker_offd[i3] > 0)

1760:                     {

1761:                        index = map_S_to_C[i3];

1762:                        if (S_marker_offd[index] < jj_row_begin_offd)

1763:                        {

1764:                           S_marker_offd[index] = num_nonzeros_offd;

1765:                           num_nonzeros_offd++;

1766:                        }

1767:                     }

1768:                  }

1769:              }

1770:              for (jj1 = S_offd_i[i1]; jj1 < S_offd_i[i1+1]; jj1++)

1771:              {

1772:                  i2 = S_offd_j[jj1];

1773:                  if (CF_marker_offd[i2] > 0)

1774:                  {

1775:                     index = map_S_to_C[i2];

1776:                     if (S_marker_offd[index] < jj_row_begin_offd)

1777:                     {

1778:                        S_marker_offd[index] = num_nonzeros_offd;

1779:                        num_nonzeros_offd++;

1780:                     }

1781:                  }

1782:                  for (jj2 = S_ext_diag_i[i2]; jj2 < S_ext_diag_i[i2+1]; jj2++)

1783:                  {

1784:                     i3 = S_ext_diag_j[jj2];

1785:                     if (i3 != ic && S_marker[i3] < jj_row_begin_diag)

1786:                     {

1787:                        S_marker[i3] = num_nonzeros_diag;

1788:                        num_nonzeros_diag++;

1789:                     }

1790:                  }

1791:                  for (jj2 = S_ext_offd_i[i2]; jj2 < S_ext_offd_i[i2+1]; jj2++)

1792:                  {

1793:                     i3 = S_ext_offd_j[jj2];

1794:                     if (S_marker_offd[i3] < jj_row_begin_offd)

1795:                     {

1796:                        S_marker_offd[i3] = num_nonzeros_offd;

1797:                        num_nonzeros_offd++;

[...]

1806:          for (ic = ic_begin; ic < ic_end; ic++)

[...]

1812:              HYPRE_Int i1 = coarse_to_fine[ic];

1813:

1814:              HYPRE_Int jj_row_begin_diag = jj_count_diag;

1815:              HYPRE_Int jj_row_begin_offd = jj_count_offd;

1816:

1817:              C_diag_i[ic] = num_nonzeros_diag;

1818:              if (num_cols_offd_C)

1819:              {

1820:                 C_offd_i[ic] = num_nonzeros_offd;

1821:              }

1822:

1823:              for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++)

1824:              {

1825:                  i2 = S_diag_j[jj1];

1826:                  if (CF_marker[i2] > 0)

1827:                  {

1828:                     index = fine_to_coarse[i2];

1829:                     if (S_marker[index] < jj_row_begin_diag)

1830:                     {

1831:                        S_marker[index] = jj_count_diag;

1832:                        C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 2;

1833:                        jj_count_diag++;

1834:                     }

1835:                     else

1836:                     {

1837:                        C_temp_diag_data[S_marker[index] - jj_row_begin_diag] += 2;

1838:                     }

1839:                  }

1840:                  for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++)

1841:                  {

1842:                     i3 = S_diag_j[jj2];

1843:                     if (CF_marker[i3] > 0 && fine_to_coarse[i3] != ic)

1844:                     {

1845:                        index = fine_to_coarse[i3];

1846:                        if (S_marker[index] < jj_row_begin_diag)

1847:                        {

1848:                           S_marker[index] = jj_count_diag;

1849:                           C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 1;

1850:                           jj_count_diag++;

1851:                        }

1852:                        else

1853:                        {

1854:                           C_temp_diag_data[S_marker[index] - jj_row_begin_diag]++;

1855:                        }

1856:                     }

1857:                  }

1858:                  for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++)

1859:                  {

1860:                     i3 = S_offd_j[jj2];

1861:                     if (CF_marker_offd[i3] > 0)

1862:                     {

1863:                        index = map_S_to_C[i3];

1864:                        if (S_marker_offd[index] < jj_row_begin_offd)

1865:                        {

1866:                           S_marker_offd[index] = jj_count_offd;

1867:                           C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 1;

1868:                           jj_count_offd++;

1869:                        }

1870:                        else

1871:                        {

1872:                           C_temp_offd_data[S_marker_offd[index] - jj_row_begin_offd]++;

1873:                        }

1874:                     }

1875:                  }

1876:              }

1877:              for (jj1 = S_offd_i[i1]; jj1 < S_offd_i[i1+1]; jj1++)

1878:              {

1879:                  i2 = S_offd_j[jj1];

1880:                  if (CF_marker_offd[i2] > 0)

1881:                  {

1882:                     index = map_S_to_C[i2];

1883:                     if (S_marker_offd[index] < jj_row_begin_offd)

1884:                     {

1885:                        S_marker_offd[index] = jj_count_offd;

1886:                        C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 2;

1887:                        jj_count_offd++;

1888:                     }

1889:                     else

1890:                     {

1891:                        C_temp_offd_data[S_marker_offd[index] - jj_row_begin_offd] += 2;

1892:                     }

1893:                  }

1894:                  for (jj2 = S_ext_diag_i[i2]; jj2 < S_ext_diag_i[i2+1]; jj2++)

1895:                  {

1896:                     i3 = S_ext_diag_j[jj2];

1897:                     if (i3 != ic)

1898:                     {

1899:                        if (S_marker[i3] < jj_row_begin_diag)

1900:                        {

1901:                           S_marker[i3] = jj_count_diag;

1902:                           C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 1;

1903:                           jj_count_diag++;

1904:                        }

1905:                        else

1906:                        {

1907:                           C_temp_diag_data[S_marker[i3] - jj_row_begin_diag]++;

1908:                        }

1909:                     }

1910:                  }

1911:                  for (jj2 = S_ext_offd_i[i2]; jj2 < S_ext_offd_i[i2+1]; jj2++)

1912:                  {

1913:                     i3 = S_ext_offd_j[jj2];

1914:                     if (S_marker_offd[i3] < jj_row_begin_offd)

1915:                     {

1916:                        S_marker_offd[i3] = jj_count_offd;

1917:                        C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 1;

1918:                        jj_count_offd++;

1919:                     }

1920:                     else

1921:                     {

1922:                        C_temp_offd_data[S_marker_offd[i3] - jj_row_begin_offd]++;

1923:                     }

1924:                  }

1925:              }

1926:

1927:              for (jj1 = jj_row_begin_diag; jj1 < jj_count_diag; jj1++)

1928:              {

1929:                  if (C_temp_diag_data[jj1 - jj_row_begin_diag] >= num_paths)

1930:                  {

1931:                     ++num_nonzeros_diag;

1932:                  }

1933:                  C_temp_diag_data[jj1 - jj_row_begin_diag] = 0;

1934:              }

1935:              for (jj1 = jj_row_begin_offd; jj1 < jj_count_offd; jj1++)

1936:              {

1937:                  if (C_temp_offd_data[jj1 - jj_row_begin_offd] >= num_paths)

1938:                  {

1939:                     ++num_nonzeros_offd;

1940:                  }

1941:                  C_temp_offd_data[jj1 - jj_row_begin_offd] = 0;

1942:              }

1943:          } /* for each row */

1944:       } /* num_paths > 1 */

1945:

1946:       hypre_prefix_sum_pair(

1947:          &num_nonzeros_diag, &C_diag_i[num_coarse],

1948:          &num_nonzeros_offd, &C_offd_i[num_coarse],

1949:          prefix_sum_workspace);

1950:

1951:       for (i1 = 0; i1 < num_coarse; i1++)

1952:       {

1953:          S_marker[i1] = -1;

1954:       }

1955:       for (i1 = 0; i1 < num_cols_offd_C; i1++)

1956:       {

1957:          S_marker_offd[i1] = -1;

1958:       }

1959:

1960: #ifdef HYPRE_USING_OPENMP

1961: #pragma omp barrier

1962: #pragma omp master

1963: #endif

1964:       {

1965:          if (C_diag_i[num_coarse])

1966:          {

1967:             C_diag_j = hypre_TAlloc(HYPRE_Int, C_diag_i[num_coarse]);

1968:          }

1969:          if (C_offd_i[num_coarse])

1970:          {

1971:             C_offd_j = hypre_TAlloc(HYPRE_Int, C_offd_i[num_coarse]);

1972:          }

1973:       }

1974: #ifdef HYPRE_USING_OPENMP

1975: #pragma omp barrier

1976: #endif

1977:

1978:       for (ic = ic_begin; ic < ic_end - 1; ic++)

1979:       {

1980:          if (C_diag_i[ic+1] == C_diag_i[ic] && C_offd_i[ic+1] == C_offd_i[ic])

1981:             CF_marker[coarse_to_fine[ic]] = 2;

1982:

1983:          C_diag_i[ic] += num_nonzeros_diag;

1984:          C_offd_i[ic] += num_nonzeros_offd;

1985:       }

1986:       if (ic_begin < ic_end)

1987:       {

1988:          C_diag_i[ic] += num_nonzeros_diag;

1989:          C_offd_i[ic] += num_nonzeros_offd;

1990:

1991:          HYPRE_Int next_C_diag_i = prefix_sum_workspace[2*(my_thread_num + 1)];

1992:          HYPRE_Int next_C_offd_i = prefix_sum_workspace[2*(my_thread_num + 1) + 1];

1993:

1994:          if (next_C_diag_i == C_diag_i[ic] && next_C_offd_i == C_offd_i[ic])

1995:             CF_marker[coarse_to_fine[ic]] = 2;

1996:       }

1997:

1998:       if (num_paths == 1)

1999:       {

2000:          for (ic = ic_begin; ic < ic_end; ic++)

[...]

2006:              HYPRE_Int i1 = coarse_to_fine[ic];

2007:

2008:              HYPRE_Int jj_row_begin_diag = num_nonzeros_diag;

2009:              HYPRE_Int jj_row_begin_offd = num_nonzeros_offd;

2010:

2011:              for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++)

2012:              {

2013:                  i2 = S_diag_j[jj1];

2014:                  if (CF_marker[i2] > 0)

2015:                  {

2016:                     index = fine_to_coarse[i2];

2017:                     if (S_marker[index] < jj_row_begin_diag)

2018:                     {

2019:                        S_marker[index] = num_nonzeros_diag;

2020:                        C_diag_j[num_nonzeros_diag] = index;

2021:                        num_nonzeros_diag++;

2022:                     }

2023:                  }

2024:                  for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++)

2025:                  {

2026:                     i3 = S_diag_j[jj2];

2027:                     if (CF_marker[i3] > 0)

2028:                     {

2029:                        index = fine_to_coarse[i3];

2030:                        if (index != ic && S_marker[index] < jj_row_begin_diag)

2031:                        {

2032:                           S_marker[index] = num_nonzeros_diag;

2033:                           C_diag_j[num_nonzeros_diag] = index;

2034:                           num_nonzeros_diag++;

2035:                        }

2036:                     }

2037:                  }

2038:                  for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++)

2039:                  {

2040:                     i3 = S_offd_j[jj2];

2041:                     if (CF_marker_offd[i3] > 0)

2042:                     {

2043:                        index = map_S_to_C[i3];

2044:                        if (S_marker_offd[index] < jj_row_begin_offd)

2045:                        {

2046:                           S_marker_offd[index] = num_nonzeros_offd;

2047:                           C_offd_j[num_nonzeros_offd] = index;

2048:                           num_nonzeros_offd++;

2049:                        }

2050:                     }

2051:                  }

2052:              }

2053:              for (jj1 = S_offd_i[i1]; jj1 < S_offd_i[i1+1]; jj1++)

2054:              {

2055:                  i2 = S_offd_j[jj1];

2056:                  if (CF_marker_offd[i2] > 0)

2057:                  {

2058:                     index = map_S_to_C[i2];

2059:                     if (S_marker_offd[index] < jj_row_begin_offd)

2060:                     {

2061:                        S_marker_offd[index] = num_nonzeros_offd;

2062:                        C_offd_j[num_nonzeros_offd] = index;

2063:                        num_nonzeros_offd++;

2064:                     }

2065:                  }

2066:                  for (jj2 = S_ext_diag_i[i2]; jj2 < S_ext_diag_i[i2+1]; jj2++)

2067:                  {

2068:                     i3 = S_ext_diag_j[jj2];

2069:                     if (i3 != ic && S_marker[i3] < jj_row_begin_diag)

2070:                     {

2071:                        S_marker[i3] = num_nonzeros_diag;

2072:                        C_diag_j[num_nonzeros_diag] = i3;

2073:                        num_nonzeros_diag++;

2074:                     }

2075:                  }

2076:                  for (jj2 = S_ext_offd_i[i2]; jj2 < S_ext_offd_i[i2+1]; jj2++)

2077:                  {

2078:                     i3 = S_ext_offd_j[jj2];

2079:                     if (S_marker_offd[i3] < jj_row_begin_offd)

2080:                     {

2081:                        S_marker_offd[i3] = num_nonzeros_offd;

2082:                        C_offd_j[num_nonzeros_offd] = i3;

2083:                        num_nonzeros_offd++;

[...]

2093:          jj_count_offd = num_nonzeros_offd;

2094:

2095:          for (ic = ic_begin; ic < ic_end; ic++)

[...]

2101:              HYPRE_Int i1 = coarse_to_fine[ic];

2102:

2103:              HYPRE_Int jj_row_begin_diag = jj_count_diag;

2104:              HYPRE_Int jj_row_begin_offd = jj_count_offd;

2105:

2106:              for (jj1 = S_diag_i[i1]; jj1 < S_diag_i[i1+1]; jj1++)

2107:              {

2108:                  i2 = S_diag_j[jj1];

2109:                  if (CF_marker[i2] > 0)

2110:                  {

2111:                     index = fine_to_coarse[i2];

2112:                     if (S_marker[index] < jj_row_begin_diag)

2113:                     {

2114:                        S_marker[index] = jj_count_diag;

2115:                        C_temp_diag_j[jj_count_diag - jj_row_begin_diag] = index;

2116:                        C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 2;

2117:                        jj_count_diag++;

2118:                     }

2119:                     else

2120:                     {

2121:                        C_temp_diag_data[S_marker[index] - jj_row_begin_diag] += 2;

2122:                     }

2123:                  }

2124:                  for (jj2 = S_diag_i[i2]; jj2 < S_diag_i[i2+1]; jj2++)

2125:                  {

2126:                     i3 = S_diag_j[jj2];

2127:                     if (CF_marker[i3] > 0 && fine_to_coarse[i3] != ic)

2128:                     {

2129:                        index = fine_to_coarse[i3];

2130:                        if (S_marker[index] < jj_row_begin_diag)

2131:                        {

2132:                           S_marker[index] = jj_count_diag;

2133:                           C_temp_diag_j[jj_count_diag - jj_row_begin_diag] = index;

2134:                           C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 1;

2135:                           jj_count_diag++;

2136:                        }

2137:                        else

2138:                        {

2139:                           C_temp_diag_data[S_marker[index] - jj_row_begin_diag]++;

2140:                        }

2141:                     }

2142:                  }

2143:                  for (jj2 = S_offd_i[i2]; jj2 < S_offd_i[i2+1]; jj2++)

2144:                  {

2145:                     i3 = S_offd_j[jj2];

2146:                     if (CF_marker_offd[i3] > 0)

2147:                     {

2148:                        index = map_S_to_C[i3];

2149:                        if (S_marker_offd[index] < jj_row_begin_offd)

2150:                        {

2151:                           S_marker_offd[index] = jj_count_offd;

2152:                           C_temp_offd_j[jj_count_offd - jj_row_begin_offd] = index;

2153:                           C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 1;

2154:                           jj_count_offd++;

2155:                        }

2156:                        else

2157:                        {

2158:                           C_temp_offd_data[S_marker_offd[index] - jj_row_begin_offd]++;

2159:                        }

2160:                     }

2161:                  }

2162:              }

2163:              for (jj1 = S_offd_i[i1]; jj1 < S_offd_i[i1+1]; jj1++)

2164:              {

2165:                  i2 = S_offd_j[jj1];

2166:                  if (CF_marker_offd[i2] > 0)

2167:                  {

2168:                     index = map_S_to_C[i2];

2169:                     if (S_marker_offd[index] < jj_row_begin_offd)

2170:                     {

2171:                        S_marker_offd[index] = jj_count_offd;

2172:                        C_temp_offd_j[jj_count_offd - jj_row_begin_offd] = index;

2173:                        C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 2;

2174:                        jj_count_offd++;

2175:                     }

2176:                     else

2177:                     {

2178:                        C_temp_offd_data[S_marker_offd[index] - jj_row_begin_offd] += 2;

2179:                     }

2180:                  }

2181:                  for (jj2 = S_ext_diag_i[i2]; jj2 < S_ext_diag_i[i2+1]; jj2++)

2182:                  {

2183:                     i3 = S_ext_diag_j[jj2];

2184:                     if (i3 != ic)

2185:                     {

2186:                        if (S_marker[i3] < jj_row_begin_diag)

2187:                        {

2188:                           S_marker[i3] = jj_count_diag;

2189:                           C_temp_diag_j[jj_count_diag - jj_row_begin_diag] = i3;

2190:                           C_temp_diag_data[jj_count_diag - jj_row_begin_diag] = 1;

2191:                           jj_count_diag++;

2192:                        }

2193:                        else

2194:                        {

2195:                           C_temp_diag_data[S_marker[i3] - jj_row_begin_diag]++;

2196:                        }

2197:                     }

2198:                  }

2199:                  for (jj2 = S_ext_offd_i[i2]; jj2 < S_ext_offd_i[i2+1]; jj2++)

2200:                  {

2201:                     i3 = S_ext_offd_j[jj2];

2202:                     if (S_marker_offd[i3] < jj_row_begin_offd)

2203:                     {

2204:                        S_marker_offd[i3] = jj_count_offd;

2205:                        C_temp_offd_j[jj_count_offd - jj_row_begin_offd] = i3;

2206:                        C_temp_offd_data[jj_count_offd - jj_row_begin_offd] = 1;

2207:                        jj_count_offd++;

2208:                     }

2209:                     else

2210:                     {

2211:                        C_temp_offd_data[S_marker_offd[i3] - jj_row_begin_offd]++;

2212:                     }

2213:                  }

2214:              }

2215:

2216:              for (jj1 = jj_row_begin_diag; jj1 < jj_count_diag; jj1++)

2217:              {

2218:                  if (C_temp_diag_data[jj1 - jj_row_begin_diag] >= num_paths)

2219:                  {

2220:                     C_diag_j[num_nonzeros_diag++] = C_temp_diag_j[jj1 - jj_row_begin_diag];

2221:                  }

2222:                  C_temp_diag_data[jj1 - jj_row_begin_diag] = 0;

2223:              }

2224:              for (jj1 = jj_row_begin_offd; jj1 < jj_count_offd; jj1++)

2225:              {

2226:                  if (C_temp_offd_data[jj1 - jj_row_begin_offd] >= num_paths)

2227:                  {

2228:                     C_offd_j[num_nonzeros_offd++] = C_temp_offd_j[jj1 - jj_row_begin_offd];

2229:                  }

2230:                  C_temp_offd_data[jj1 - jj_row_begin_offd] = 0;

0x465590 SUB	SP, SP, #384

0x465594 STP	X29, X30, [SP, #288]

0x465598 STP	X28, X27, [SP, #304]

0x46559c STP	X26, X25, [SP, #320]

0x4655a0 STP	X24, X23, [SP, #336]

0x4655a4 STP	X22, X21, [SP, #352]

0x4655a8 STP	X20, X19, [SP, #368]

0x4655ac ADD	X29, SP, #288

0x4655b0 LDP	X8, X9, [X29, #112]

0x4655b4 ORR	X22, XZR, X7

0x4655b8 ORR	X24, XZR, X6

0x4655bc STR	X0, [SP, #16]

0x4655c0 STP	X8, X9, [X29, #968]

0x4655c4 ORR	X28, XZR, X5

0x4655c8 ORR	X25, XZR, X4

0x4655cc ORR	X19, XZR, X3

0x4655d0 ORR	X26, XZR, X2

0x4655d4 BL	4a4720

0x4655d8 LDR	X2, [X26]

0x4655dc ORR	X27, XZR, X0

0x4655e0 SUB	X0, X29, #16

0x4655e4 SUB	X1, X29, #24

0x4655e8 BL	4a4740

0x4655ec LDR	X8, [X19]

0x4655f0 CMP	X8, #1

0x4655f4 B.LE	465638

0x4655f8 LDR	X10, [X28]

0x4655fc LDR	X9, [X25]

0x465600 LDP	X13, X8, [X29, #96]

0x465604 MADD	X11, X10, X27, XZR

0x465608 LDR	X15, [X24]

0x46560c LDR	X13, [X13]

0x465610 LDR	X8, [X8]

0x465614 UBFM	X14, X11, #61, #60

0x465618 ADD	X26, X9, X14

0x46561c LDR	X9, [X22]

0x465620 ADD	X20, X13, X14

0x465624 MADD	X12, X9, X27, XZR

0x465628 UBFM	X16, X12, #61, #60

0x46562c ADD	X23, X15, X16

0x465630 ADD	X21, X8, X16

0x465634 B	465658

0x465638 LDR	X10, [X28]

0x46563c LDR	X9, [X22]

0x465640 ORR	X21, XZR, XZR

0x465644 ORR	X20, XZR, XZR

0x465648 ORR	X23, XZR, XZR

0x46564c ORR	X26, XZR, XZR

0x465650 MADD	X11, X10, X27, XZR

0x465654 MADD	X12, X9, X27, XZR

0x465658 LDUR	X13, [X29, #456]

0x46565c CMP	X10, #0

0x465660 LDR	X8, [X29, #128]

0x465664 LDR	X13, [X13]

0x465668 ADD	X11, X13, X11,LSL #3

0x46566c CSEL	X24, XZR, X11, #0

0x465670 LDUR	X11, [X29, #464]

0x465674 CMP	X9, #0

0x465678 LDR	X11, [X11]

0x46567c ADD	X11, X11, X12,LSL #3

0x465680 CSEL	X25, XZR, X11, #0

0x465684 CMP	X10, #1

0x465688 B.LT	4656b8

0x46568c ORR	X9, XZR, XZR

0x465690 MOVN	X10, #0

0x465694 HINT	#0

0x465698 HINT	#0

0x46569c HINT	#0

(1096) 0x4656a0 STR	X10, [X24, X9,LSL #3]

(1096) 0x4656a4 ADD	X9, X9, #1

(1096) 0x4656a8 LDR	X11, [X28]

(1096) 0x4656ac CMP	X9, X11

(1096) 0x4656b0 B.LT	4656a0

0x4656b4 LDR	X9, [X22]

0x4656b8 LDR	X10, [X29, #256]

0x4656bc LDR	X11, [X29, #208]

0x4656c0 CMP	X9, #1

0x4656c4 LDR	X9, [X29, #144]

0x4656c8 STUR	X19, [X29, #424]

0x4656cc STR	X10, [SP, #80]

0x4656d0 LDR	X10, [X29, #248]

0x4656d4 STR	X9, [SP, #112]

0x4656d8 LDR	X9, [X29, #136]

0x4656dc STUR	X10, [X29, #392]

0x4656e0 LDR	X10, [X29, #240]

0x4656e4 STR	X9, [SP, #96]

0x4656e8 STR	X10, [SP, #56]

0x4656ec LDR	X10, [X29, #232]

0x4656f0 STUR	X10, [X29, #384]

0x4656f4 LDR	X10, [X29, #224]

0x4656f8 STR	X10, [SP, #48]

0x4656fc LDR	X10, [X29, #216]

0x465700 STUR	X10, [X29, #464]

0x465704 LDR	X10, [X29, #200]

0x465708 STP	X10, X11, [X29, #912]

0x46570c LDR	X10, [X29, #192]

0x465710 STR	X10, [SP, #40]

0x465714 LDR	X10, [X29, #184]

0x465718 STUR	X10, [X29, #456]

0x46571c LDR	X10, [X29, #176]

0x465720 STR	X10, [SP, #104]

0x465724 LDR	X10, [X29, #168]

0x465728 STR	X10, [SP, #32]

0x46572c LDR	X10, [X29, #160]

0x465730 STR	X10, [SP, #24]

0x465734 LDR	X10, [X29, #152]

0x465738 STR	X10, [SP, #120]

0x46573c B.LT	46575c

0x465740 ORR	X9, XZR, XZR

0x465744 MOVN	X10, #0

(1095) 0x465748 STR	X10, [X25, X9,LSL #3]

(1095) 0x46574c ADD	X9, X9, #1

(1095) 0x465750 LDR	X11, [X22]

(1095) 0x465754 CMP	X9, X11

(1095) 0x465758 B.LT	465748

0x46575c LDR	X8, [X8]

0x465760 STP	XZR, XZR, [X29, #984]

0x465764 ADD	X9, X27, #1

0x465768 STUR	X22, [X29, #432]

0x46576c LDR	X22, [X8, X27,LSL #3]

0x465770 LDR	X30, [X8, X9,LSL #3]

0x465774 LDUR	X8, [X29, #424]

0x465778 STR	X28, [SP, #88]

0x46577c STR	X9, [SP, #8]

0x465780 LDR	X8, [X8]

0x465784 STUR	X30, [X29, #416]

0x465788 CMP	X8, #1

0x46578c B.NE	465ac4

0x465790 CMP	X22, X30

0x465794 B.GE	466070

0x465798 LDR	X8, [SP, #96]

0x46579c ORR	X18, XZR, X22

0x4657a0 LDR	X8, [X8]

0x4657a4 STUR	X8, [X29, #448]

0x4657a8 LDR	X8, [SP, #112]

0x4657ac LDR	X8, [X8]

0x4657b0 STUR	X8, [X29, #440]

0x4657b4 LDR	X8, [SP, #120]

0x4657b8 LDR	X8, [X8]

0x4657bc STR	X8, [SP, #144]

0x4657c0 LDR	X8, [SP, #24]

0x4657c4 LDR	X11, [X8]

0x4657c8 LDR	X8, [SP, #32]

0x4657cc LDR	X12, [X8]

0x4657d0 LDR	X8, [SP, #104]

0x4657d4 LDR	X13, [X8]

0x4657d8 LDR	X8, [SP, #40]

0x4657dc LDR	X14, [X8]

0x4657e0 LDUR	X8, [X29, #400]

0x4657e4 LDR	X15, [X8]

0x4657e8 LDUR	X8, [X29, #408]

0x4657ec LDR	X16, [X8]

0x4657f0 LDR	X8, [SP, #48]

0x4657f4 LDR	X17, [X8]

0x4657f8 LDR	X8, [SP, #56]

0x4657fc LDR	X0, [X8]

0x465800 B	465810

    (1088) 0x465804 ADD	X18, X18, #1

    (1088) 0x465808 CMP	X18, X30

    (1088) 0x46580c B.EQ	466070

    (1088) 0x465810 LDUR	X8, [X29, #448]

    (1088) 0x465814 LDP	X2, X1, [X29, #984]

    (1088) 0x465818 LDR	X10, [X8, X18,LSL #3]

    (1088) 0x46581c LDUR	X8, [X29, #440]

    (1088) 0x465820 STR	X1, [X8, X18,LSL #3]

    (1088) 0x465824 LDUR	X8, [X29, #432]

    (1088) 0x465828 LDR	X8, [X8]

    (1088) 0x46582c CBZ	X8, 46583c

    (1088) 0x465830 LDUR	X8, [X29, #472]

    (1088) 0x465834 LDR	X9, [SP, #144]

    (1088) 0x465838 STR	X8, [X9, X18,LSL #3]

    (1088) 0x46583c ADD	X3, X10, #1

    (1088) 0x465840 LDR	X5, [X11, X10,LSL #3]

    (1088) 0x465844 LDR	X8, [X11, X3,LSL #3]

    (1088) 0x465848 CMP	X5, X8

    (1088) 0x46584c B.GE	4659b0

    (1088) 0x465850 LDUR	X8, [X29, #456]

    (1088) 0x465854 STUR	X10, [X29, #376]

    (1088) 0x465858 LDR	X6, [X8]

    (1088) 0x46585c LDUR	X8, [X29, #400]

    (1088) 0x465860 LDR	X7, [X8]

    (1088) 0x465864 LDUR	X8, [X29, #408]

    (1088) 0x465868 LDR	X30, [X8]

    (1088) 0x46586c B	465890

0x465870 HINT	#0

0x465874 HINT	#0

0x465878 HINT	#0

0x46587c HINT	#0

      (1090) 0x465880 LDR	X8, [X11, X3,LSL #3]

      (1090) 0x465884 ADD	X5, X5, #1

      (1090) 0x465888 CMP	X5, X8

      (1090) 0x46588c B.GE	4659a8

      (1090) 0x465890 LDR	X27, [X12, X5,LSL #3]

      (1090) 0x465894 LDR	X8, [X13, X27,LSL #3]

      (1090) 0x465898 CMP	X8, #1

      (1090) 0x46589c B.LT	4658c4

      (1090) 0x4658a0 LDR	X8, [X6, X27,LSL #3]

      (1090) 0x4658a4 LDR	X9, [X24, X8,LSL #3]

      (1090) 0x4658a8 CMP	X9, X1

      (1090) 0x4658ac B.GE	4658c4

      (1090) 0x4658b0 LDUR	X9, [X29, #480]

      (1090) 0x4658b4 STR	X9, [X24, X8,LSL #3]

      (1090) 0x4658b8 LDUR	X8, [X29, #480]

      (1090) 0x4658bc ADD	X8, X8, #1

      (1090) 0x4658c0 STUR	X8, [X29, #480]

      (1090) 0x4658c4 ADD	X28, X27, #1

      (1090) 0x4658c8 LDR	X10, [X11, X27,LSL #3]

      (1090) 0x4658cc LDR	X8, [X11, X28,LSL #3]

      (1090) 0x4658d0 CMP	X10, X8

      (1090) 0x4658d4 B.GE	465940

      (1090) 0x4658d8 LDUR	X9, [X29, #456]

      (1090) 0x4658dc LDR	X9, [X9]

      (1090) 0x4658e0 B	4658f0

        (1092) 0x4658e4 ADD	X10, X10, #1

        (1092) 0x4658e8 CMP	X10, X8

        (1092) 0x4658ec B.GE	465940

        (1092) 0x4658f0 LDR	X4, [X12, X10,LSL #3]

        (1092) 0x4658f4 LDR	X19, [X13, X4,LSL #3]

        (1092) 0x4658f8 CMP	X19, #1

        (1092) 0x4658fc B.LT	4658e4

        (1092) 0x465900 LDR	X4, [X9, X4,LSL #3]

        (1092) 0x465904 CMP	X4, X18

        (1092) 0x465908 B.EQ	4658e4

        (1092) 0x46590c LDR	X19, [X24, X4,LSL #3]

        (1092) 0x465910 CMP	X19, X1

        (1092) 0x465914 B.GE	4658e4

        (1092) 0x465918 LDUR	X8, [X29, #480]

        (1092) 0x46591c STR	X8, [X24, X4,LSL #3]

        (1092) 0x465920 LDUR	X8, [X29, #480]

        (1092) 0x465924 ADD	X8, X8, #1

        (1092) 0x465928 STUR	X8, [X29, #480]

        (1092) 0x46592c LDR	X8, [X11, X28,LSL #3]

        (1092) 0x465930 B	4658e4

0x465934 HINT	#0

0x465938 HINT	#0

0x46593c HINT	#0

      (1090) 0x465940 LDR	X10, [X14, X27,LSL #3]

      (1090) 0x465944 LDR	X9, [X14, X28,LSL #3]

      (1090) 0x465948 CMP	X10, X9

      (1090) 0x46594c B.GE	465880

      (1090) 0x465950 LDUR	X8, [X29, #464]

      (1090) 0x465954 LDR	X8, [X8]

      (1090) 0x465958 B	46596c

0x46595c HINT	#0

        (1091) 0x465960 ADD	X10, X10, #1

        (1091) 0x465964 CMP	X10, X9

        (1091) 0x465968 B.GE	465880

        (1091) 0x46596c LDR	X4, [X7, X10,LSL #3]

        (1091) 0x465970 LDR	X19, [X30, X4,LSL #3]

        (1091) 0x465974 CMP	X19, #1

        (1091) 0x465978 B.LT	465960

        (1091) 0x46597c LDR	X4, [X8, X4,LSL #3]

        (1091) 0x465980 LDR	X19, [X25, X4,LSL #3]

        (1091) 0x465984 CMP	X19, X2

        (1091) 0x465988 B.GE	465960

        (1091) 0x46598c LDUR	X9, [X29, #472]

        (1091) 0x465990 STR	X9, [X25, X4,LSL #3]

        (1091) 0x465994 LDUR	X9, [X29, #472]

        (1091) 0x465998 ADD	X9, X9, #1

        (1091) 0x46599c STUR	X9, [X29, #472]

        (1091) 0x4659a0 LDR	X9, [X14, X28,LSL #3]

        (1091) 0x4659a4 B	465960

    (1088) 0x4659a8 LDUR	X30, [X29, #416]

    (1088) 0x4659ac LDUR	X10, [X29, #376]

    (1088) 0x4659b0 LDR	X4, [X14, X10,LSL #3]

    (1088) 0x4659b4 LDR	X8, [X14, X3,LSL #3]

    (1088) 0x4659b8 CMP	X4, X8

    (1088) 0x4659bc B.GE	465804

  (1089) 0x4659c0 LDUR	X8, [X29, #464]

  (1089) 0x4659c4 LDR	X5, [X8]

  (1089) 0x4659c8 LDUR	X8, [X29, #384]

  (1089) 0x4659cc LDR	X6, [X8]

  (1089) 0x4659d0 LDUR	X8, [X29, #392]

  (1089) 0x4659d4 LDR	X7, [X8]

  (1089) 0x4659d8 B	4659f0

0x4659dc HINT	#0

  (1089) 0x4659e0 LDR	X8, [X14, X3,LSL #3]

  (1089) 0x4659e4 ADD	X4, X4, #1

  (1089) 0x4659e8 CMP	X4, X8

  (1089) 0x4659ec B.GE	465804

  (1089) 0x4659f0 LDR	X28, [X15, X4,LSL #3]

  (1089) 0x4659f4 LDR	X8, [X16, X28,LSL #3]

  (1089) 0x4659f8 CMP	X8, #1

  (1089) 0x4659fc B.LT	465a24

  (1089) 0x465a00 LDR	X8, [X5, X28,LSL #3]

  (1089) 0x465a04 LDR	X9, [X25, X8,LSL #3]

  (1089) 0x465a08 CMP	X9, X2

  (1089) 0x465a0c B.GE	465a24

  (1089) 0x465a10 LDUR	X9, [X29, #472]

  (1089) 0x465a14 STR	X9, [X25, X8,LSL #3]

  (1089) 0x465a18 LDUR	X8, [X29, #472]

  (1089) 0x465a1c ADD	X8, X8, #1

  (1089) 0x465a20 STUR	X8, [X29, #472]

  (1089) 0x465a24 ADD	X27, X28, #1

  (1089) 0x465a28 LDR	X8, [X17, X28,LSL #3]

  (1089) 0x465a2c LDR	X9, [X17, X27,LSL #3]

  (1089) 0x465a30 B	465a44

0x465a34 HINT	#0

0x465a38 HINT	#0

0x465a3c HINT	#0

(1094) 0x465a40 ADD	X8, X8, #1

  (1089) 0x465a44 CMP	X8, X9

  (1089) 0x465a48 B.GE	465a80

(1094) 0x465a4c LDR	X10, [X6, X8,LSL #3]

(1094) 0x465a50 CMP	X10, X18

(1094) 0x465a54 B.EQ	465a40

(1094) 0x465a58 LDR	X19, [X24, X10,LSL #3]

(1094) 0x465a5c CMP	X19, X1

(1094) 0x465a60 B.GE	465a40

(1094) 0x465a64 LDUR	X9, [X29, #480]

(1094) 0x465a68 STR	X9, [X24, X10,LSL #3]

(1094) 0x465a6c LDUR	X9, [X29, #480]

(1094) 0x465a70 ADD	X9, X9, #1

(1094) 0x465a74 STUR	X9, [X29, #480]

(1094) 0x465a78 LDR	X9, [X17, X27,LSL #3]

(1094) 0x465a7c B	465a40

  (1089) 0x465a80 LDR	X8, [X0, X28,LSL #3]

  (1089) 0x465a84 LDR	X9, [X0, X27,LSL #3]

  (1089) 0x465a88 B	465a90

    (1093) 0x465a8c ADD	X8, X8, #1

    (1093) 0x465a90 CMP	X8, X9

    (1093) 0x465a94 B.GE	4659e0

    (1093) 0x465a98 LDR	X10, [X7, X8,LSL #3]

    (1093) 0x465a9c LDR	X19, [X25, X10,LSL #3]

    (1093) 0x465aa0 CMP	X19, X2

    (1093) 0x465aa4 B.GE	465a8c

    (1093) 0x465aa8 LDUR	X9, [X29, #472]

    (1093) 0x465aac STR	X9, [X25, X10,LSL #3]

    (1093) 0x465ab0 LDUR	X9, [X29, #472]

    (1093) 0x465ab4 ADD	X9, X9, #1

    (1093) 0x465ab8 STUR	X9, [X29, #472]

    (1093) 0x465abc LDR	X9, [X0, X27,LSL #3]

    (1093) 0x465ac0 B	465a8c

0x465ac4 CMP	X22, X30

0x465ac8 B.GE	466070

0x465acc LDR	X8, [SP, #96]

0x465ad0 ADD	X9, X20, #8

0x465ad4 ORR	X2, XZR, XZR

0x465ad8 ORR	X3, XZR, XZR

0x465adc MOVZ	W4, #1

0x465ae0 LDR	X8, [X8]

0x465ae4 ORR	X5, XZR, X22

0x465ae8 STUR	X8, [X29, #376]

0x465aec LDR	X8, [SP, #112]

0x465af0 LDR	X8, [X8]

0x465af4 STR	X8, [SP, #144]

0x465af8 LDR	X8, [SP, #120]

0x465afc LDR	X8, [X8]

0x465b00 STR	X8, [SP, #128]

0x465b04 LDR	X8, [SP, #24]

0x465b08 LDR	X11, [X8]

0x465b0c LDR	X8, [SP, #32]

0x465b10 LDR	X12, [X8]

0x465b14 LDR	X8, [SP, #104]

0x465b18 LDR	X13, [X8]

0x465b1c LDR	X8, [SP, #40]

0x465b20 LDR	X14, [X8]

0x465b24 LDUR	X8, [X29, #400]

0x465b28 LDR	X8, [X8]

0x465b2c STUR	X8, [X29, #448]

0x465b30 ADD	X8, X21, #8

0x465b34 STP	X8, X9, [SP, #64]

0x465b38 LDUR	X8, [X29, #408]

0x465b3c LDR	X8, [X8]

0x465b40 STUR	X8, [X29, #440]

0x465b44 LDR	X8, [SP, #48]

0x465b48 LDR	X1, [X8]

0x465b4c LDR	X8, [SP, #56]

0x465b50 LDR	X6, [X8]

0x465b54 B	465b6c

0x465b58 HINT	#0

0x465b5c HINT	#0

    (1078) 0x465b60 ADD	X5, X5, #1

    (1078) 0x465b64 CMP	X5, X16

    (1078) 0x465b68 B.EQ	466070

    (1078) 0x465b6c LDUR	X8, [X29, #376]

    (1078) 0x465b70 LDR	X9, [SP, #144]

    (1078) 0x465b74 ORR	X7, XZR, X3

    (1078) 0x465b78 ORR	X30, XZR, X2

    (1078) 0x465b7c LDR	X15, [X8, X5,LSL #3]

    (1078) 0x465b80 LDUR	X8, [X29, #480]

    (1078) 0x465b84 STR	X8, [X9, X5,LSL #3]

    (1078) 0x465b88 LDUR	X8, [X29, #432]

    (1078) 0x465b8c LDR	X8, [X8]

    (1078) 0x465b90 CBZ	X8, 465ba0

    (1078) 0x465b94 LDUR	X8, [X29, #472]

    (1078) 0x465b98 LDR	X9, [SP, #128]

    (1078) 0x465b9c STR	X8, [X9, X5,LSL #3]

    (1078) 0x465ba0 ADD	X16, X15, #1

    (1078) 0x465ba4 LDR	X10, [X11, X15,LSL #3]

    (1078) 0x465ba8 ORR	X3, XZR, X7

    (1078) 0x465bac ORR	X2, XZR, X30

    (1078) 0x465bb0 LDR	X8, [X11, X16,LSL #3]

    (1078) 0x465bb4 CMP	X10, X8

    (1078) 0x465bb8 B.GE	465d44

    (1078) 0x465bbc STR	X15, [SP, #136]

    (1078) 0x465bc0 LDUR	X8, [X29, #456]

    (1078) 0x465bc4 LDP	X9, X15, [X29, #912]

    (1078) 0x465bc8 ORR	X2, XZR, X30

    (1078) 0x465bcc ORR	X3, XZR, X7

    (1078) 0x465bd0 LDR	X8, [X8]

    (1078) 0x465bd4 LDR	X9, [X9]

    (1078) 0x465bd8 LDR	X0, [X15]

    (1078) 0x465bdc B	465bf0

      (1084) 0x465be0 LDR	X15, [X11, X16,LSL #3]

      (1084) 0x465be4 ADD	X10, X10, #1

      (1084) 0x465be8 CMP	X10, X15

      (1084) 0x465bec B.GE	465d40

      (1084) 0x465bf0 LDR	X27, [X12, X10,LSL #3]

      (1084) 0x465bf4 LDR	X15, [X13, X27,LSL #3]

      (1084) 0x465bf8 CMP	X15, #1

      (1084) 0x465bfc B.LT	465c24

      (1084) 0x465c00 LDR	X15, [X8, X27,LSL #3]

      (1084) 0x465c04 LDR	X17, [X24, X15,LSL #3]

      (1084) 0x465c08 SUBS	X17, X17, X30

      (1084) 0x465c0c B.GE	465c40

      (1084) 0x465c10 STR	X2, [X24, X15,LSL #3]

      (1084) 0x465c14 SUB	X15, X2, X30

      (1084) 0x465c18 MOVZ	W17, #2

      (1084) 0x465c1c ADD	X2, X2, #1

      (1084) 0x465c20 STR	X17, [X20, X15,LSL #3]

      (1084) 0x465c24 ADD	X28, X27, #1

      (1084) 0x465c28 LDR	X17, [X11, X27,LSL #3]

      (1084) 0x465c2c LDR	X15, [X11, X28,LSL #3]

      (1084) 0x465c30 CMP	X17, X15

      (1084) 0x465c34 B.LT	465c60

      (1084) 0x465c38 B	465ccc

0x465c3c HINT	#0

      (1084) 0x465c40 LDR	X15, [X20, X17,LSL #3]

      (1084) 0x465c44 ADD	X15, X15, #2

      (1084) 0x465c48 STR	X15, [X20, X17,LSL #3]

      (1084) 0x465c4c ADD	X28, X27, #1

      (1084) 0x465c50 LDR	X17, [X11, X27,LSL #3]

      (1084) 0x465c54 LDR	X15, [X11, X28,LSL #3]

      (1084) 0x465c58 CMP	X17, X15

      (1084) 0x465c5c B.GE	465ccc

      (1084) 0x465c60 LDUR	X15, [X29, #456]

      (1084) 0x465c64 LDR	X15, [X15]

      (1084) 0x465c68 B	465c90

        (1086) 0x465c6c LDR	X18, [X20, X19,LSL #3]

        (1086) 0x465c70 ADD	X18, X18, #1

        (1086) 0x465c74 STR	X18, [X20, X19,LSL #3]

        (1086) 0x465c78 HINT	#0

        (1086) 0x465c7c HINT	#0

        (1086) 0x465c80 LDR	X18, [X11, X28,LSL #3]

        (1086) 0x465c84 ADD	X17, X17, #1

        (1086) 0x465c88 CMP	X17, X18

        (1086) 0x465c8c B.GE	465ccc

        (1086) 0x465c90 LDR	X18, [X12, X17,LSL #3]

        (1086) 0x465c94 LDR	X19, [X13, X18,LSL #3]

        (1086) 0x465c98 CMP	X19, #1

        (1086) 0x465c9c B.LT	465c80

        (1086) 0x465ca0 LDR	X18, [X15, X18,LSL #3]

        (1086) 0x465ca4 CMP	X18, X5

        (1086) 0x465ca8 B.EQ	465c80

        (1086) 0x465cac LDR	X19, [X24, X18,LSL #3]

        (1086) 0x465cb0 SUBS	X19, X19, X30

        (1086) 0x465cb4 B.GE	465c6c

        (1086) 0x465cb8 STR	X2, [X24, X18,LSL #3]

        (1086) 0x465cbc SUB	X18, X2, X30

        (1086) 0x465cc0 ADD	X2, X2, #1

        (1086) 0x465cc4 STR	X4, [X20, X18,LSL #3]

        (1086) 0x465cc8 B	465c80

      (1084) 0x465ccc LDR	X17, [X14, X27,LSL #3]

      (1084) 0x465cd0 LDR	X15, [X14, X28,LSL #3]

      (1084) 0x465cd4 CMP	X17, X15

      (1084) 0x465cd8 B.GE	465be0

      (1084) 0x465cdc LDUR	X15, [X29, #464]

      (1084) 0x465ce0 LDR	X15, [X15]

      (1084) 0x465ce4 B	465d04

        (1085) 0x465ce8 LDR	X18, [X21, X19,LSL #3]

        (1085) 0x465cec ADD	X18, X18, #1

        (1085) 0x465cf0 STR	X18, [X21, X19,LSL #3]

        (1085) 0x465cf4 LDR	X18, [X14, X28,LSL #3]

        (1085) 0x465cf8 ADD	X17, X17, #1

        (1085) 0x465cfc CMP	X17, X18

        (1085) 0x465d00 B.GE	465be0

        (1085) 0x465d04 LDR	X18, [X9, X17,LSL #3]

        (1085) 0x465d08 LDR	X19, [X0, X18,LSL #3]

        (1085) 0x465d0c CMP	X19, #1

        (1085) 0x465d10 B.LT	465cf4

        (1085) 0x465d14 LDR	X18, [X15, X18,LSL #3]

        (1085) 0x465d18 LDR	X19, [X25, X18,LSL #3]

        (1085) 0x465d1c SUBS	X19, X19, X7

        (1085) 0x465d20 B.GE	465ce8

        (1085) 0x465d24 STR	X3, [X25, X18,LSL #3]

        (1085) 0x465d28 SUB	X18, X3, X7

        (1085) 0x465d2c ADD	X3, X3, #1

        (1085) 0x465d30 STR	X4, [X21, X18,LSL #3]

        (1085) 0x465d34 B	465cf4

0x465d38 HINT	#0

0x465d3c HINT	#0

    (1078) 0x465d40 LDR	X15, [SP, #136]

    (1078) 0x465d44 LDR	X8, [X14, X15,LSL #3]

    (1078) 0x465d48 LDR	X9, [X14, X16,LSL #3]

    (1078) 0x465d4c CMP	X8, X9

    (1078) 0x465d50 B.GE	465ec0

    (1078) 0x465d54 LDUR	X9, [X29, #464]

    (1078) 0x465d58 LDP	X10, X15, [X29, #896]

    (1078) 0x465d5c LDR	X9, [X9]

    (1078) 0x465d60 LDR	X10, [X10]

    (1078) 0x465d64 LDR	X17, [X15]

    (1078) 0x465d68 B	465d7c

      (1081) 0x465d6c LDR	X15, [X14, X16,LSL #3]

      (1081) 0x465d70 ADD	X8, X8, #1

      (1081) 0x465d74 CMP	X8, X15

      (1081) 0x465d78 B.GE	465ec0

      (1081) 0x465d7c LDUR	X15, [X29, #448]

      (1081) 0x465d80 LDR	X27, [X15, X8,LSL #3]

      (1081) 0x465d84 LDUR	X15, [X29, #440]

      (1081) 0x465d88 LDR	X15, [X15, X27,LSL #3]

      (1081) 0x465d8c CMP	X15, #1

      (1081) 0x465d90 B.LT	465db8

      (1081) 0x465d94 LDR	X15, [X9, X27,LSL #3]

      (1081) 0x465d98 LDR	X18, [X25, X15,LSL #3]

      (1081) 0x465d9c SUBS	X18, X18, X7

      (1081) 0x465da0 B.GE	465de0

      (1081) 0x465da4 STR	X3, [X25, X15,LSL #3]

      (1081) 0x465da8 SUB	X15, X3, X7

      (1081) 0x465dac MOVZ	W18, #2

      (1081) 0x465db0 ADD	X3, X3, #1

      (1081) 0x465db4 STR	X18, [X21, X15,LSL #3]

      (1081) 0x465db8 LDR	X15, [X1, X27,LSL #3]

      (1081) 0x465dbc ADD	X0, X27, #1

      (1081) 0x465dc0 LDR	X18, [X1, X0,LSL #3]

      (1081) 0x465dc4 CMP	X15, X18

      (1081) 0x465dc8 B.LT	465e20

      (1081) 0x465dcc B	465e58

0x465dd0 HINT	#0

0x465dd4 HINT	#0

0x465dd8 HINT	#0

0x465ddc HINT	#0

      (1081) 0x465de0 LDR	X15, [X21, X18,LSL #3]

      (1081) 0x465de4 ADD	X15, X15, #2

      (1081) 0x465de8 STR	X15, [X21, X18,LSL #3]

      (1081) 0x465dec LDR	X15, [X1, X27,LSL #3]

      (1081) 0x465df0 ADD	X0, X27, #1

      (1081) 0x465df4 LDR	X18, [X1, X0,LSL #3]

      (1081) 0x465df8 CMP	X15, X18

      (1081) 0x465dfc B.LT	465e20

      (1081) 0x465e00 B	465e58

        (1083) 0x465e04 LDR	X18, [X20, X19,LSL #3]

        (1083) 0x465e08 ADD	X18, X18, #1

        (1083) 0x465e0c STR	X18, [X20, X19,LSL #3]

        (1083) 0x465e10 ADD	X15, X15, #1

        (1083) 0x465e14 LDR	X18, [X1, X0,LSL #3]

        (1083) 0x465e18 CMP	X15, X18

        (1083) 0x465e1c B.GE	465e58

        (1083) 0x465e20 LDR	X18, [X10, X15,LSL #3]

        (1083) 0x465e24 CMP	X18, X5

        (1083) 0x465e28 B.EQ	465e10

        (1083) 0x465e2c LDR	X19, [X24, X18,LSL #3]

        (1083) 0x465e30 SUBS	X19, X19, X30

        (1083) 0x465e34 B.GE	465e04

        (1083) 0x465e38 STR	X2, [X24, X18,LSL #3]

        (1083) 0x465e3c SUB	X18, X2, X30

        (1083) 0x465e40 ADD	X2, X2, #1

        (1083) 0x465e44 ADD	X15, X15, #1

        (1083) 0x465e48 STR	X4, [X20, X18,LSL #3]

        (1083) 0x465e4c LDR	X18, [X1, X0,LSL #3]

        (1083) 0x465e50 CMP	X15, X18

        (1083) 0x465e54 B.LT	465e20

      (1081) 0x465e58 LDR	X15, [X6, X27,LSL #3]

      (1081) 0x465e5c LDR	X18, [X6, X0,LSL #3]

      (1081) 0x465e60 CMP	X15, X18

      (1081) 0x465e64 B.LT	465e8c

      (1081) 0x465e68 B	465d6c

        (1082) 0x465e6c STR	X3, [X25, X18,LSL #3]

        (1082) 0x465e70 SUB	X18, X3, X7

        (1082) 0x465e74 ADD	X3, X3, #1

        (1082) 0x465e78 ADD	X15, X15, #1

        (1082) 0x465e7c STR	X4, [X21, X18,LSL #3]

        (1082) 0x465e80 LDR	X18, [X6, X0,LSL #3]

        (1082) 0x465e84 CMP	X15, X18

        (1082) 0x465e88 B.GE	465d6c

        (1082) 0x465e8c LDR	X18, [X17, X15,LSL #3]

        (1082) 0x465e90 LDR	X19, [X25, X18,LSL #3]

        (1082) 0x465e94 SUBS	X19, X19, X7

        (1082) 0x465e98 B.LT	465e6c

        (1082) 0x465e9c LDR	X18, [X21, X19,LSL #3]

        (1082) 0x465ea0 ADD	X15, X15, #1

        (1082) 0x465ea4 ADD	X18, X18, #1

        (1082) 0x465ea8 STR	X18, [X21, X19,LSL #3]

        (1082) 0x465eac LDR	X18, [X6, X0,LSL #3]

        (1082) 0x465eb0 CMP	X15, X18

        (1082) 0x465eb4 B.LT	465e8c

      (1081) 0x465eb8 B	465d6c

0x465ebc HINT	#0

    (1078) 0x465ec0 CMP	X2, X30

    (1078) 0x465ec4 B.LE	465f08

    (1078) 0x465ec8 SUB	W8, W2, W30

    (1078) 0x465ecc ORR	X9, XZR, X30

    (1078) 0x465ed0 TBZ	W8, #0, 465efc

    (1078) 0x465ed4 LDUR	X9, [X29, #424]

    (1078) 0x465ed8 LDR	X8, [X20]

    (1078) 0x465edc LDR	X9, [X9]

    (1078) 0x465ee0 CMP	X8, X9

    (1078) 0x465ee4 B.LT	465ef4

    (1078) 0x465ee8 LDUR	X8, [X29, #480]

    (1078) 0x465eec ADD	X8, X8, #1

    (1078) 0x465ef0 STUR	X8, [X29, #480]

    (1078) 0x465ef4 ADD	X9, X30, #1

    (1078) 0x465ef8 STR	XZR, [X20]

    (1078) 0x465efc ADD	X8, X30, #1

    (1078) 0x465f00 CMP	X2, X8

    (1078) 0x465f04 B.NE	465fe0

    (1078) 0x465f08 LDP	X16, X17, [X29, #928]

    (1078) 0x465f0c CMP	X3, X7

    (1078) 0x465f10 B.LE	465b60

    (1078) 0x465f14 SUB	W8, W3, W7

    (1078) 0x465f18 ORR	X9, XZR, X7

    (1078) 0x465f1c TBZ	W8, #0, 465f44

    (1078) 0x465f20 LDR	X8, [X21]

    (1078) 0x465f24 LDR	X9, [X17]

    (1078) 0x465f28 CMP	X8, X9

    (1078) 0x465f2c B.LT	465f3c

    (1078) 0x465f30 LDUR	X8, [X29, #472]

    (1078) 0x465f34 ADD	X8, X8, #1

    (1078) 0x465f38 STUR	X8, [X29, #472]

    (1078) 0x465f3c ADD	X9, X7, #1

    (1078) 0x465f40 STR	XZR, [X21]

    (1078) 0x465f44 ADD	X8, X7, #1

    (1078) 0x465f48 CMP	X3, X8

    (1078) 0x465f4c B.EQ	465b60

    (1078) 0x465f50 LDR	X10, [SP, #64]

    (1078) 0x465f54 SUB	X8, X3, X9

    (1078) 0x465f58 SUB	X10, X10, X7,LSL #3

    (1078) 0x465f5c ADD	X9, X10, X9,LSL #3

    (1078) 0x465f60 B	465f70

      (1087) 0x465f64 STR	XZR, [X9], #16

      (1087) 0x465f68 SUBS	X8, X8, #2

      (1087) 0x465f6c B.EQ	465b60

      (1087) 0x465f70 LDUR	X10, [X9, #504]

      (1087) 0x465f74 LDR	X15, [X17]

      (1087) 0x465f78 CMP	X10, X15

      (1087) 0x465f7c B.GE	465fa0

      (1087) 0x465f80 STUR	XZR, [X9, #504]

      (1087) 0x465f84 LDR	X10, [X9]

      (1087) 0x465f88 LDR	X15, [X17]

      (1087) 0x465f8c CMP	X10, X15

      (1087) 0x465f90 B.LT	465f64

      (1087) 0x465f94 B	465fc0

0x465f98 HINT	#0

0x465f9c HINT	#0

      (1087) 0x465fa0 LDUR	X10, [X29, #472]

      (1087) 0x465fa4 ADD	X10, X10, #1

      (1087) 0x465fa8 STUR	X10, [X29, #472]

      (1087) 0x465fac STUR	XZR, [X9, #504]

      (1087) 0x465fb0 LDR	X10, [X9]

      (1087) 0x465fb4 LDR	X15, [X17]

      (1087) 0x465fb8 CMP	X10, X15

      (1087) 0x465fbc B.LT	465f64

      (1087) 0x465fc0 LDUR	X10, [X29, #472]

      (1087) 0x465fc4 ADD	X10, X10, #1

      (1087) 0x465fc8 STUR	X10, [X29, #472]

      (1087) 0x465fcc B	465f64

0x465fd0 HINT	#0

0x465fd4 HINT	#0

0x465fd8 HINT	#0

0x465fdc HINT	#0

  (1080) 0x465fe0 LDR	X10, [SP, #72]

  (1080) 0x465fe4 LDUR	X16, [X29, #424]

  (1080) 0x465fe8 SUB	X8, X2, X9

  (1080) 0x465fec SUB	X10, X10, X30,LSL #3

  (1080) 0x465ff0 ADD	X9, X10, X9,LSL #3

  (1080) 0x465ff4 B	46600c

0x465ff8 HINT	#0

0x465ffc HINT	#0

  (1080) 0x466000 STR	XZR, [X9], #16

  (1080) 0x466004 SUBS	X8, X8, #2

  (1080) 0x466008 B.EQ	465f08

  (1080) 0x46600c LDUR	X10, [X9, #504]

  (1080) 0x466010 LDR	X15, [X16]

  (1080) 0x466014 CMP	X10, X15

  (1080) 0x466018 B.GE	466040

  (1080) 0x46601c STUR	XZR, [X9, #504]

  (1080) 0x466020 LDR	X10, [X9]

  (1080) 0x466024 LDR	X15, [X16]

  (1080) 0x466028 CMP	X10, X15

  (1080) 0x46602c B.LT	466000

  (1080) 0x466030 B	466060

0x466034 HINT	#0

0x466038 HINT	#0

0x46603c HINT	#0

(1079) 0x466040 LDUR	X10, [X29, #480]

(1079) 0x466044 ADD	X10, X10, #1

(1079) 0x466048 STUR	X10, [X29, #480]

(1079) 0x46604c STUR	XZR, [X9, #504]

(1079) 0x466050 LDR	X10, [X9]

(1079) 0x466054 LDR	X15, [X16]

(1079) 0x466058 CMP	X10, X15

(1079) 0x46605c B.LT	466000

  (1080) 0x466060 LDUR	X10, [X29, #480]

  (1080) 0x466064 ADD	X10, X10, #1

  (1080) 0x466068 STUR	X10, [X29, #480]

  (1080) 0x46606c B	466000

0x466070 LDR	X19, [SP, #88]

0x466074 LDR	X8, [SP, #112]

0x466078 SUB	X0, X29, #32

0x46607c SUB	X2, X29, #40

0x466080 LDR	X9, [X19]

0x466084 LDR	X8, [X8]

0x466088 UBFM	X9, X9, #61, #60

0x46608c ADD	X1, X8, X9

0x466090 LDR	X8, [SP, #120]

0x466094 LDR	X8, [X8]

0x466098 ADD	X3, X8, X9

0x46609c LDR	X8, [SP, #80]

0x4660a0 LDR	X4, [X8]

0x4660a4 BL	4a5310

0x4660a8 LDR	X8, [X19]

0x4660ac LDUR	X12, [X29, #432]

0x4660b0 CMP	X8, #1

0x4660b4 B.LT	4660d8

0x4660b8 ORR	X11, XZR, X19

0x4660bc ORR	X8, XZR, XZR

0x4660c0 MOVN	X9, #0

(1077) 0x4660c4 STR	X9, [X24, X8,LSL #3]

(1077) 0x4660c8 ADD	X8, X8, #1

(1077) 0x4660cc LDR	X10, [X11]

(1077) 0x4660d0 CMP	X8, X10

(1077) 0x4660d4 B.LT	4660c4

0x4660d8 LDP	X8, X28, [X29, #264]

0x4660dc STUR	X8, [X29, #448]

0x4660e0 LDR	X8, [X12]

0x4660e4 CMP	X8, #1

0x4660e8 B.LT	466114

0x4660ec ORR	X8, XZR, XZR

0x4660f0 MOVN	X9, #0

0x4660f4 HINT	#0

0x4660f8 HINT	#0

0x4660fc HINT	#0

(1076) 0x466100 STR	X9, [X25, X8,LSL #3]

(1076) 0x466104 ADD	X8, X8, #1

(1076) 0x466108 LDR	X10, [X12]

(1076) 0x46610c CMP	X8, X10

(1076) 0x466110 B.LT	466100

0x466114 LDR	X8, [SP, #16]

0x466118 ADRP	X0,

0x46611c ADD	X0, X0, #560

0x466120 LDR	W27, [X8]

0x466124 ORR	W1, WZR, W27

0x466128 BL	40f4b0

0x46612c ORR	W1, WZR, W27

0x466130 ADRP	X0,

0x466134 ADD	X0, X0, #584

0x466138 BL	40f9f0

0x46613c CBZ	W0, 46619c

0x466140 LDR	X8, [SP, #112]

0x466144 LDR	X10, [SP, #88]

0x466148 LDR	X9, [X8]

0x46614c LDR	X8, [X10]

0x466150 LDR	X9, [X9, X8,LSL #3]

0x466154 CBZ	X9, 466170

0x466158 UBFM	X0, X9, #61, #60

0x46615c ORR	X19, XZR, X10

0x466160 BL	4a2500

0x466164 LDUR	X8, [X29, #448]

0x466168 STR	X0, [X8]

0x46616c LDR	X8, [X19]

0x466170 LDR	X9, [SP, #120]

0x466174 LDR	X9, [X9]

0x466178 LDR	X8, [X9, X8,LSL #3]

0x46617c CBZ	X8, 46618c

0x466180 UBFM	X0, X8, #61, #60

0x466184 BL	4a2500

0x466188 STR	X0, [X28]

0x46618c ORR	W1, WZR, W27

0x466190 ADRP	X0,

0x466194 ADD	X0, X0, #584

0x466198 BL	40f920

0x46619c ORR	W1, WZR, W27

0x4661a0 ADRP	X0,

0x4661a4 ADD	X0, X0, #608

0x4661a8 BL	40f4b0

0x4661ac LDUR	X30, [X29, #416]

0x4661b0 ORR	X9, XZR, X22

0x4661b4 SUB	X8, X30, #1

0x4661b8 CMP	X22, X8

0x4661bc B.GE	466258

0x4661c0 LDP	X10, X9, [SP, #104]

0x4661c4 ORN	X11, XZR, X22

0x4661c8 UBFM	X14, X22, #61, #60

0x4661cc ADD	X11, X11, X30

0x4661d0 LDR	X12, [X9]

0x4661d4 LDR	X9, [SP, #120]

0x4661d8 LDR	X10, [X10]

0x4661dc LDR	X13, [X9]

0x4661e0 LDR	X9, [SP, #96]

0x4661e4 ADD	X12, X12, X14

0x4661e8 LDR	X9, [X9]

0x4661ec ADD	X13, X13, X14

0x4661f0 ADD	X9, X9, X14

0x4661f4 MOVZ	W14, #2

0x4661f8 B	466228

0x4661fc HINT	#0

(1075) 0x466200 LDUR	X16, [X29, #480]

(1075) 0x466204 ADD	X9, X9, #8

(1075) 0x466208 SUBS	X11, X11, #1

(1075) 0x46620c ADD	X15, X16, X15

(1075) 0x466210 STR	X15, [X12], #8

(1075) 0x466214 LDUR	X15, [X29, #472]

(1075) 0x466218 LDR	X16, [X13]

(1075) 0x46621c ADD	X15, X16, X15

(1075) 0x466220 STR	X15, [X13], #8

(1075) 0x466224 B.EQ	466254

(1075) 0x466228 LDP	X15, X16, [X12]

(1075) 0x46622c CMP	X16, X15

(1075) 0x466230 B.NE	466200

(1075) 0x466234 LDP	X17, X15, [X13]

(1075) 0x466238 CMP	X15, X17

(1075) 0x46623c ORR	X15, XZR, X16

(1075) 0x466240 B.NE	466200

(1075) 0x466244 LDR	X15, [X9]

(1075) 0x466248 STR	X14, [X10, X15,LSL #3]

(1075) 0x46624c LDR	X15, [X12]

(1075) 0x466250 B	466200

0x466254 ORR	X9, XZR, X8

0x466258 CMP	X22, X30

0x46625c B.GE	466c00

0x466260 LDR	X8, [SP, #112]

0x466264 LDUR	X10, [X29, #480]

0x466268 LDR	X13, [SP, #8]

0x46626c LDR	X11, [X8]

0x466270 LDR	X8, [X11, X9,LSL #3]

0x466274 ADD	X8, X8, X10

0x466278 LDR	X10, [SP, #120]

0x46627c STR	X8, [X11, X9,LSL #3]

0x466280 LDUR	X8, [X29, #472]

0x466284 LDR	X10, [X10]

0x466288 LDR	X12, [X10, X9,LSL #3]

0x46628c ADD	X8, X12, X8

0x466290 UBFM	X12, X13, #60, #59

0x466294 STR	X8, [X10, X9,LSL #3]

0x466298 LDR	X10, [SP, #80]

0x46629c LDR	X11, [X11, X9,LSL #3]

0x4662a0 LDR	X10, [X10]

0x4662a4 LDR	X12, [X10, X12]

0x4662a8 CMP	X12, X11

0x4662ac B.NE	4662e0

0x4662b0 UBFM	X11, X13, #63, #62

0x4662b4 UBFM	X11, X11, #61, #60

0x4662b8 ORR	X11, X11, #4157

0x4662bc LDR	X10, [X10, X11]

0x4662c0 CMP	X10, X8

0x4662c4 B.NE	4662e0

0x4662c8 LDP	X10, X8, [SP, #96]

0x4662cc LDR	X10, [X10]

0x4662d0 LDR	X8, [X8]

0x4662d4 LDR	X9, [X10, X9,LSL #3]

0x4662d8 MOVZ	W10, #2

0x4662dc STR	X10, [X8, X9,LSL #3]

0x4662e0 LDUR	X8, [X29, #424]

0x4662e4 STUR	X28, [X29, #432]

0x4662e8 LDR	X8, [X8]

0x4662ec CMP	X8, #1

0x4662f0 B.NE	466620

0x4662f4 LDP	X8, X11, [SP, #96]

0x4662f8 LDP	X9, X10, [SP, #24]

0x4662fc LDP	X12, X15, [SP, #40]

0x466300 LDP	X13, X14, [X29, #912]

0x466304 LDR	X16, [SP, #56]

0x466308 LDR	X8, [X8]

0x46630c LDR	X9, [X9]

0x466310 LDR	X10, [X10]

0x466314 LDR	X11, [X11]

0x466318 LDR	X12, [X12]

0x46631c LDR	X13, [X13]

0x466320 LDR	X14, [X14]

0x466324 LDR	X15, [X15]

0x466328 LDR	X16, [X16]

0x46632c B	46634c

0x466330 HINT	#0

0x466334 HINT	#0

0x466338 HINT	#0

0x46633c HINT	#0

    (1068) 0x466340 ADD	X22, X22, #1

    (1068) 0x466344 CMP	X22, X30

    (1068) 0x466348 B.EQ	466c00

    (1068) 0x46634c LDR	X1, [X8, X22,LSL #3]

    (1068) 0x466350 LDP	X18, X17, [X29, #984]

    (1068) 0x466354 ADD	X0, X1, #1

    (1068) 0x466358 LDR	X2, [X9, X1,LSL #3]

    (1068) 0x46635c LDR	X3, [X9, X0,LSL #3]

    (1068) 0x466360 CMP	X2, X3

    (1068) 0x466364 B.GE	4664e0

    (1068) 0x466368 LDP	X4, X3, [X29, #960]

    (1068) 0x46636c LDP	X5, X6, [X29, #912]

    (1068) 0x466370 LDR	X3, [X3]

    (1068) 0x466374 LDR	X4, [X4]

    (1068) 0x466378 LDR	X5, [X5]

    (1068) 0x46637c LDR	X6, [X6]

    (1068) 0x466380 B	466394

      (1071) 0x466384 LDR	X7, [X9, X0,LSL #3]

      (1071) 0x466388 ADD	X2, X2, #1

      (1071) 0x46638c CMP	X2, X7

      (1071) 0x466390 B.GE	4664e0

      (1071) 0x466394 LDR	X19, [X10, X2,LSL #3]

      (1071) 0x466398 LDR	X7, [X11, X19,LSL #3]

      (1071) 0x46639c CMP	X7, #1

      (1071) 0x4663a0 B.LT	4663d0

      (1071) 0x4663a4 LDR	X7, [X3, X19,LSL #3]

      (1071) 0x4663a8 LDR	X20, [X24, X7,LSL #3]

      (1071) 0x4663ac CMP	X20, X17

      (1071) 0x4663b0 B.GE	4663d0

      (1071) 0x4663b4 LDUR	X20, [X29, #480]

      (1071) 0x4663b8 STR	X20, [X24, X7,LSL #3]

      (1071) 0x4663bc LDUR	X20, [X29, #480]

      (1071) 0x4663c0 STR	X7, [X4, X20,LSL #3]

      (1071) 0x4663c4 LDUR	X7, [X29, #480]

      (1071) 0x4663c8 ADD	X7, X7, #1

      (1071) 0x4663cc STUR	X7, [X29, #480]

      (1071) 0x4663d0 ADD	X7, X19, #1

      (1071) 0x4663d4 LDR	X20, [X9, X19,LSL #3]

      (1071) 0x4663d8 LDR	X23, [X9, X7,LSL #3]

      (1071) 0x4663dc CMP	X20, X23

      (1071) 0x4663e0 B.GE	466464

      (1071) 0x4663e4 LDP	X26, X21, [X29, #960]

      (1071) 0x4663e8 LDR	X21, [X21]

      (1071) 0x4663ec LDR	X26, [X26]

      (1071) 0x4663f0 B	46640c

0x4663f4 HINT	#0

0x4663f8 HINT	#0

0x4663fc HINT	#0

        (1073) 0x466400 ADD	X20, X20, #1

        (1073) 0x466404 CMP	X20, X23

        (1073) 0x466408 B.GE	466460

        (1073) 0x46640c LDR	X27, [X10, X20,LSL #3]

        (1073) 0x466410 LDR	X28, [X11, X27,LSL #3]

        (1073) 0x466414 CMP	X28, #1

        (1073) 0x466418 B.LT	466400

        (1073) 0x46641c LDR	X27, [X21, X27,LSL #3]

        (1073) 0x466420 CMP	X27, X22

        (1073) 0x466424 B.EQ	466400

        (1073) 0x466428 LDR	X28, [X24, X27,LSL #3]

        (1073) 0x46642c CMP	X28, X17

        (1073) 0x466430 B.GE	466400

        (1073) 0x466434 LDUR	X23, [X29, #480]

        (1073) 0x466438 STR	X23, [X24, X27,LSL #3]

        (1073) 0x46643c LDUR	X23, [X29, #480]

        (1073) 0x466440 STR	X27, [X26, X23,LSL #3]

        (1073) 0x466444 LDUR	X23, [X29, #480]

        (1073) 0x466448 ADD	X23, X23, #1

        (1073) 0x46644c STUR	X23, [X29, #480]

        (1073) 0x466450 LDR	X23, [X9, X7,LSL #3]

        (1073) 0x466454 B	466400

0x466458 HINT	#0

0x46645c HINT	#0

      (1071) 0x466460 LDUR	X28, [X29, #432]

      (1071) 0x466464 LDR	X19, [X12, X19,LSL #3]

      (1071) 0x466468 LDR	X23, [X12, X7,LSL #3]

      (1071) 0x46646c CMP	X19, X23

      (1071) 0x466470 B.GE	466384

      (1071) 0x466474 LDUR	X20, [X29, #464]

      (1071) 0x466478 LDR	X21, [X28]

      (1071) 0x46647c LDR	X20, [X20]

      (1071) 0x466480 B	466490

        (1072) 0x466484 ADD	X19, X19, #1

        (1072) 0x466488 CMP	X19, X23

        (1072) 0x46648c B.GE	466384

        (1072) 0x466490 LDR	X26, [X5, X19,LSL #3]

        (1072) 0x466494 LDR	X27, [X6, X26,LSL #3]

        (1072) 0x466498 CMP	X27, #1

        (1072) 0x46649c B.LT	466484

        (1072) 0x4664a0 LDR	X26, [X20, X26,LSL #3]

        (1072) 0x4664a4 LDR	X27, [X25, X26,LSL #3]

        (1072) 0x4664a8 CMP	X27, X18

        (1072) 0x4664ac B.GE	466484

        (1072) 0x4664b0 LDUR	X23, [X29, #472]

        (1072) 0x4664b4 STR	X23, [X25, X26,LSL #3]

        (1072) 0x4664b8 LDUR	X23, [X29, #472]

        (1072) 0x4664bc STR	X26, [X21, X23,LSL #3]

        (1072) 0x4664c0 LDUR	X23, [X29, #472]

        (1072) 0x4664c4 ADD	X23, X23, #1

        (1072) 0x4664c8 STUR	X23, [X29, #472]

        (1072) 0x4664cc LDR	X23, [X12, X7,LSL #3]

        (1072) 0x4664d0 B	466484

0x4664d4 HINT	#0

0x4664d8 HINT	#0

0x4664dc HINT	#0

    (1068) 0x4664e0 LDR	X1, [X12, X1,LSL #3]

    (1068) 0x4664e4 LDR	X2, [X12, X0,LSL #3]

    (1068) 0x4664e8 CMP	X1, X2

    (1068) 0x4664ec B.GE	466340

  (1069) 0x4664f0 LDUR	X2, [X29, #464]

  (1069) 0x4664f4 LDP	X4, X5, [X29, #896]

  (1069) 0x4664f8 LDR	X3, [X28]

  (1069) 0x4664fc LDR	X2, [X2]

  (1069) 0x466500 LDR	X4, [X4]

  (1069) 0x466504 LDR	X5, [X5]

  (1069) 0x466508 B	46651c

  (1069) 0x46650c LDR	X6, [X12, X0,LSL #3]

  (1069) 0x466510 ADD	X1, X1, #1

  (1069) 0x466514 CMP	X1, X6

  (1069) 0x466518 B.GE	466340

  (1069) 0x46651c LDR	X7, [X13, X1,LSL #3]

  (1069) 0x466520 LDR	X6, [X14, X7,LSL #3]

  (1069) 0x466524 CMP	X6, #1

  (1069) 0x466528 B.LT	466558

  (1069) 0x46652c LDR	X6, [X2, X7,LSL #3]

  (1069) 0x466530 LDR	X19, [X25, X6,LSL #3]

  (1069) 0x466534 CMP	X19, X18

  (1069) 0x466538 B.GE	466558

  (1069) 0x46653c LDUR	X19, [X29, #472]

  (1069) 0x466540 STR	X19, [X25, X6,LSL #3]

  (1069) 0x466544 LDUR	X19, [X29, #472]

  (1069) 0x466548 STR	X6, [X3, X19,LSL #3]

  (1069) 0x46654c LDUR	X6, [X29, #472]

  (1069) 0x466550 ADD	X6, X6, #1

  (1069) 0x466554 STUR	X6, [X29, #472]

  (1069) 0x466558 ADD	X6, X7, #1

  (1069) 0x46655c LDR	X19, [X15, X7,LSL #3]

  (1069) 0x466560 LDR	X21, [X15, X6,LSL #3]

  (1069) 0x466564 CMP	X19, X21

  (1069) 0x466568 B.GE	4665c8

(1070) 0x46656c LDUR	X20, [X29, #448]

(1070) 0x466570 LDR	X20, [X20]

(1070) 0x466574 B	46658c

0x466578 HINT	#0

0x46657c HINT	#0

(1070) 0x466580 ADD	X19, X19, #1

(1070) 0x466584 CMP	X19, X21

(1070) 0x466588 B.GE	4665c8

(1070) 0x46658c LDR	X23, [X4, X19,LSL #3]

(1070) 0x466590 CMP	X23, X22

(1070) 0x466594 B.EQ	466580

(1070) 0x466598 LDR	X26, [X24, X23,LSL #3]

(1070) 0x46659c CMP	X26, X17

(1070) 0x4665a0 B.GE	466580

(1070) 0x4665a4 LDUR	X21, [X29, #480]

(1070) 0x4665a8 STR	X21, [X24, X23,LSL #3]

(1070) 0x4665ac LDUR	X21, [X29, #480]

(1070) 0x4665b0 STR	X23, [X20, X21,LSL #3]

(1070) 0x4665b4 LDUR	X21, [X29, #480]

(1070) 0x4665b8 ADD	X21, X21, #1

(1070) 0x4665bc STUR	X21, [X29, #480]

(1070) 0x4665c0 LDR	X21, [X15, X6,LSL #3]

(1070) 0x4665c4 B	466580

  (1069) 0x4665c8 LDR	X7, [X16, X7,LSL #3]

  (1069) 0x4665cc LDR	X20, [X16, X6,LSL #3]

  (1069) 0x4665d0 CMP	X7, X20

  (1069) 0x4665d4 B.GE	46650c

  (1069) 0x4665d8 LDR	X19, [X28]

  (1069) 0x4665dc B	4665ec

    (1074) 0x4665e0 ADD	X7, X7, #1

    (1074) 0x4665e4 CMP	X7, X20

    (1074) 0x4665e8 B.GE	46650c

    (1074) 0x4665ec LDR	X21, [X5, X7,LSL #3]

    (1074) 0x4665f0 LDR	X23, [X25, X21,LSL #3]

    (1074) 0x4665f4 CMP	X23, X18

    (1074) 0x4665f8 B.GE	4665e0

    (1074) 0x4665fc LDUR	X20, [X29, #472]

    (1074) 0x466600 STR	X20, [X25, X21,LSL #3]

    (1074) 0x466604 LDUR	X20, [X29, #472]

    (1074) 0x466608 STR	X21, [X19, X20,LSL #3]

    (1074) 0x46660c LDUR	X20, [X29, #472]

    (1074) 0x466610 ADD	X20, X20, #1

    (1074) 0x466614 STUR	X20, [X29, #472]

    (1074) 0x466618 LDR	X20, [X16, X6,LSL #3]

    (1074) 0x46661c B	4665e0

0x466620 LDR	X8, [SP, #96]

0x466624 LDP	X12, X13, [X29, #984]

0x466628 MOVZ	W4, #1

0x46662c LDR	X8, [X8]

0x466630 STUR	X8, [X29, #376]

0x466634 LDR	X8, [SP, #24]

0x466638 LDR	X9, [X8]

0x46663c LDR	X8, [SP, #32]

0x466640 LDR	X10, [X8]

0x466644 LDR	X8, [SP, #104]

0x466648 LDR	X11, [X8]

0x46664c LDR	X8, [SP, #40]

0x466650 LDR	X14, [X8]

0x466654 ADD	X8, X26, #8

0x466658 STR	X8, [SP, #136]

0x46665c LDUR	X8, [X29, #400]

0x466660 LDR	X8, [X8]

0x466664 STUR	X8, [X29, #440]

0x466668 ADD	X8, X20, #8

0x46666c STR	X8, [SP, #128]

0x466670 ADD	X8, X23, #8

0x466674 STR	X8, [SP, #120]

0x466678 LDUR	X8, [X29, #408]

0x46667c LDR	X0, [X8]

0x466680 ADD	X8, X21, #8

0x466684 STR	X8, [SP, #112]

0x466688 LDR	X8, [SP, #48]

0x46668c LDR	X2, [X8]

0x466690 LDR	X8, [SP, #56]

0x466694 LDR	X5, [X8]

0x466698 B	4666ac

0x46669c HINT	#0

    (1058) 0x4666a0 ADD	X22, X22, #1

    (1058) 0x4666a4 CMP	X22, X19

    (1058) 0x4666a8 B.EQ	466c00

    (1058) 0x4666ac LDUR	X8, [X29, #376]

    (1058) 0x4666b0 ORR	X6, XZR, X12

    (1058) 0x4666b4 ORR	X7, XZR, X13

    (1058) 0x4666b8 LDR	X15, [X8, X22,LSL #3]

    (1058) 0x4666bc ADD	X30, X15, #1

    (1058) 0x4666c0 LDR	X17, [X9, X15,LSL #3]

    (1058) 0x4666c4 LDR	X8, [X9, X30,LSL #3]

    (1058) 0x4666c8 CMP	X17, X8

    (1058) 0x4666cc B.GE	466888

    (1058) 0x4666d0 LDUR	X8, [X29, #456]

    (1058) 0x4666d4 ORR	X13, XZR, X7

    (1058) 0x4666d8 ORR	X12, XZR, X6

    (1058) 0x4666dc STR	X15, [SP, #144]

    (1058) 0x4666e0 LDR	X18, [X8]

    (1058) 0x4666e4 LDUR	X8, [X29, #400]

    (1058) 0x4666e8 LDR	X1, [X8]

    (1058) 0x4666ec LDUR	X8, [X29, #408]

    (1058) 0x4666f0 LDR	X8, [X8]

    (1058) 0x4666f4 B	466710

0x4666f8 HINT	#0

0x4666fc HINT	#0

      (1064) 0x466700 LDR	X15, [X9, X30,LSL #3]

      (1064) 0x466704 ADD	X17, X17, #1

      (1064) 0x466708 CMP	X17, X15

      (1064) 0x46670c B.GE	466880

      (1064) 0x466710 LDR	X28, [X10, X17,LSL #3]

      (1064) 0x466714 LDR	X15, [X11, X28,LSL #3]

      (1064) 0x466718 CMP	X15, #1

      (1064) 0x46671c B.LT	466748

      (1064) 0x466720 LDR	X15, [X18, X28,LSL #3]

      (1064) 0x466724 LDR	X16, [X24, X15,LSL #3]

      (1064) 0x466728 SUBS	X16, X16, X7

      (1064) 0x46672c B.GE	466760

      (1064) 0x466730 SUB	X16, X13, X7

      (1064) 0x466734 STR	X13, [X24, X15,LSL #3]

      (1064) 0x466738 ADD	X13, X13, #1

      (1064) 0x46673c STR	X15, [X26, X16,LSL #3]

      (1064) 0x466740 MOVZ	W15, #2

      (1064) 0x466744 STR	X15, [X20, X16,LSL #3]

      (1064) 0x466748 ADD	X3, X28, #1

      (1064) 0x46674c LDR	X27, [X9, X28,LSL #3]

      (1064) 0x466750 LDR	X15, [X9, X3,LSL #3]

      (1064) 0x466754 CMP	X27, X15

      (1064) 0x466758 B.LT	466780

      (1064) 0x46675c B	466800

      (1064) 0x466760 LDR	X15, [X20, X16,LSL #3]

      (1064) 0x466764 ADD	X15, X15, #2

      (1064) 0x466768 STR	X15, [X20, X16,LSL #3]

      (1064) 0x46676c ADD	X3, X28, #1

      (1064) 0x466770 LDR	X27, [X9, X28,LSL #3]

      (1064) 0x466774 LDR	X15, [X9, X3,LSL #3]

      (1064) 0x466778 CMP	X27, X15

      (1064) 0x46677c B.GE	466800

      (1064) 0x466780 LDUR	X15, [X29, #456]

      (1064) 0x466784 LDR	X15, [X15]

      (1064) 0x466788 B	4667b0

        (1066) 0x46678c LDR	X16, [X20, X19,LSL #3]

        (1066) 0x466790 ADD	X16, X16, #1

        (1066) 0x466794 STR	X16, [X20, X19,LSL #3]

        (1066) 0x466798 HINT	#0

        (1066) 0x46679c HINT	#0

        (1066) 0x4667a0 LDR	X16, [X9, X3,LSL #3]

        (1066) 0x4667a4 ADD	X27, X27, #1

        (1066) 0x4667a8 CMP	X27, X16

        (1066) 0x4667ac B.GE	466800

        (1066) 0x4667b0 LDR	X16, [X10, X27,LSL #3]

        (1066) 0x4667b4 LDR	X19, [X11, X16,LSL #3]

        (1066) 0x4667b8 CMP	X19, #1

        (1066) 0x4667bc B.LT	4667a0

        (1066) 0x4667c0 LDR	X16, [X15, X16,LSL #3]

        (1066) 0x4667c4 CMP	X16, X22

        (1066) 0x4667c8 B.EQ	4667a0

        (1066) 0x4667cc LDR	X19, [X24, X16,LSL #3]

        (1066) 0x4667d0 SUBS	X19, X19, X7

        (1066) 0x4667d4 B.GE	46678c

        (1066) 0x4667d8 SUB	X19, X13, X7

        (1066) 0x4667dc STR	X13, [X24, X16,LSL #3]

        (1066) 0x4667e0 ADD	X13, X13, #1

        (1066) 0x4667e4 STR	X16, [X26, X19,LSL #3]

        (1066) 0x4667e8 STR	X4, [X20, X19,LSL #3]

        (1066) 0x4667ec B	4667a0

0x4667f0 HINT	#0

0x4667f4 HINT	#0

0x4667f8 HINT	#0

0x4667fc HINT	#0

      (1064) 0x466800 LDR	X27, [X14, X28,LSL #3]

      (1064) 0x466804 LDR	X15, [X14, X3,LSL #3]

      (1064) 0x466808 CMP	X27, X15

      (1064) 0x46680c B.GE	466700

      (1064) 0x466810 LDUR	X15, [X29, #464]

      (1064) 0x466814 LDR	X15, [X15]

      (1064) 0x466818 B	46683c

0x46681c HINT	#0

        (1065) 0x466820 LDR	X16, [X21, X19,LSL #3]

        (1065) 0x466824 ADD	X16, X16, #1

        (1065) 0x466828 STR	X16, [X21, X19,LSL #3]

        (1065) 0x46682c LDR	X16, [X14, X3,LSL #3]

        (1065) 0x466830 ADD	X27, X27, #1

        (1065) 0x466834 CMP	X27, X16

        (1065) 0x466838 B.GE	466700

        (1065) 0x46683c LDR	X16, [X1, X27,LSL #3]

        (1065) 0x466840 LDR	X19, [X8, X16,LSL #3]

        (1065) 0x466844 CMP	X19, #1

        (1065) 0x466848 B.LT	46682c

        (1065) 0x46684c LDR	X16, [X15, X16,LSL #3]

        (1065) 0x466850 LDR	X19, [X25, X16,LSL #3]

        (1065) 0x466854 SUBS	X19, X19, X6

        (1065) 0x466858 B.GE	466820

        (1065) 0x46685c SUB	X19, X12, X6

        (1065) 0x466860 STR	X12, [X25, X16,LSL #3]

        (1065) 0x466864 ADD	X12, X12, #1

        (1065) 0x466868 STR	X16, [X23, X19,LSL #3]

        (1065) 0x46686c STR	X4, [X21, X19,LSL #3]

        (1065) 0x466870 B	46682c

0x466874 HINT	#0

0x466878 HINT	#0

0x46687c HINT	#0

    (1058) 0x466880 LDUR	X28, [X29, #432]

    (1058) 0x466884 LDR	X15, [SP, #144]

    (1058) 0x466888 LDR	X8, [X14, X15,LSL #3]

    (1058) 0x46688c LDR	X15, [X14, X30,LSL #3]

    (1058) 0x466890 CMP	X8, X15

    (1058) 0x466894 B.GE	466a20

    (1058) 0x466898 LDUR	X16, [X29, #384]

    (1058) 0x46689c LDUR	X15, [X29, #464]

    (1058) 0x4668a0 LDR	X17, [X16]

    (1058) 0x4668a4 LDUR	X16, [X29, #392]

    (1058) 0x4668a8 LDR	X15, [X15]

    (1058) 0x4668ac LDR	X18, [X16]

    (1058) 0x4668b0 B	4668d0

0x4668b4 HINT	#0

0x4668b8 HINT	#0

0x4668bc HINT	#0

      (1061) 0x4668c0 LDR	X16, [X14, X30,LSL #3]

      (1061) 0x4668c4 ADD	X8, X8, #1

      (1061) 0x4668c8 CMP	X8, X16

      (1061) 0x4668cc B.GE	466a20

      (1061) 0x4668d0 LDUR	X16, [X29, #440]

      (1061) 0x4668d4 LDR	X3, [X16, X8,LSL #3]

      (1061) 0x4668d8 LDR	X16, [X0, X3,LSL #3]

      (1061) 0x4668dc CMP	X16, #1

      (1061) 0x4668e0 B.LT	46690c

      (1061) 0x4668e4 LDR	X16, [X15, X3,LSL #3]

      (1061) 0x4668e8 LDR	X1, [X25, X16,LSL #3]

      (1061) 0x4668ec SUBS	X1, X1, X6

      (1061) 0x4668f0 B.GE	466924

      (1061) 0x4668f4 SUB	X1, X12, X6

      (1061) 0x4668f8 STR	X12, [X25, X16,LSL #3]

      (1061) 0x4668fc ADD	X12, X12, #1

      (1061) 0x466900 STR	X16, [X23, X1,LSL #3]

      (1061) 0x466904 MOVZ	W16, #2

      (1061) 0x466908 STR	X16, [X21, X1,LSL #3]

      (1061) 0x46690c LDR	X27, [X2, X3,LSL #3]

      (1061) 0x466910 ADD	X1, X3, #1

      (1061) 0x466914 LDR	X16, [X2, X1,LSL #3]

      (1061) 0x466918 CMP	X27, X16

      (1061) 0x46691c B.LT	466964

      (1061) 0x466920 B	4669a0

      (1061) 0x466924 LDR	X16, [X21, X1,LSL #3]

      (1061) 0x466928 ADD	X16, X16, #2

      (1061) 0x46692c STR	X16, [X21, X1,LSL #3]

      (1061) 0x466930 LDR	X27, [X2, X3,LSL #3]

      (1061) 0x466934 ADD	X1, X3, #1

      (1061) 0x466938 LDR	X16, [X2, X1,LSL #3]

      (1061) 0x46693c CMP	X27, X16

      (1061) 0x466940 B.LT	466964

      (1061) 0x466944 B	4669a0

        (1063) 0x466948 LDR	X16, [X20, X19,LSL #3]

        (1063) 0x46694c ADD	X16, X16, #1

        (1063) 0x466950 STR	X16, [X20, X19,LSL #3]

        (1063) 0x466954 ADD	X27, X27, #1

        (1063) 0x466958 LDR	X16, [X2, X1,LSL #3]

        (1063) 0x46695c CMP	X27, X16

        (1063) 0x466960 B.GE	4669a0

        (1063) 0x466964 LDR	X16, [X17, X27,LSL #3]

        (1063) 0x466968 CMP	X16, X22

        (1063) 0x46696c B.EQ	466954

        (1063) 0x466970 LDR	X19, [X24, X16,LSL #3]

        (1063) 0x466974 SUBS	X19, X19, X7

        (1063) 0x466978 B.GE	466948

        (1063) 0x46697c SUB	X19, X13, X7

        (1063) 0x466980 STR	X13, [X24, X16,LSL #3]

        (1063) 0x466984 ADD	X13, X13, #1

        (1063) 0x466988 ADD	X27, X27, #1

        (1063) 0x46698c STR	X16, [X26, X19,LSL #3]

        (1063) 0x466990 STR	X4, [X20, X19,LSL #3]

        (1063) 0x466994 LDR	X16, [X2, X1,LSL #3]

        (1063) 0x466998 CMP	X27, X16

        (1063) 0x46699c B.LT	466964

      (1061) 0x4669a0 LDR	X3, [X5, X3,LSL #3]

      (1061) 0x4669a4 LDR	X16, [X5, X1,LSL #3]

      (1061) 0x4669a8 CMP	X3, X16

      (1061) 0x4669ac B.LT	4669e4

      (1061) 0x4669b0 B	4668c0

0x4669b4 HINT	#0

0x4669b8 HINT	#0

0x4669bc HINT	#0

        (1062) 0x4669c0 SUB	X19, X12, X6

        (1062) 0x4669c4 STR	X12, [X25, X16,LSL #3]

        (1062) 0x4669c8 ADD	X12, X12, #1

        (1062) 0x4669cc ADD	X3, X3, #1

        (1062) 0x4669d0 STR	X16, [X23, X19,LSL #3]

        (1062) 0x4669d4 STR	X4, [X21, X19,LSL #3]

        (1062) 0x4669d8 LDR	X16, [X5, X1,LSL #3]

        (1062) 0x4669dc CMP	X3, X16

        (1062) 0x4669e0 B.GE	4668c0

        (1062) 0x4669e4 LDR	X16, [X18, X3,LSL #3]

        (1062) 0x4669e8 LDR	X19, [X25, X16,LSL #3]

        (1062) 0x4669ec SUBS	X19, X19, X6

        (1062) 0x4669f0 B.LT	4669c0

        (1062) 0x4669f4 LDR	X16, [X21, X19,LSL #3]

        (1062) 0x4669f8 ADD	X3, X3, #1

        (1062) 0x4669fc ADD	X16, X16, #1

        (1062) 0x466a00 STR	X16, [X21, X19,LSL #3]

        (1062) 0x466a04 LDR	X16, [X5, X1,LSL #3]

        (1062) 0x466a08 CMP	X3, X16

        (1062) 0x466a0c B.LT	4669e4

      (1061) 0x466a10 B	4668c0

0x466a14 HINT	#0

0x466a18 HINT	#0

0x466a1c HINT	#0

    (1058) 0x466a20 LDP	X19, X27, [X29, #928]

    (1058) 0x466a24 CMP	X13, X7

    (1058) 0x466a28 B.LE	466a78

    (1058) 0x466a2c LDUR	X8, [X29, #448]

    (1058) 0x466a30 SUB	W15, W13, W7

    (1058) 0x466a34 ORR	X17, XZR, X7

    (1058) 0x466a38 LDR	X8, [X8]

    (1058) 0x466a3c TBZ	W15, #0, 466a6c

    (1058) 0x466a40 LDR	X15, [X20]

    (1058) 0x466a44 LDR	X16, [X27]

    (1058) 0x466a48 CMP	X15, X16

    (1058) 0x466a4c B.LT	466a64

    (1058) 0x466a50 LDUR	X16, [X29, #480]

    (1058) 0x466a54 LDR	X15, [X26]

    (1058) 0x466a58 ADD	X17, X16, #1

    (1058) 0x466a5c STUR	X17, [X29, #480]

    (1058) 0x466a60 STR	X15, [X8, X16,LSL #3]

    (1058) 0x466a64 ADD	X17, X7, #1

    (1058) 0x466a68 STR	XZR, [X20]

    (1058) 0x466a6c ADD	X15, X7, #1

    (1058) 0x466a70 CMP	X13, X15

    (1058) 0x466a74 B.NE	466b60

    (1058) 0x466a78 CMP	X12, X6

    (1058) 0x466a7c B.LE	4666a0

    (1058) 0x466a80 LDR	X8, [X28]

    (1058) 0x466a84 SUB	W15, W12, W6

    (1058) 0x466a88 ORR	X17, XZR, X6

    (1058) 0x466a8c TBZ	W15, #0, 466abc

    (1058) 0x466a90 LDR	X15, [X21]

    (1058) 0x466a94 LDR	X16, [X27]

    (1058) 0x466a98 CMP	X15, X16

    (1058) 0x466a9c B.LT	466ab4

    (1058) 0x466aa0 LDUR	X16, [X29, #472]

    (1058) 0x466aa4 LDR	X15, [X23]

    (1058) 0x466aa8 ADD	X17, X16, #1

    (1058) 0x466aac STUR	X17, [X29, #472]

    (1058) 0x466ab0 STR	X15, [X8, X16,LSL #3]

    (1058) 0x466ab4 ADD	X17, X6, #1

    (1058) 0x466ab8 STR	XZR, [X21]

    (1058) 0x466abc ADD	X15, X6, #1

    (1058) 0x466ac0 CMP	X12, X15

    (1058) 0x466ac4 B.EQ	4666a0

    (1058) 0x466ac8 SUB	X15, X12, X17

    (1058) 0x466acc UBFM	X16, X17, #61, #60

    (1058) 0x466ad0 LDP	X18, X17, [SP, #112]

    (1058) 0x466ad4 SUB	X16, X16, X6,LSL #3

    (1058) 0x466ad8 ADD	X17, X17, X16

    (1058) 0x466adc ADD	X18, X18, X16

    (1058) 0x466ae0 B	466af4

      (1067) 0x466ae4 STR	XZR, [X18], #16

      (1067) 0x466ae8 SUBS	X15, X15, #2

      (1067) 0x466aec ADD	X17, X17, #16

      (1067) 0x466af0 B.EQ	4666a0

      (1067) 0x466af4 LDUR	X16, [X18, #504]

      (1067) 0x466af8 LDR	X1, [X27]

      (1067) 0x466afc CMP	X16, X1

      (1067) 0x466b00 B.GE	466b20

      (1067) 0x466b04 STUR	XZR, [X18, #504]

      (1067) 0x466b08 LDR	X16, [X18]

      (1067) 0x466b0c LDR	X1, [X27]

      (1067) 0x466b10 CMP	X16, X1

      (1067) 0x466b14 B.LT	466ae4

      (1067) 0x466b18 B	466b48

0x466b1c HINT	#0

      (1067) 0x466b20 LDUR	X1, [X29, #472]

      (1067) 0x466b24 LDUR	X16, [X17, #504]

      (1067) 0x466b28 ADD	X3, X1, #1

      (1067) 0x466b2c STUR	X3, [X29, #472]

      (1067) 0x466b30 STR	X16, [X8, X1,LSL #3]

      (1067) 0x466b34 STUR	XZR, [X18, #504]

      (1067) 0x466b38 LDR	X16, [X18]

      (1067) 0x466b3c LDR	X1, [X27]

      (1067) 0x466b40 CMP	X16, X1

      (1067) 0x466b44 B.LT	466ae4

      (1067) 0x466b48 LDUR	X1, [X29, #472]

      (1067) 0x466b4c LDR	X16, [X17]

      (1067) 0x466b50 ADD	X3, X1, #1

      (1067) 0x466b54 STUR	X3, [X29, #472]

      (1067) 0x466b58 STR	X16, [X8, X1,LSL #3]

      (1067) 0x466b5c B	466ae4

  (1060) 0x466b60 SUB	X15, X13, X17

  (1060) 0x466b64 UBFM	X16, X17, #61, #60

  (1060) 0x466b68 LDP	X18, X17, [SP, #128]

  (1060) 0x466b6c SUB	X16, X16, X7,LSL #3

  (1060) 0x466b70 ADD	X17, X17, X16

  (1060) 0x466b74 ADD	X18, X18, X16

  (1060) 0x466b78 B	466b90

0x466b7c HINT	#0

  (1060) 0x466b80 STR	XZR, [X18], #16

  (1060) 0x466b84 SUBS	X15, X15, #2

  (1060) 0x466b88 ADD	X17, X17, #16

  (1060) 0x466b8c B.EQ	466a78

  (1060) 0x466b90 LDUR	X16, [X18, #504]

  (1060) 0x466b94 LDR	X1, [X27]

  (1060) 0x466b98 CMP	X16, X1

  (1060) 0x466b9c B.GE	466bc0

  (1060) 0x466ba0 STUR	XZR, [X18, #504]

  (1060) 0x466ba4 LDR	X16, [X18]

  (1060) 0x466ba8 LDR	X1, [X27]

  (1060) 0x466bac CMP	X16, X1

  (1060) 0x466bb0 B.LT	466b80

  (1060) 0x466bb4 B	466be8

0x466bb8 HINT	#0

0x466bbc HINT	#0

(1059) 0x466bc0 LDUR	X1, [X29, #480]

(1059) 0x466bc4 LDUR	X16, [X17, #504]

(1059) 0x466bc8 ADD	X3, X1, #1

(1059) 0x466bcc STUR	X3, [X29, #480]

(1059) 0x466bd0 STR	X16, [X8, X1,LSL #3]

(1059) 0x466bd4 STUR	XZR, [X18, #504]

(1059) 0x466bd8 LDR	X16, [X18]

(1059) 0x466bdc LDR	X1, [X27]

(1059) 0x466be0 CMP	X16, X1

(1059) 0x466be4 B.LT	466b80

  (1060) 0x466be8 LDUR	X1, [X29, #480]

  (1060) 0x466bec LDR	X16, [X17]

  (1060) 0x466bf0 ADD	X3, X1, #1

  (1060) 0x466bf4 STUR	X3, [X29, #480]

  (1060) 0x466bf8 STR	X16, [X8, X1,LSL #3]

  (1060) 0x466bfc B	466b80

0x466c00 LDP	X20, X19, [SP, #368]

0x466c04 LDP	X22, X21, [SP, #352]

0x466c08 LDP	X24, X23, [SP, #336]

0x466c0c LDP	X26, X25, [SP, #320]

0x466c10 LDP	X28, X27, [SP, #304]

0x466c14 LDP	X29, X30, [SP, #288]

0x466c18 ADD	SP, SP, #384

0x466c1c RET

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	par_strength.c:1668-2230
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c:1668-1697,1705-1714,1720-1797,1806,1812-2000,2006-2083,2093-2095,2101-2230.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 75.17 to 9.40 cycles (8.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 75.17 to 4.50 cycles (16.70x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 1516 bytes. The binary function is storing 488 bytes.

General properties

nb instructions	439
loop length	1756
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

45.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	16.00	16.00	28.25	28.25	28.25	28.25	0.00	0.00	0.00	0.00	75.17	74.83	75.00	25.50	25.50
cycles	16.00	16.00	28.25	28.25	28.25	28.25	0.00	0.00	0.00	0.00	75.17	74.83	75.00	25.50	25.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	45.13
Overall L1	75.17

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 75.17 cycles. At this rate:

21% of peak load performance is reached (20.17 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.49 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 465590

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X8, X9, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X22, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X24, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X0, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X8, X9, [X29, #968]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X28, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a4720 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X27, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X0, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X1, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a4740 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 465638 <.omp_outlined..20+0xa8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X13, X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MADD X11, X10, X27, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X15, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X14, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X26, X9, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X20, X13, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X12, X9, X27, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X16, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X23, X15, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X21, X8, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 465658 <.omp_outlined..20+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X21, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X23, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X26, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X11, X10, X27, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X12, X9, X27, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDUR X13, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X13, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X24, XZR, X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X11, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X11, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X25, XZR, X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4656b8 <.omp_outlined..20+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
LDR X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X9, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X19, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X10, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X9, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X10, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X10, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X10, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X10, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X10, X11, [X29, #912]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X10, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.LT 46575c <.omp_outlined..20+0x1cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP XZR, XZR, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X9, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X22, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X22, [X8, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X28, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X9, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X30, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 465ac4 <.omp_outlined..20+0x534>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X22, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 466070 <.omp_outlined..20+0xae0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X18, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 465810 <.omp_outlined..20+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
CMP X22, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 466070 <.omp_outlined..20+0xae0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X20, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X5, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X8, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X8, X21, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X8, X9, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 465b6c <.omp_outlined..20+0x5dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDR X19, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X0, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X2, X29, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X9, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4a5310 <hypre_prefix_sum_pair>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X12, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4660d8 <.omp_outlined..20+0xb48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X11, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X8, X28, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 466114 <.omp_outlined..20+0xb84>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
LDR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <4de118>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #560	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W27, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4de130>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #584	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f9f0 <@plt_start@+0x590>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W0, 46619c <.omp_outlined..20+0xc0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X9, 466170 <.omp_outlined..20+0xbe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X0, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2500 <hypre_MAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X8, 46618c <.omp_outlined..20+0xbfc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X0, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2500 <hypre_MAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4de190>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #584	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f920 <@plt_start@+0x4c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4de1a0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #608	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X30, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X9, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X8, X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X22, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 466258 <.omp_outlined..20+0xcc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X10, X9, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORN X11, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X14, X22, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X11, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X12, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X13, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 466228 <.omp_outlined..20+0xc98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
ORR X9, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X22, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 466c00 <.omp_outlined..20+0x1670>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X12, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X12, X13, #60, #59	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X10, X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 4662e0 <.omp_outlined..20+0xd50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X11, X13, #63, #62	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X11, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X11, X11, #4157	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X10, X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 4662e0 <.omp_outlined..20+0xd50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X10, X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X10, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X28, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 466620 <.omp_outlined..20+0x1090>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X11, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X9, X10, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X12, X15, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X13, X14, [X29, #912]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X16, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 46634c <.omp_outlined..20+0xdbc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X12, X13, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X26, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X8, X20, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X8, X23, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X21, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4666ac <.omp_outlined..20+0x111c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDP X20, X19, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	par_strength.c:1668-2230
Module	exec

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 75.17 to 4.50 cycles (16.70x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 1516 bytes. The binary function is storing 488 bytes.

General properties

nb instructions	439
loop length	1756
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

45.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	16.00	16.00	28.25	28.25	28.25	28.25	0.00	0.00	0.00	0.00	75.17	74.83	75.00	25.50	25.50
cycles	16.00	16.00	28.25	28.25	28.25	28.25	0.00	0.00	0.00	0.00	75.17	74.83	75.00	25.50	25.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	45.13
Overall L1	75.17

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 75.17 cycles. At this rate:

21% of peak load performance is reached (20.17 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.49 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 465590

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #288	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X8, X9, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORR X22, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X24, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X0, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X8, X9, [X29, #968]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X28, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a4720 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X2, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X27, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X0, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X1, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a4740 <hypre_GetSimpleThreadPartition>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 465638 <.omp_outlined..20+0xa8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X13, X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MADD X11, X10, X27, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X15, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X14, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X26, X9, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X20, X13, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X12, X9, X27, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X16, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X23, X15, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X21, X8, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 465658 <.omp_outlined..20+0xc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X10, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X21, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X23, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X26, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X11, X10, X27, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X12, X9, X27, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDUR X13, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X13, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X24, XZR, X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDUR X11, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X11, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X25, XZR, X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4656b8 <.omp_outlined..20+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
LDR X9, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X29, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X9, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X19, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X10, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X9, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X10, [X29, #392]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X10, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X10, [X29, #384]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X10, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X10, X11, [X29, #912]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X10, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.LT 46575c <.omp_outlined..20+0x1cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP XZR, XZR, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X9, X27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X22, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X22, [X8, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X28, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X9, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X30, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 465ac4 <.omp_outlined..20+0x534>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X22, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 466070 <.omp_outlined..20+0xae0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X18, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 465810 <.omp_outlined..20+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
CMP X22, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 466070 <.omp_outlined..20+0xae0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X20, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X2, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X5, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X8, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X8, X21, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X8, X9, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 465b6c <.omp_outlined..20+0x5dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDR X19, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X0, X29, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X2, X29, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X9, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4a5310 <hypre_prefix_sum_pair>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X12, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4660d8 <.omp_outlined..20+0xb48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X11, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X8, X28, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 466114 <.omp_outlined..20+0xb84>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
LDR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADRP X0, <4de118>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #560	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W27, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4de130>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #584	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f9f0 <@plt_start@+0x590>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W0, 46619c <.omp_outlined..20+0xc0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X9, 466170 <.omp_outlined..20+0xbe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X0, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2500 <hypre_MAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X8, 46618c <.omp_outlined..20+0xbfc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X0, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2500 <hypre_MAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR X0, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4de190>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #584	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f920 <@plt_start@+0x4c0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W1, WZR, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4de1a0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #608	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 40f4b0 <@plt_start@+0x50>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X30, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X9, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X8, X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X22, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 466258 <.omp_outlined..20+0xcc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X10, X9, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ORN X11, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X14, X22, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X11, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X12, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X13, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 466228 <.omp_outlined..20+0xc98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
ORR X9, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X22, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 466c00 <.omp_outlined..20+0x1670>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X10, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X12, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X12, X13, #60, #59	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X10, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X10, X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 4662e0 <.omp_outlined..20+0xd50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UBFM X11, X13, #63, #62	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X11, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X11, X11, #4157	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X10, X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 4662e0 <.omp_outlined..20+0xd50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X10, X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ W10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X10, [X8, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #424]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X28, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 466620 <.omp_outlined..20+0x1090>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X8, X11, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X9, X10, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X12, X15, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X13, X14, [X29, #912]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X16, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 46634c <.omp_outlined..20+0xdbc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X12, X13, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #376]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X26, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X8, X20, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X8, X23, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X21, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 4666ac <.omp_outlined..20+0x111c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
LDP X20, X19, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #384	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼.omp_outlined..20#0x465590–	1.67	0.63
○Loop 1096 - par_strength.c:1691-1693 - exec	0.29	0.1
○Loop 1077 - par_strength.c:1951-1953 - exec	0.03	0.01
▼Loop 1059 - par_strength.c:2095-2230 - exec–	0	0
▼Loop 1060 - par_strength.c:2095-2230 - exec–	0	0
▼Loop 1058 - par_strength.c:2095-2230 - exec–	0	0
○Loop 1067 - par_strength.c:2224-2230 - exec	0	0
▼Loop 1064 - par_strength.c:2106-2158 - exec–	0	0
○Loop 1066 - par_strength.c:2124-2139 - exec	0	0
○Loop 1065 - par_strength.c:2143-2158 - exec	0	0
▼Loop 1061 - par_strength.c:2163-2211 - exec–	0	0
○Loop 1062 - par_strength.c:2199-2211 - exec	0	0
○Loop 1063 - par_strength.c:2181-2195 - exec	0	0
○Loop 1075 - par_strength.c:1978-1984 - exec	0	0
○Loop 1076 - par_strength.c:1955-1957 - exec	0	0
▼Loop 1094 - par_strength.c:1714-1797 - exec–	0	0
▼Loop 1089 - par_strength.c:1714-1797 - exec–	0	0
▼Loop 1088 - par_strength.c:1714-1770 - exec–	0.01	0.01
▼Loop 1090 - par_strength.c:1731-1765 - exec–	0.1	0.03
○Loop 1092 - par_strength.c:1743-1752 - exec	0.59	0.19
○Loop 1091 - par_strength.c:1756-1765 - exec	0	0
○Loop 1093 - par_strength.c:1791-1797 - exec	0	0
○Loop 1095 - par_strength.c:1695-1697 - exec	0	0
▼Loop 1070 - par_strength.c:2000-2083 - exec–	0	0
▼Loop 1069 - par_strength.c:2000-2083 - exec–	0	0
○Loop 1074 - par_strength.c:2076-2083 - exec	0	0
▼Loop 1068 - par_strength.c:2000-2053 - exec–	0	0
▼Loop 1071 - par_strength.c:2011-2048 - exec–	0.08	0.03
○Loop 1073 - par_strength.c:2024-2034 - exec	0.56	0.18
○Loop 1072 - par_strength.c:2038-2048 - exec	0	0
▼Loop 1079 - par_strength.c:1806-1941 - exec–	0	0
▼Loop 1080 - par_strength.c:1806-1941 - exec–	0	0
▼Loop 1078 - par_strength.c:1806-1941 - exec–	0	0
○Loop 1087 - par_strength.c:1935-1941 - exec	0	0
▼Loop 1084 - par_strength.c:1823-1872 - exec–	0	0
○Loop 1086 - par_strength.c:1840-1854 - exec	0	0
○Loop 1085 - par_strength.c:1858-1872 - exec	0	0
▼Loop 1081 - par_strength.c:1877-1922 - exec–	0	0
○Loop 1082 - par_strength.c:1911-1922 - exec	0	0
○Loop 1083 - par_strength.c:1894-1907 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

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Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code