OV - exec - Function .omp_outlined..20#0x4354e0

	Function: .omp_outlined..20#0x4354e0	Module: exec	Source: par_multi_interp.c:1575-1663 [...]	Coverage: 2.01%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1575 - 1663

--------------------------------------------------------------------------------

1575: #pragma omp parallel private(thread_start,thread_stop,my_thread_num,num_threads,k,k1,i,i1,j,j1,sum_C,sum_N,j_start,j_end,cnt,tmp_marker,tmp_marker_offd,cnt_offd,diagonal,alfa)

[...]

1585:            if (n_fine)

1586:            {   tmp_marker = hypre_CTAlloc(HYPRE_Int,n_fine); }

1587:            tmp_marker_offd = NULL;

1588:            if (num_cols_offd)

1589:            {   tmp_marker_offd = hypre_CTAlloc(HYPRE_Int,num_cols_offd); }

1590:            for (i=0; i < n_fine; i++)

1591:            {   tmp_marker[i] = -1; }

1592:            for (i=0; i < num_cols_offd; i++)

1593:            {   tmp_marker_offd[i] = -1; }

1594:

1595:            /* Compute this thread's range of pass_length */

1596:            my_thread_num = hypre_GetThreadNum();

1597:            num_threads = hypre_NumActiveThreads();

1598:            thread_start = pass_pointer[1] + (pass_length/num_threads)*my_thread_num;

1599:            if (my_thread_num == num_threads-1)

[...]

1605:            for (i=thread_start; i < thread_stop; i++)

1606:            {

1607:              i1 = pass_array[i];

1608:              sum_C = 0;

1609:              sum_N = 0;

1610:              j_start = P_diag_start[i1];

1611:              j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1612:              for (j=j_start; j < j_end; j++)

1613:              {

1614:                 k1 = P_diag_pass[1][j];

1615:                 tmp_marker[C_array[k1]] = i1;

1616:              }

1617:              cnt = P_diag_i[i1];

1618:              for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1619:              {

1620:                 j1 = A_diag_j[j];

1621:                 if (CF_marker[j1] != -3 &&

1622:                    (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1623:                    sum_N += A_diag_data[j];

1624:                 if (j1 != -1 && tmp_marker[j1] == i1)

1625:                 {

1626:                    P_diag_data[cnt] = A_diag_data[j];

1627:                    P_diag_j[cnt++] = fine_to_coarse[j1];

1628:                    sum_C += A_diag_data[j];

1629:                 }

1630:              }

1631:              j_start = P_offd_start[i1];

1632:              j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1633:              for (j=j_start; j < j_end; j++)

1634:              {

1635:                 k1 = P_offd_pass[1][j];

1636:                 tmp_marker_offd[C_array_offd[k1]] = i1;

1637:              }

1638:              cnt_offd = P_offd_i[i1];

1639:              for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

1640:              {

1641:                 if (col_offd_S_to_A)

1642:                     j1 = map_A_to_S[A_offd_j[j]];

1643:                 else

1644:                     j1 = A_offd_j[j];

1645:                 if (CF_marker_offd[j1] != -3 &&

1646:                   (num_functions == 1 || dof_func[i1] == dof_func_offd[j1]))

1647:                     sum_N += A_offd_data[j];

1648:                 if (j1 != -1 && tmp_marker_offd[j1] == i1)

1649:                 {

1650:                    P_offd_data[cnt_offd] = A_offd_data[j];

1651:                    P_offd_j[cnt_offd++] = map_S_to_new[j1];

1652:                    sum_C += A_offd_data[j];

1653:                 }

1654:              }

1655:              diagonal = A_diag_data[A_diag_i[i1]];

1656:              if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1657:              for (j=P_diag_i[i1]; j < cnt; j++)

1658:                 P_diag_data[j] *= alfa;

1659:              for (j=P_offd_i[i1]; j < cnt_offd; j++)

1660:                 P_offd_data[j] *= alfa;

1661:           }

1662:           hypre_TFree(tmp_marker);

1663:           hypre_TFree(tmp_marker_offd);

0x4354e0 SUB	SP, SP, #320

0x4354e4 STP	X29, X30, [SP, #224]

0x4354e8 STP	X28, X27, [SP, #240]

0x4354ec STP	X26, X25, [SP, #256]

0x4354f0 STP	X24, X23, [SP, #272]

0x4354f4 STP	X22, X21, [SP, #288]

0x4354f8 STP	X20, X19, [SP, #304]

0x4354fc ADD	X29, SP, #224

0x435500 STUR	X7, [X29, #480]

0x435504 STUR	X6, [X29, #456]

0x435508 LDR	X0, [X2]

0x43550c ORR	X24, XZR, X5

0x435510 ORR	X25, XZR, X3

0x435514 ORR	X26, XZR, X2

0x435518 STR	X4, [SP, #72]

0x43551c LDP	X8, X9, [X29, #288]

0x435520 STP	X8, X9, [X29, #928]

0x435524 LDR	X8, [X29, #280]

0x435528 STUR	X8, [X29, #448]

0x43552c LDR	X8, [X29, #272]

0x435530 STUR	X8, [X29, #408]

0x435534 LDR	X8, [X29, #264]

0x435538 STR	X8, [SP, #112]

0x43553c LDP	X8, X22, [X29, #248]

0x435540 STR	X8, [SP, #104]

0x435544 LDR	X8, [X29, #240]

0x435548 STR	X8, [SP, #96]

0x43554c LDP	X9, X8, [X29, #208]

0x435550 LDP	X28, X27, [X29, #224]

0x435554 STUR	X8, [X29, #496]

0x435558 LDR	X8, [X29, #200]

0x43555c STP	X9, X8, [X29, #976]

0x435560 LDR	X8, [X29, #192]

0x435564 STR	X8, [SP, #40]

0x435568 LDR	X8, [X29, #184]

0x43556c STR	X8, [SP, #88]

0x435570 LDR	X8, [X29, #176]

0x435574 STR	X8, [SP, #80]

0x435578 LDP	X8, X9, [X29, #160]

0x43557c STP	X8, X9, [X29, #944]

0x435580 LDP	X23, X8, [X29, #144]

0x435584 STUR	X8, [X29, #488]

0x435588 LDR	X8, [X29, #136]

0x43558c STR	X8, [SP, #32]

0x435590 LDR	X8, [X29, #128]

0x435594 STR	X8, [SP, #24]

0x435598 LDR	X8, [X29, #120]

0x43559c STR	X8, [SP, #16]

0x4355a0 LDR	X8, [X29, #112]

0x4355a4 STR	X8, [SP, #8]

0x4355a8 LDR	X8, [X29, #104]

0x4355ac STR	X8, [SP, #48]

0x4355b0 LDR	X21, [X29, #96]

0x4355b4 CBZ	X0, 4355e8

0x4355b8 MOVZ	W1, #8

0x4355bc BL	4a2570

0x4355c0 ORR	X19, XZR, X0

0x4355c4 LDR	X0, [X25]

0x4355c8 CBZ	X0, 4355f4

0x4355cc MOVZ	W1, #8

0x4355d0 BL	4a2570

0x4355d4 ORR	X20, XZR, X0

0x4355d8 LDR	X8, [X26]

0x4355dc CMP	X8, #1

0x4355e0 B.GE	435604

0x4355e4 B	435620

0x4355e8 ORR	X19, XZR, XZR

0x4355ec LDR	X0, [X25]

0x4355f0 CBNZ	X0, 4355cc

0x4355f4 ORR	X20, XZR, XZR

0x4355f8 LDR	X8, [X26]

0x4355fc CMP	X8, #1

0x435600 B.LT	435620

0x435604 ORR	X8, XZR, XZR

0x435608 MOVN	X9, #0

(1120) 0x43560c STR	X9, [X19, X8,LSL #3]

(1120) 0x435610 ADD	X8, X8, #1

(1120) 0x435614 LDR	X10, [X26]

(1120) 0x435618 CMP	X8, X10

(1120) 0x43561c B.LT	43560c

0x435620 LDR	X8, [X25]

0x435624 CMP	X8, #1

0x435628 B.LT	435654

0x43562c ORR	X8, XZR, XZR

0x435630 MOVN	X9, #0

0x435634 HINT	#0

0x435638 HINT	#0

0x43563c HINT	#0

(1121) 0x435640 STR	X9, [X20, X8,LSL #3]

(1121) 0x435644 ADD	X8, X8, #1

(1121) 0x435648 LDR	X10, [X25]

(1121) 0x43564c CMP	X8, X10

(1121) 0x435650 B.LT	435640

0x435654 BL	4a4720

0x435658 ORR	X25, XZR, X0

0x43565c BL	4a4700

0x435660 LDR	X9, [X24]

0x435664 SUB	X11, X0, #1

0x435668 CMP	X25, X11

0x43566c SDIV	X10, X9, X0

0x435670 MADD	X8, X10, X25, XZR

0x435674 ADD	X10, X10, X8

0x435678 CSEL	X9, X9, X10, #0

0x43567c CMP	X8, X9

0x435680 B.GE	435c70

0x435684 LDUR	X11, [X29, #456]

0x435688 LDR	X10, [SP, #72]

0x43568c ORR	X16, XZR, X28

0x435690 LDR	X28, [X21]

0x435694 LDR	X4, [X27]

0x435698 LDR	X5, [X22]

0x43569c LDR	X17, [X11]

0x4356a0 LDUR	X11, [X29, #480]

0x4356a4 LDR	X10, [X10]

0x4356a8 LDR	X3, [X11]

0x4356ac LDR	X11, [SP, #48]

0x4356b0 LDR	X10, [X10, #8]

0x4356b4 LDR	X11, [X11]

0x4356b8 ADD	X0, X8, X10

0x4356bc ADD	X9, X9, X10

0x4356c0 STR	X11, [SP, #48]

0x4356c4 LDR	X11, [SP, #8]

0x4356c8 LDUR	X8, [X29, #464]

0x4356cc LDR	X12, [X11]

0x4356d0 LDR	X11, [SP, #16]

0x4356d4 LDR	X8, [X8]

0x4356d8 LDR	X13, [X11]

0x4356dc LDR	X11, [SP, #24]

0x4356e0 LDR	X14, [X11]

0x4356e4 LDR	X11, [SP, #32]

0x4356e8 LDR	X15, [X11]

0x4356ec LDR	X11, [SP, #40]

0x4356f0 LDR	X10, [X11]

0x4356f4 LDUR	X11, [X29, #472]

0x4356f8 STP	X9, X10, [X29, #984]

0x4356fc STR	X8, [SP, #40]

0x435700 LDUR	X8, [X29, #496]

0x435704 LDR	X6, [X11]

0x435708 LDR	X2, [X8]

0x43570c LDR	X8, [X16]

0x435710 STUR	X8, [X29, #496]

0x435714 LDUR	X8, [X29, #432]

0x435718 LDR	X8, [X8]

0x43571c STUR	X8, [X29, #464]

0x435720 LDUR	X8, [X29, #440]

0x435724 LDR	X7, [X8]

0x435728 LDUR	X8, [X29, #448]

0x43572c LDR	X24, [X8]

0x435730 ADD	X9, X7, #16

0x435734 ADD	X8, X24, #16

0x435738 STP	X8, X9, [SP, #24]

0x43573c STUR	X6, [X29, #456]

0x435740 STP	X3, X17, [SP, #64]

0x435744 STR	X28, [SP, #56]

0x435748 B	43575c

  (1107) 0x43574c LDUR	X8, [X29, #472]

  (1107) 0x435750 ADD	X0, X0, #1

  (1107) 0x435754 CMP	X0, X8

  (1107) 0x435758 B.GE	435c70

  (1107) 0x43575c LDR	X30, [X17, X0,LSL #3]

  (1107) 0x435760 ADD	X26, X30, #1

  (1107) 0x435764 LDR	X8, [X3, X30,LSL #3]

  (1107) 0x435768 LDR	X25, [X28, X30,LSL #3]

  (1107) 0x43576c LDR	X9, [X28, X26,LSL #3]

  (1107) 0x435770 ADD	X10, X9, X8

  (1107) 0x435774 SUB	X10, X10, X25

  (1107) 0x435778 CMP	X8, X10

  (1107) 0x43577c B.GE	435840

  (1107) 0x435780 LDR	X10, [SP, #48]

  (1107) 0x435784 LDR	X11, [X10, #8]

  (1107) 0x435788 SUB	W10, W9, W25

  (1107) 0x43578c ANDS	X16, X10, #4160

  (1107) 0x435790 B.EQ	4357cc

  (1107) 0x435794 ORR	X10, XZR, X8

  (1107) 0x435798 HINT	#0

  (1107) 0x43579c HINT	#0

    (1115) 0x4357a0 LDR	X18, [X11, X10,LSL #3]

    (1115) 0x4357a4 ADD	X10, X10, #1

    (1115) 0x4357a8 SUBS	X16, X16, #1

    (1115) 0x4357ac LDR	X18, [X12, X18,LSL #3]

    (1115) 0x4357b0 STR	X30, [X19, X18,LSL #3]

    (1115) 0x4357b4 B.NE	4357a0

  (1107) 0x4357b8 ORN	X16, XZR, X25

  (1107) 0x4357bc ADD	X16, X9, X16

  (1107) 0x4357c0 CMP	X16, #3

  (1107) 0x4357c4 B.CS	4357e0

  (1107) 0x4357c8 B	43583c

  (1107) 0x4357cc ORR	X10, XZR, X8

  (1107) 0x4357d0 ORN	X16, XZR, X25

  (1107) 0x4357d4 ADD	X16, X9, X16

  (1107) 0x4357d8 CMP	X16, #3

  (1107) 0x4357dc B.CC	43583c

  (1107) 0x4357e0 ADD	X8, X9, X8

  (1107) 0x4357e4 ADD	X9, X11, X10,LSL #3

  (1107) 0x4357e8 ADD	X9, X9, #16

  (1107) 0x4357ec SUB	X8, X8, X10

  (1107) 0x4357f0 SUB	X8, X8, X25

  (1107) 0x4357f4 HINT	#0

  (1107) 0x4357f8 HINT	#0

  (1107) 0x4357fc HINT	#0

    (1114) 0x435800 LDUR	X10, [X9, #496]

    (1114) 0x435804 SUBS	X8, X8, #4

    (1114) 0x435808 LDR	X10, [X12, X10,LSL #3]

    (1114) 0x43580c STR	X30, [X19, X10,LSL #3]

    (1114) 0x435810 LDUR	X10, [X9, #504]

    (1114) 0x435814 LDR	X10, [X12, X10,LSL #3]

    (1114) 0x435818 STR	X30, [X19, X10,LSL #3]

    (1114) 0x43581c LDR	X10, [X9]

    (1114) 0x435820 LDR	X10, [X12, X10,LSL #3]

    (1114) 0x435824 STR	X30, [X19, X10,LSL #3]

    (1114) 0x435828 LDR	X10, [X9, #8]

    (1114) 0x43582c ADD	X9, X9, #32

    (1114) 0x435830 LDR	X10, [X12, X10,LSL #3]

    (1114) 0x435834 STR	X30, [X19, X10,LSL #3]

    (1114) 0x435838 B.NE	435800

  (1107) 0x43583c LDR	X25, [X28, X30,LSL #3]

  (1107) 0x435840 LDR	X8, [X13, X30,LSL #3]

  (1107) 0x435844 LDR	X16, [X13, X26,LSL #3]

  (1107) 0x435848 MOVI	D2, #0

  (1107) 0x43584c ADD	X8, X8, #1

  (1107) 0x435850 CMP	X8, X16

  (1107) 0x435854 B.GE	435904

  (1107) 0x435858 LDUR	X10, [X29, #432]

  (1107) 0x43585c LDUR	X9, [X29, #488]

  (1107) 0x435860 MOVI	D1, #0

  (1107) 0x435864 MOVI	D2, #0

  (1107) 0x435868 LDR	X11, [X10]

  (1107) 0x43586c LDUR	X10, [X29, #440]

  (1107) 0x435870 LDR	X9, [X9]

  (1107) 0x435874 LDR	X18, [X10]

  (1107) 0x435878 LDR	X10, [SP, #88]

  (1107) 0x43587c LDR	X1, [X10]

  (1107) 0x435880 LDR	X10, [SP, #80]

  (1107) 0x435884 LDR	X6, [X10]

  (1107) 0x435888 B	435898

    (1113) 0x43588c ADD	X8, X8, #1

    (1113) 0x435890 CMP	X8, X16

    (1113) 0x435894 B.GE	43590c

    (1113) 0x435898 LDR	X21, [X14, X8,LSL #3]

    (1113) 0x43589c LDR	X10, [X15, X21,LSL #3]

    (1113) 0x4358a0 CMN	X10, #3

    (1113) 0x4358a4 B.EQ	4358cc

    (1113) 0x4358a8 LDR	X10, [X23]

    (1113) 0x4358ac CMP	X10, #1

    (1113) 0x4358b0 B.EQ	4358c4

    (1113) 0x4358b4 LDR	X10, [X9, X30,LSL #3]

    (1113) 0x4358b8 LDR	X22, [X9, X21,LSL #3]

    (1113) 0x4358bc CMP	X10, X22

    (1113) 0x4358c0 B.NE	4358cc

    (1113) 0x4358c4 LDR	D3, [X11, X8,LSL #3]

    (1113) 0x4358c8 FADD	D1, D1, D3

    (1113) 0x4358cc CMN	X21, #1

    (1113) 0x4358d0 B.EQ	43588c

    (1113) 0x4358d4 LDR	X10, [X19, X21,LSL #3]

    (1113) 0x4358d8 CMP	X10, X30

    (1113) 0x4358dc B.NE	43588c

    (1113) 0x4358e0 LDR	D3, [X11, X8,LSL #3]

    (1113) 0x4358e4 LDR	X10, [X1, X21,LSL #3]

    (1113) 0x4358e8 STR	X10, [X6, X25,LSL #3]

    (1113) 0x4358ec LDR	X16, [X13, X26,LSL #3]

    (1113) 0x4358f0 STR	D3, [X18, X25,LSL #3]

    (1113) 0x4358f4 ADD	X25, X25, #1

    (1113) 0x4358f8 LDR	D3, [X11, X8,LSL #3]

    (1113) 0x4358fc FADD	D2, D2, D3

    (1113) 0x435900 B	43588c

  (1107) 0x435904 MOVI	D1, #0

  (1107) 0x435908 B	435910

  (1107) 0x43590c LDUR	X6, [X29, #456]

  (1107) 0x435910 LDUR	X8, [X29, #480]

  (1107) 0x435914 LDR	X9, [X6, X26,LSL #3]

  (1107) 0x435918 LDR	X21, [X6, X30,LSL #3]

  (1107) 0x43591c LDR	X8, [X8, X30,LSL #3]

  (1107) 0x435920 ADD	X10, X9, X8

  (1107) 0x435924 SUB	X10, X10, X21

  (1107) 0x435928 CMP	X8, X10

  (1107) 0x43592c B.LT	4359ac

  (1107) 0x435930 LDUR	X8, [X29, #496]

  (1107) 0x435934 LDR	X27, [X8, X30,LSL #3]

  (1107) 0x435938 LDR	X1, [X8, X26,LSL #3]

  (1107) 0x43593c CMP	X27, X1

  (1107) 0x435940 B.LT	435b14

  (1107) 0x435944 LDR	X8, [X13, X30,LSL #3]

  (1107) 0x435948 LDUR	X9, [X29, #464]

  (1107) 0x43594c LDR	D3, [X9, X8,LSL #3]

  (1107) 0x435950 FMUL	D2, D2, D3

  (1107) 0x435954 FCMP	D2, #0

  (1107) 0x435958 B.EQ	435964

  (1108) 0x43595c FNEG	D0, D1

  (1108) 0x435960 FDIV	D0, D0, D2

  (1107) 0x435964 LDR	X8, [X28, X30,LSL #3]

  (1107) 0x435968 CMP	X25, X8

  (1107) 0x43596c B.LE	435a48

  (1107) 0x435970 SUB	W9, W25, W8

  (1107) 0x435974 ANDS	X10, X9, #4160

  (1107) 0x435978 B.EQ	4359f0

  (1107) 0x43597c ORR	X9, XZR, X8

    (1119) 0x435980 LDR	D1, [X7, X9,LSL #3]

    (1119) 0x435984 SUBS	X10, X10, #1

    (1119) 0x435988 FMUL	D1, D0, D1

    (1119) 0x43598c STR	D1, [X7, X9,LSL #3]

    (1119) 0x435990 ADD	X9, X9, #1

    (1119) 0x435994 B.NE	435980

  (1107) 0x435998 ORN	X8, XZR, X8

  (1107) 0x43599c ADD	X8, X25, X8

  (1107) 0x4359a0 CMP	X8, #3

  (1107) 0x4359a4 B.CS	435a04

  (1107) 0x4359a8 B	435a48

  (1107) 0x4359ac LDR	X10, [SP, #40]

  (1107) 0x4359b0 LDR	X11, [X10, #8]

  (1107) 0x4359b4 SUB	W10, W9, W21

  (1107) 0x4359b8 ANDS	X16, X10, #4160

  (1107) 0x4359bc B.EQ	435a90

  (1107) 0x4359c0 ORR	X10, XZR, X8

    (1112) 0x4359c4 LDR	X18, [X11, X10,LSL #3]

    (1112) 0x4359c8 ADD	X10, X10, #1

    (1112) 0x4359cc SUBS	X16, X16, #1

    (1112) 0x4359d0 LDR	X18, [X2, X18,LSL #3]

    (1112) 0x4359d4 STR	X30, [X20, X18,LSL #3]

    (1112) 0x4359d8 B.NE	4359c4

  (1107) 0x4359dc ORN	X16, XZR, X21

  (1107) 0x4359e0 ADD	X16, X9, X16

  (1107) 0x4359e4 CMP	X16, #3

  (1107) 0x4359e8 B.CS	435aa4

  (1107) 0x4359ec B	435afc

  (1107) 0x4359f0 ORR	X9, XZR, X8

  (1107) 0x4359f4 ORN	X8, XZR, X8

  (1107) 0x4359f8 ADD	X8, X25, X8

  (1107) 0x4359fc CMP	X8, #3

  (1107) 0x435a00 B.CC	435a48

  (1107) 0x435a04 LDR	X10, [SP, #32]

  (1107) 0x435a08 SUB	X8, X25, X9

  (1107) 0x435a0c ADD	X9, X10, X9,LSL #3

  (1107) 0x435a10 HINT	#0

  (1107) 0x435a14 HINT	#0

  (1107) 0x435a18 HINT	#0

  (1107) 0x435a1c HINT	#0

    (1118) 0x435a20 LDP	D1, D2, [X9, #1008]

    (1118) 0x435a24 SUBS	X8, X8, #4

    (1118) 0x435a28 FMUL	D2, D0, D2

    (1118) 0x435a2c FMUL	D1, D0, D1

    (1118) 0x435a30 STP	D1, D2, [X9, #1008]

    (1118) 0x435a34 LDP	D1, D2, [X9]

    (1118) 0x435a38 FMUL	D2, D0, D2

    (1118) 0x435a3c FMUL	D1, D0, D1

    (1118) 0x435a40 STP	D1, D2, [X9], #32

    (1118) 0x435a44 B.NE	435a20

  (1107) 0x435a48 LDR	X8, [X6, X30,LSL #3]

  (1107) 0x435a4c CMP	X21, X8

  (1107) 0x435a50 B.LE	43574c

  (1107) 0x435a54 SUB	W9, W21, W8

  (1107) 0x435a58 ANDS	X10, X9, #4160

  (1107) 0x435a5c B.EQ	435c24

  (1107) 0x435a60 ORR	X9, XZR, X8

    (1117) 0x435a64 LDR	D1, [X24, X9,LSL #3]

    (1117) 0x435a68 SUBS	X10, X10, #1

    (1117) 0x435a6c FMUL	D1, D0, D1

    (1117) 0x435a70 STR	D1, [X24, X9,LSL #3]

    (1117) 0x435a74 ADD	X9, X9, #1

    (1117) 0x435a78 B.NE	435a64

  (1107) 0x435a7c ORN	X8, XZR, X8

  (1107) 0x435a80 ADD	X8, X21, X8

  (1107) 0x435a84 CMP	X8, #3

  (1107) 0x435a88 B.CC	43574c

  (1107) 0x435a8c B	435c38

  (1107) 0x435a90 ORR	X10, XZR, X8

  (1107) 0x435a94 ORN	X16, XZR, X21

  (1107) 0x435a98 ADD	X16, X9, X16

  (1107) 0x435a9c CMP	X16, #3

  (1107) 0x435aa0 B.CC	435afc

  (1107) 0x435aa4 ADD	X8, X9, X8

  (1107) 0x435aa8 ADD	X9, X11, X10,LSL #3

  (1107) 0x435aac ADD	X9, X9, #16

  (1107) 0x435ab0 SUB	X8, X8, X10

  (1107) 0x435ab4 SUB	X8, X8, X21

  (1107) 0x435ab8 HINT	#0

  (1107) 0x435abc HINT	#0

    (1111) 0x435ac0 LDUR	X10, [X9, #496]

    (1111) 0x435ac4 SUBS	X8, X8, #4

    (1111) 0x435ac8 LDR	X10, [X2, X10,LSL #3]

    (1111) 0x435acc STR	X30, [X20, X10,LSL #3]

    (1111) 0x435ad0 LDUR	X10, [X9, #504]

    (1111) 0x435ad4 LDR	X10, [X2, X10,LSL #3]

    (1111) 0x435ad8 STR	X30, [X20, X10,LSL #3]

    (1111) 0x435adc LDR	X10, [X9]

    (1111) 0x435ae0 LDR	X10, [X2, X10,LSL #3]

    (1111) 0x435ae4 STR	X30, [X20, X10,LSL #3]

    (1111) 0x435ae8 LDR	X10, [X9, #8]

    (1111) 0x435aec ADD	X9, X9, #32

    (1111) 0x435af0 LDR	X10, [X2, X10,LSL #3]

    (1111) 0x435af4 STR	X30, [X20, X10,LSL #3]

    (1111) 0x435af8 B.NE	435ac0

  (1107) 0x435afc LDR	X21, [X6, X30,LSL #3]

  (1107) 0x435b00 LDUR	X8, [X29, #496]

  (1107) 0x435b04 LDR	X27, [X8, X30,LSL #3]

  (1107) 0x435b08 LDR	X1, [X8, X26,LSL #3]

  (1107) 0x435b0c CMP	X27, X1

  (1107) 0x435b10 B.GE	435944

(1109) 0x435b14 LDR	X8, [SP, #96]

(1109) 0x435b18 LDUR	X9, [X29, #448]

(1109) 0x435b1c LDUR	X16, [X29, #424]

(1109) 0x435b20 LDR	X28, [X8]

(1109) 0x435b24 LDR	X8, [SP, #104]

(1109) 0x435b28 LDR	X9, [X9]

(1109) 0x435b2c LDR	X16, [X16]

(1109) 0x435b30 LDR	X10, [X8]

(1109) 0x435b34 LDUR	X8, [X29, #488]

(1109) 0x435b38 LDR	X11, [X8]

(1109) 0x435b3c LDR	X8, [SP, #112]

(1109) 0x435b40 ADD	X6, X10, X27,LSL #3

(1109) 0x435b44 LDR	X22, [X8]

(1109) 0x435b48 LDP	X8, X17, [X29, #920]

(1109) 0x435b4c LDR	X8, [X8]

(1109) 0x435b50 LDR	X18, [X17]

(1109) 0x435b54 B	435b70

0x435b58 HINT	#0

0x435b5c HINT	#0

  (1110) 0x435b60 ADD	X27, X27, #1

  (1110) 0x435b64 ADD	X6, X6, #8

  (1110) 0x435b68 CMP	X27, X1

  (1110) 0x435b6c B.GE	435c00

  (1110) 0x435b70 ORR	X10, XZR, X6

  (1110) 0x435b74 CBZ	X4, 435b80

  (1110) 0x435b78 LDR	X10, [X6]

  (1110) 0x435b7c ADD	X10, X28, X10,LSL #3

  (1110) 0x435b80 LDR	X10, [X10]

  (1110) 0x435b84 LDR	X17, [X5, X10,LSL #3]

  (1110) 0x435b88 CMN	X17, #3

  (1110) 0x435b8c B.EQ	435bb4

  (1110) 0x435b90 LDR	X17, [X23]

  (1110) 0x435b94 CMP	X17, #1

  (1110) 0x435b98 B.EQ	435bac

  (1110) 0x435b9c LDR	X17, [X11, X30,LSL #3]

  (1110) 0x435ba0 LDR	X3, [X22, X10,LSL #3]

  (1110) 0x435ba4 CMP	X17, X3

  (1110) 0x435ba8 B.NE	435bb4

  (1110) 0x435bac LDR	D3, [X8, X27,LSL #3]

  (1110) 0x435bb0 FADD	D1, D1, D3

  (1110) 0x435bb4 CMN	X10, #1

  (1110) 0x435bb8 B.EQ	435b60

  (1110) 0x435bbc LDR	X17, [X20, X10,LSL #3]

  (1110) 0x435bc0 CMP	X17, X30

  (1110) 0x435bc4 B.NE	435b60

  (1110) 0x435bc8 LDR	D3, [X8, X27,LSL #3]

  (1110) 0x435bcc LDR	X10, [X16, X10,LSL #3]

  (1110) 0x435bd0 STR	X10, [X18, X21,LSL #3]

  (1110) 0x435bd4 LDUR	X10, [X29, #496]

  (1110) 0x435bd8 STR	D3, [X9, X21,LSL #3]

  (1110) 0x435bdc ADD	X21, X21, #1

  (1110) 0x435be0 LDR	D3, [X8, X27,LSL #3]

  (1110) 0x435be4 LDR	X1, [X10, X26,LSL #3]

  (1110) 0x435be8 FADD	D2, D2, D3

  (1110) 0x435bec B	435b60

0x435bf0 HINT	#0

0x435bf4 HINT	#0

0x435bf8 HINT	#0

0x435bfc HINT	#0

(1109) 0x435c00 LDP	X3, X17, [SP, #64]

(1109) 0x435c04 LDR	X28, [SP, #56]

(1109) 0x435c08 LDP	X6, X9, [X29, #968]

(1109) 0x435c0c LDR	X8, [X13, X30,LSL #3]

(1109) 0x435c10 LDR	D3, [X9, X8,LSL #3]

(1109) 0x435c14 FMUL	D2, D2, D3

(1109) 0x435c18 FCMP	D2, #0

(1109) 0x435c1c B.NE	43595c

(1109) 0x435c20 B	435964

  (1107) 0x435c24 ORR	X9, XZR, X8

  (1107) 0x435c28 ORN	X8, XZR, X8

  (1107) 0x435c2c ADD	X8, X21, X8

  (1107) 0x435c30 CMP	X8, #3

  (1107) 0x435c34 B.CC	43574c

  (1107) 0x435c38 LDR	X10, [SP, #24]

  (1107) 0x435c3c SUB	X8, X21, X9

  (1107) 0x435c40 ADD	X9, X10, X9,LSL #3

    (1116) 0x435c44 LDP	D1, D2, [X9, #1008]

    (1116) 0x435c48 SUBS	X8, X8, #4

    (1116) 0x435c4c FMUL	D2, D0, D2

    (1116) 0x435c50 FMUL	D1, D0, D1

    (1116) 0x435c54 STP	D1, D2, [X9, #1008]

    (1116) 0x435c58 LDP	D1, D2, [X9]

    (1116) 0x435c5c FMUL	D2, D0, D2

    (1116) 0x435c60 FMUL	D1, D0, D1

    (1116) 0x435c64 STP	D1, D2, [X9], #32

    (1116) 0x435c68 B.NE	435c44

  (1107) 0x435c6c B	43574c

0x435c70 ORR	X0, XZR, X19

0x435c74 BL	4a2670

0x435c78 ORR	X0, XZR, X20

0x435c7c LDP	X20, X19, [SP, #304]

0x435c80 LDP	X22, X21, [SP, #288]

0x435c84 LDP	X24, X23, [SP, #272]

0x435c88 LDP	X26, X25, [SP, #256]

0x435c8c LDP	X28, X27, [SP, #240]

0x435c90 LDP	X29, X30, [SP, #224]

0x435c94 ADD	SP, SP, #320

0x435c98 B	4a2670

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	par_multi_interp.c:1575-1663
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1575,1585-1599,1605-1663.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 34.67 to 10.00 cycles (3.47x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 34.67 to 2.50 cycles (13.87x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 640 bytes. The binary function is storing 384 bytes.

General properties

nb instructions	162
loop length	648
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

19.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	7.50	7.50	9.75	9.75	9.75	9.75	0.00	0.00	0.00	0.00	34.67	34.67	34.67	18.00	18.00
cycles	7.50	7.50	9.75	9.75	9.75	9.75	0.00	0.00	0.00	0.00	34.67	34.67	34.67	18.00	18.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	19.13
Overall L1	34.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 34.67 cycles. At this rate:

19% of peak load performance is reached (18.46 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
23% of peak store performance is reached (11.08 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4354e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #320	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X7, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X6, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X24, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X4, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X8, X9, [X29, #928]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X22, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X9, X8, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X9, X8, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X8, X9, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X23, X8, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X0, 4355e8 <.omp_outlined..20+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X0, 4355f4 <.omp_outlined..20+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 435604 <.omp_outlined..20+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 435620 <.omp_outlined..20+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X0, 4355cc <.omp_outlined..20+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 435620 <.omp_outlined..20+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 435654 <.omp_outlined..20+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
BL 4a4720 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a4700 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X11, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X25, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SDIV X10, X9, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
MADD X8, X10, X25, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X10, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X9, X9, X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 435c70 <.omp_outlined..20+0x790>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X11, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X16, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X28, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X11, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X11, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X11, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X11, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X9, X10, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X24, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X7, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X24, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X8, X9, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X6, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X3, X17, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X28, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 43575c <.omp_outlined..20+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X20, X19, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #320	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a2670 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	par_multi_interp.c:1575-1663
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1575,1585-1599,1605-1663.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 34.67 to 2.50 cycles (13.87x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 640 bytes. The binary function is storing 384 bytes.

General properties

nb instructions	162
loop length	648
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

19.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	7.50	7.50	9.75	9.75	9.75	9.75	0.00	0.00	0.00	0.00	34.67	34.67	34.67	18.00	18.00
cycles	7.50	7.50	9.75	9.75	9.75	9.75	0.00	0.00	0.00	0.00	34.67	34.67	34.67	18.00	18.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	19.13
Overall L1	34.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 34.67 cycles. At this rate:

19% of peak load performance is reached (18.46 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
23% of peak store performance is reached (11.08 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4354e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
SUB SP, SP, #320	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X29, X30, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X28, X27, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STUR X7, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X6, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X24, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X26, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X4, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X29, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X8, X9, [X29, #928]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #408]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X22, [X29, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X9, X8, [X29, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [X29, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X9, X8, [X29, #976]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X8, X9, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X8, X9, [X29, #944]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X23, X8, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STUR X8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X8, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X0, 4355e8 <.omp_outlined..20+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X0, 4355f4 <.omp_outlined..20+0x114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2570 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 435604 <.omp_outlined..20+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 435620 <.omp_outlined..20+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBNZ X0, 4355cc <.omp_outlined..20+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 435620 <.omp_outlined..20+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 435654 <.omp_outlined..20+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
BL 4a4720 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X25, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a4700 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X11, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X25, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SDIV X10, X9, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20
MADD X8, X10, X25, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X10, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL X9, X9, X10, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 435c70 <.omp_outlined..20+0x790>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR X11, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X16, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X28, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X5, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X17, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X11, [X29, #480]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X3, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X10, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X11, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X11, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X11, [X29, #472]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X9, X10, [X29, #984]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X8, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #496]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #432]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STUR X8, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDUR X8, [X29, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDUR X8, [X29, #448]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X24, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X7, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X24, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X8, X9, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STUR X6, [X29, #456]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X3, X17, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X28, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 43575c <.omp_outlined..20+0x27c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
HINT #0
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a2670 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X0, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X20, X19, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X28, X27, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD SP, SP, #320	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4a2670 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼.omp_outlined..20#0x4354e0–	2.01	0.76
○Loop 1120 - par_multi_interp.c:1590-1591 - exec	1.73	0.57
○Loop 1121 - par_multi_interp.c:1592-1593 - exec	0	0
▼Loop 1109 - par_multi_interp.c:1605-1660 - exec–	0	0
▼Loop 1107 - par_multi_interp.c:1605-1660 - exec–	0.05	0.02
○Loop 1113 - par_multi_interp.c:1618-1628 - exec	0.22	0.07
○Loop 1115 - par_multi_interp.c:1612-1615 - exec	0.01	0.01
○Loop 1111 - par_multi_interp.c:1633-1636 - exec	0	0
○Loop 1112 - par_multi_interp.c:1633-1636 - exec	0	0
○Loop 1119 - par_multi_interp.c:1657-1658 - exec	0	0
○Loop 1117 - par_multi_interp.c:1659-1660 - exec	0	0
○Loop 1118 - par_multi_interp.c:1657-1658 - exec	0	0
○Loop 1116 - par_multi_interp.c:1659-1660 - exec	0	0
○Loop 1114 - par_multi_interp.c:1612-1615 - exec	0	0
○Loop 1108 - par_multi_interp.c:1656-1656 - exec	0	0
○Loop 1110 - par_multi_interp.c:1639-1652 - exec	0	0

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Vectorization

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

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Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code