OV - exec - Function .omp_outlined..18#0x49a9a0

	Function: .omp_outlined..18#0x49a9a0	Module: exec	Source: csr_matvec.c:243-404 [...]	Coverage: 15.72%

/home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 243 - 404

--------------------------------------------------------------------------------

243: #pragma omp parallel private(i,jj,tempx)

244: #endif

245:       {

246:       HYPRE_Int iBegin = hypre_CSRMatrixGetLoadBalancedPartitionBegin(A);

247:       HYPRE_Int iEnd = hypre_CSRMatrixGetLoadBalancedPartitionEnd(A);

248:       hypre_assert(iBegin <= iEnd);

249:       hypre_assert(iBegin >= 0 && iBegin <= num_rows);

250:       hypre_assert(iEnd >= 0 && iEnd <= num_rows);

251:

252:       if (0 == temp)

253:       {

254:          if (1 == alpha) // JSP: a common path

255:          {

256:             for (i = iBegin; i < iEnd; i++)

257:             {

258:                tempx = 0.0;

259:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

260:                {

261:                   tempx += A_data[jj] * x_data[A_j[jj]];

262:                }

263:                y_data[i] = tempx;

264:             }

265:          } // y = A*x

266:          else if (-1 == alpha)

267:          {

268:             for (i = iBegin; i < iEnd; i++)

269:             {

270:                tempx = 0.0;

271:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

272:                {

273:                   tempx -= A_data[jj] * x_data[A_j[jj]];

274:                }

275:                y_data[i] = tempx;

276:             }

277:          } // y = -A*x

278:          else

279:          {

280:             for (i = iBegin; i < iEnd; i++)

281:             {

282:                tempx = 0.0;

283:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

284:                {

285:                   tempx += A_data[jj] * x_data[A_j[jj]];

286:                }

287:                y_data[i] = alpha*tempx;

288:             }

289:          } // y = alpha*A*x

290:       } // temp == 0

291:       else if (-1 == temp) // beta == -alpha

292:       {

293:          if (1 == alpha) // JSP: a common path

294:          {

295:             for (i = iBegin; i < iEnd; i++)

296:             {

297:                tempx = -b_data[i];

298:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

299:                {

300:                   tempx += A_data[jj] * x_data[A_j[jj]];

301:                }

302:                y_data[i] = tempx;

303:             }

304:          } // y = A*x - y

305:          else if (-1 == alpha) // JSP: a common path

306:          {

307:             for (i = iBegin; i < iEnd; i++)

308:             {

309:                tempx = b_data[i];

310:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

311:                {

312:                   tempx -= A_data[jj] * x_data[A_j[jj]];

313:                }

314:                y_data[i] = tempx;

315:             }

316:          } // y = -A*x + y

317:          else

318:          {

319:             for (i = iBegin; i < iEnd; i++)

320:             {

321:                tempx = -b_data[i];

322:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

323:                {

324:                   tempx += A_data[jj] * x_data[A_j[jj]];

325:                }

326:                y_data[i] = alpha*tempx;

327:             }

328:          } // y = alpha*(A*x - y)

329:       } // temp == -1

330:       else if (1 == temp)

331:       {

332:          if (1 == alpha) // JSP: a common path

333:          {

334:             for (i = iBegin; i < iEnd; i++)

335:             {

336:                tempx = b_data[i];

337:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

338:                {

339:                   tempx += A_data[jj] * x_data[A_j[jj]];

340:                }

341:                y_data[i] = tempx;

342:             }

343:          } // y = A*x + y

344:          else if (-1 == alpha)

345:          {

346:             for (i = iBegin; i < iEnd; i++)

347:             {

348:                tempx = -b_data[i];

349:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

350:                {

351:                   tempx -= A_data[jj] * x_data[A_j[jj]];

352:                }

353:                y_data[i] = tempx;

354:             }

355:          } // y = -A*x - y

356:          else

357:          {

358:             for (i = iBegin; i < iEnd; i++)

359:             {

360:                tempx = b_data[i];

361:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

362:                {

363:                   tempx += A_data[jj] * x_data[A_j[jj]];

364:                }

365:                y_data[i] = alpha*tempx;

[...]

371:          if (1 == alpha) // JSP: a common path

372:          {

373:             for (i = iBegin; i < iEnd; i++)

374:             {

375:                tempx = b_data[i]*temp;

376:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

377:                {

378:                   tempx += A_data[jj] * x_data[A_j[jj]];

379:                }

380:                y_data[i] = tempx;

381:             }

382:          } // y = A*x + temp*y

383:          else if (-1 == alpha)

384:          {

385:             for (i = iBegin; i < iEnd; i++)

386:             {

387:                tempx = -b_data[i]*temp;

388:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

389:                {

390:                   tempx -= A_data[jj] * x_data[A_j[jj]];

391:                }

392:                y_data[i] = tempx;

393:             }

394:          } // y = -A*x - temp*y

395:          else

396:          {

397:             for (i = iBegin; i < iEnd; i++)

398:             {

399:                tempx = b_data[i]*temp;

400:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

401:                {

402:                   tempx += A_data[jj] * x_data[A_j[jj]];

403:                }

404:                y_data[i] = alpha*tempx;

0x49a9a0 STP	X29, X30, [SP, #928]!

0x49a9a4 STR	X27, [SP, #16]

0x49a9a8 STP	X26, X25, [SP, #32]

0x49a9ac STP	X24, X23, [SP, #48]

0x49a9b0 STP	X22, X21, [SP, #64]

0x49a9b4 STP	X20, X19, [SP, #80]

0x49a9b8 ADD	X29, SP, #0

0x49a9bc LDR	X0, [X2]

0x49a9c0 ORR	X23, XZR, X7

0x49a9c4 ORR	X24, XZR, X6

0x49a9c8 ORR	X21, XZR, X5

0x49a9cc ORR	X22, XZR, X4

0x49a9d0 ORR	X25, XZR, X3

0x49a9d4 ORR	X19, XZR, X2

0x49a9d8 BL	4997d0

0x49a9dc ORR	X20, XZR, X0

0x49a9e0 LDR	X0, [X19]

0x49a9e4 BL	499860

0x49a9e8 ORR	X19, XZR, X0

0x49a9ec CMP	X20, X0

0x49a9f0 B.LE	49aa2c

0x49a9f4 ADRP	X8,

0x49a9f8 ADRP	X1,

0x49a9fc ADD	X1, X1, #675

0x49aa00 ADRP	X2,

0x49aa04 ADD	X2, X2, #3881

0x49aa08 LDR	X8, [X8, #3824]

0x49aa0c LDR	X0, [X8]

0x49aa10 BL	4a2830

0x49aa14 ORR	X3, XZR, XZR

0x49aa18 ADRP	X0,

0x49aa1c ADD	X0, X0, #1582

0x49aa20 MOVZ	W1, #248

0x49aa24 MOVZ	W2, #1

0x49aa28 BL	4a5070

0x49aa2c TBNZ	X20, #63, 49aa3c

0x49aa30 LDR	X8, [X25]

0x49aa34 CMP	X20, X8

0x49aa38 B.LE	49aa78

0x49aa3c ADRP	X8,

0x49aa40 ADRP	X1,

0x49aa44 ADD	X1, X1, #675

0x49aa48 ADRP	X2,

0x49aa4c ADD	X2, X2, #3187

0x49aa50 LDR	X8, [X8, #3824]

0x49aa54 LDR	X0, [X8]

0x49aa58 BL	4a2830

0x49aa5c ORR	X3, XZR, XZR

0x49aa60 ADRP	X0,

0x49aa64 ADD	X0, X0, #1582

0x49aa68 MOVZ	W1, #249

0x49aa6c MOVZ	W2, #1

0x49aa70 BL	4a5070

0x49aa74 LDR	X8, [X25]

0x49aa78 LDP	X26, X25, [X29, #104]

0x49aa7c LDR	X27, [X29, #96]

0x49aa80 TBNZ	X19, #63, 49abbc

0x49aa84 CMP	X19, X8

0x49aa88 B.GT	49abbc

0x49aa8c LDR	D1, [X22]

0x49aa90 FCMP	D1, #0

0x49aa94 B.NE	49ac00

0x49aa98 LDR	D0, [X21]

0x49aa9c FMOV	D1, #1.0000000

0x49aaa0 FCMP	D0, D1

0x49aaa4 B.NE	49ad3c

0x49aaa8 CMP	X20, X19

0x49aaac B.GE	49b83c

0x49aab0 LDR	X8, [X24]

0x49aab4 LDR	X9, [X23]

0x49aab8 LDR	X11, [X26]

0x49aabc ADD	X13, X9, #16

0x49aac0 LDR	X10, [X27]

0x49aac4 LDR	X12, [X25]

0x49aac8 LDR	X14, [X8, X20,LSL #3]

0x49aacc ADD	X15, X11, #16

0x49aad0 B	49aaf0

0x49aad4 HINT	#0

0x49aad8 HINT	#0

0x49aadc HINT	#0

(977) 0x49aae0 STR	D0, [X12, X20,LSL #3]

(977) 0x49aae4 ORR	X20, XZR, X16

(977) 0x49aae8 CMP	X16, X19

(977) 0x49aaec B.EQ	49b83c

(977) 0x49aaf0 ADD	X16, X20, #1

(977) 0x49aaf4 ORR	X17, XZR, X14

(977) 0x49aaf8 MOVI	D0, #0

(977) 0x49aafc LDR	X14, [X8, X16,LSL #3]

(977) 0x49ab00 CMP	X14, X17

(977) 0x49ab04 B.LE	49aae0

(977) 0x49ab08 SUB	W18, W14, W17

(977) 0x49ab0c MOVI	D0, #0

(977) 0x49ab10 ANDS	X0, X18, #4160

(977) 0x49ab14 B.EQ	49ab50

(977) 0x49ab18 ORR	X18, XZR, X17

(977) 0x49ab1c HINT	#0

  (979) 0x49ab20 LDR	X1, [X11, X18,LSL #3]

  (979) 0x49ab24 LDR	D1, [X9, X18,LSL #3]

  (979) 0x49ab28 ADD	X18, X18, #1

  (979) 0x49ab2c SUBS	X0, X0, #1

  (979) 0x49ab30 LDR	D2, [X10, X1,LSL #3]

  (979) 0x49ab34 FMADD	D0, D1, D2, D0

  (979) 0x49ab38 B.NE	49ab20

(977) 0x49ab3c ORN	X17, XZR, X17

(977) 0x49ab40 ADD	X17, X14, X17

(977) 0x49ab44 CMP	X17, #3

(977) 0x49ab48 B.CC	49aae0

(977) 0x49ab4c B	49ab64

(977) 0x49ab50 ORR	X18, XZR, X17

(977) 0x49ab54 ORN	X17, XZR, X17

(977) 0x49ab58 ADD	X17, X14, X17

(977) 0x49ab5c CMP	X17, #3

(977) 0x49ab60 B.CC	49aae0

(977) 0x49ab64 UBFM	X0, X18, #61, #60

(977) 0x49ab68 SUB	X17, X14, X18

(977) 0x49ab6c ADD	X18, X13, X0

(977) 0x49ab70 ADD	X0, X15, X0

(977) 0x49ab74 HINT	#0

(977) 0x49ab78 HINT	#0

(977) 0x49ab7c HINT	#0

  (978) 0x49ab80 LDP	X1, X2, [X0, #1008]

  (978) 0x49ab84 LDP	D2, D3, [X18, #1008]

  (978) 0x49ab88 SUBS	X17, X17, #4

  (978) 0x49ab8c LDR	D1, [X10, X1,LSL #3]

  (978) 0x49ab90 FMADD	D0, D2, D1, D0

  (978) 0x49ab94 LDR	D1, [X10, X2,LSL #3]

  (978) 0x49ab98 FMADD	D0, D3, D1, D0

  (978) 0x49ab9c LDP	X1, X2, [X0], #32

  (978) 0x49aba0 LDR	D2, [X10, X1,LSL #3]

  (978) 0x49aba4 LDP	D1, D3, [X18], #32

  (978) 0x49aba8 FMADD	D0, D1, D2, D0

  (978) 0x49abac LDR	D1, [X10, X2,LSL #3]

  (978) 0x49abb0 FMADD	D0, D3, D1, D0

  (978) 0x49abb4 B.NE	49ab80

(977) 0x49abb8 B	49aae0

0x49abbc ADRP	X8,

0x49abc0 ADRP	X1,

0x49abc4 ADD	X1, X1, #675

0x49abc8 ADRP	X2,

0x49abcc ADD	X2, X2, #3221

0x49abd0 LDR	X8, [X8, #3824]

0x49abd4 LDR	X0, [X8]

0x49abd8 BL	4a2830

0x49abdc ORR	X3, XZR, XZR

0x49abe0 ADRP	X0,

0x49abe4 ADD	X0, X0, #1582

0x49abe8 MOVZ	W1, #250

0x49abec MOVZ	W2, #1

0x49abf0 BL	4a5070

0x49abf4 LDR	D1, [X22]

0x49abf8 FCMP	D1, #0

0x49abfc B.EQ	49aa98

0x49ac00 LDR	X8, [X29, #120]

0x49ac04 FMOV	D0, #-1.0000000

0x49ac08 FCMP	D1, D0

0x49ac0c B.NE	49ae5c

0x49ac10 LDR	D0, [X21]

0x49ac14 FMOV	D1, #1.0000000

0x49ac18 FCMP	D0, D1

0x49ac1c B.NE	49af7c

0x49ac20 CMP	X20, X19

0x49ac24 B.GE	49b83c

0x49ac28 LDR	X9, [X24]

0x49ac2c LDR	X10, [X23]

0x49ac30 LDR	X12, [X26]

0x49ac34 ADD	X14, X10, #16

0x49ac38 LDR	X8, [X8]

0x49ac3c LDR	X11, [X27]

0x49ac40 LDR	X13, [X25]

0x49ac44 LDR	X16, [X9, X20,LSL #3]

0x49ac48 ADD	X15, X12, #16

0x49ac4c B	49ac70

0x49ac50 HINT	#0

0x49ac54 HINT	#0

0x49ac58 HINT	#0

0x49ac5c HINT	#0

(974) 0x49ac60 STR	D0, [X13, X20,LSL #3]

(974) 0x49ac64 ORR	X20, XZR, X17

(974) 0x49ac68 CMP	X17, X19

(974) 0x49ac6c B.EQ	49b83c

(974) 0x49ac70 LDR	D0, [X8, X20,LSL #3]

(974) 0x49ac74 ADD	X17, X20, #1

(974) 0x49ac78 ORR	X18, XZR, X16

(974) 0x49ac7c LDR	X16, [X9, X17,LSL #3]

(974) 0x49ac80 CMP	X16, X18

(974) 0x49ac84 FNEG	D0, D0

(974) 0x49ac88 B.LE	49ac60

(974) 0x49ac8c SUB	W0, W16, W18

(974) 0x49ac90 ANDS	X1, X0, #4160

(974) 0x49ac94 B.EQ	49acd0

(974) 0x49ac98 ORR	X0, XZR, X18

(974) 0x49ac9c HINT	#0

  (976) 0x49aca0 LDR	X2, [X12, X0,LSL #3]

  (976) 0x49aca4 LDR	D1, [X10, X0,LSL #3]

  (976) 0x49aca8 ADD	X0, X0, #1

  (976) 0x49acac SUBS	X1, X1, #1

  (976) 0x49acb0 LDR	D2, [X11, X2,LSL #3]

  (976) 0x49acb4 FMADD	D0, D1, D2, D0

  (976) 0x49acb8 B.NE	49aca0

(974) 0x49acbc ORN	X18, XZR, X18

(974) 0x49acc0 ADD	X18, X16, X18

(974) 0x49acc4 CMP	X18, #3

(974) 0x49acc8 B.CC	49ac60

(974) 0x49accc B	49ace4

(974) 0x49acd0 ORR	X0, XZR, X18

(974) 0x49acd4 ORN	X18, XZR, X18

(974) 0x49acd8 ADD	X18, X16, X18

(974) 0x49acdc CMP	X18, #3

(974) 0x49ace0 B.CC	49ac60

(974) 0x49ace4 UBFM	X1, X0, #61, #60

(974) 0x49ace8 SUB	X18, X16, X0

(974) 0x49acec ADD	X0, X14, X1

(974) 0x49acf0 ADD	X1, X15, X1

(974) 0x49acf4 HINT	#0

(974) 0x49acf8 HINT	#0

(974) 0x49acfc HINT	#0

  (975) 0x49ad00 LDP	X2, X3, [X1, #1008]

  (975) 0x49ad04 LDP	D2, D3, [X0, #1008]

  (975) 0x49ad08 SUBS	X18, X18, #4

  (975) 0x49ad0c LDR	D1, [X11, X2,LSL #3]

  (975) 0x49ad10 FMADD	D0, D2, D1, D0

  (975) 0x49ad14 LDR	D1, [X11, X3,LSL #3]

  (975) 0x49ad18 FMADD	D0, D3, D1, D0

  (975) 0x49ad1c LDP	X2, X3, [X1], #32

  (975) 0x49ad20 LDR	D2, [X11, X2,LSL #3]

  (975) 0x49ad24 LDP	D1, D3, [X0], #32

  (975) 0x49ad28 FMADD	D0, D1, D2, D0

  (975) 0x49ad2c LDR	D1, [X11, X3,LSL #3]

  (975) 0x49ad30 FMADD	D0, D3, D1, D0

  (975) 0x49ad34 B.NE	49ad00

(974) 0x49ad38 B	49ac60

0x49ad3c FMOV	D1, #-1.0000000

0x49ad40 FCMP	D0, D1

0x49ad44 B.NE	49b09c

0x49ad48 CMP	X20, X19

0x49ad4c B.GE	49b83c

0x49ad50 LDR	X8, [X24]

0x49ad54 LDR	X9, [X23]

0x49ad58 LDR	X11, [X26]

0x49ad5c ADD	X13, X9, #16

0x49ad60 LDR	X10, [X27]

0x49ad64 LDR	X12, [X25]

0x49ad68 LDR	X14, [X8, X20,LSL #3]

0x49ad6c ADD	X15, X11, #16

0x49ad70 B	49ad90

0x49ad74 HINT	#0

0x49ad78 HINT	#0

0x49ad7c HINT	#0

(971) 0x49ad80 STR	D0, [X12, X20,LSL #3]

(971) 0x49ad84 ORR	X20, XZR, X16

(971) 0x49ad88 CMP	X16, X19

(971) 0x49ad8c B.EQ	49b83c

(971) 0x49ad90 ADD	X16, X20, #1

(971) 0x49ad94 ORR	X17, XZR, X14

(971) 0x49ad98 MOVI	D0, #0

(971) 0x49ad9c LDR	X14, [X8, X16,LSL #3]

(971) 0x49ada0 CMP	X14, X17

(971) 0x49ada4 B.LE	49ad80

(971) 0x49ada8 SUB	W18, W14, W17

(971) 0x49adac MOVI	D0, #0

(971) 0x49adb0 ANDS	X0, X18, #4160

(971) 0x49adb4 B.EQ	49adf0

(971) 0x49adb8 ORR	X18, XZR, X17

(971) 0x49adbc HINT	#0

  (973) 0x49adc0 LDR	X1, [X11, X18,LSL #3]

  (973) 0x49adc4 LDR	D1, [X9, X18,LSL #3]

  (973) 0x49adc8 ADD	X18, X18, #1

  (973) 0x49adcc SUBS	X0, X0, #1

  (973) 0x49add0 LDR	D2, [X10, X1,LSL #3]

  (973) 0x49add4 FMSUB	D0, D1, D2, D0

  (973) 0x49add8 B.NE	49adc0

(971) 0x49addc ORN	X17, XZR, X17

(971) 0x49ade0 ADD	X17, X14, X17

(971) 0x49ade4 CMP	X17, #3

(971) 0x49ade8 B.CC	49ad80

(971) 0x49adec B	49ae04

(971) 0x49adf0 ORR	X18, XZR, X17

(971) 0x49adf4 ORN	X17, XZR, X17

(971) 0x49adf8 ADD	X17, X14, X17

(971) 0x49adfc CMP	X17, #3

(971) 0x49ae00 B.CC	49ad80

(971) 0x49ae04 UBFM	X0, X18, #61, #60

(971) 0x49ae08 SUB	X17, X14, X18

(971) 0x49ae0c ADD	X18, X13, X0

(971) 0x49ae10 ADD	X0, X15, X0

(971) 0x49ae14 HINT	#0

(971) 0x49ae18 HINT	#0

(971) 0x49ae1c HINT	#0

  (972) 0x49ae20 LDP	X1, X2, [X0, #1008]

  (972) 0x49ae24 LDP	D2, D3, [X18, #1008]

  (972) 0x49ae28 SUBS	X17, X17, #4

  (972) 0x49ae2c LDR	D1, [X10, X1,LSL #3]

  (972) 0x49ae30 FMSUB	D0, D2, D1, D0

  (972) 0x49ae34 LDR	D1, [X10, X2,LSL #3]

  (972) 0x49ae38 FMSUB	D0, D3, D1, D0

  (972) 0x49ae3c LDP	X1, X2, [X0], #32

  (972) 0x49ae40 LDR	D2, [X10, X1,LSL #3]

  (972) 0x49ae44 LDP	D1, D3, [X18], #32

  (972) 0x49ae48 FMSUB	D0, D1, D2, D0

  (972) 0x49ae4c LDR	D1, [X10, X2,LSL #3]

  (972) 0x49ae50 FMSUB	D0, D3, D1, D0

  (972) 0x49ae54 B.NE	49ae20

(971) 0x49ae58 B	49ad80

0x49ae5c LDR	D0, [X21]

0x49ae60 FMOV	D2, #1.0000000

0x49ae64 FCMP	D1, D2

0x49ae68 B.NE	49b19c

0x49ae6c FCMP	D0, D2

0x49ae70 B.NE	49b2bc

0x49ae74 CMP	X20, X19

0x49ae78 B.GE	49b83c

0x49ae7c LDR	X9, [X24]

0x49ae80 LDR	X10, [X23]

0x49ae84 LDR	X12, [X26]

0x49ae88 ADD	X14, X10, #16

0x49ae8c LDR	X8, [X8]

0x49ae90 LDR	X11, [X27]

0x49ae94 LDR	X13, [X25]

0x49ae98 LDR	X16, [X9, X20,LSL #3]

0x49ae9c ADD	X15, X12, #16

0x49aea0 B	49aeb4

(992) 0x49aea4 STR	D0, [X13, X20,LSL #3]

(992) 0x49aea8 ORR	X20, XZR, X17

(992) 0x49aeac CMP	X17, X19

(992) 0x49aeb0 B.EQ	49b83c

(992) 0x49aeb4 LDR	D0, [X8, X20,LSL #3]

(992) 0x49aeb8 ADD	X17, X20, #1

(992) 0x49aebc ORR	X18, XZR, X16

(992) 0x49aec0 LDR	X16, [X9, X17,LSL #3]

(992) 0x49aec4 CMP	X16, X18

(992) 0x49aec8 B.LE	49aea4

(992) 0x49aecc SUB	W0, W16, W18

(992) 0x49aed0 ANDS	X1, X0, #4160

(992) 0x49aed4 B.EQ	49af10

(992) 0x49aed8 ORR	X0, XZR, X18

(992) 0x49aedc HINT	#0

  (994) 0x49aee0 LDR	X2, [X12, X0,LSL #3]

  (994) 0x49aee4 LDR	D1, [X10, X0,LSL #3]

  (994) 0x49aee8 ADD	X0, X0, #1

  (994) 0x49aeec SUBS	X1, X1, #1

  (994) 0x49aef0 LDR	D2, [X11, X2,LSL #3]

  (994) 0x49aef4 FMADD	D0, D1, D2, D0

  (994) 0x49aef8 B.NE	49aee0

(992) 0x49aefc ORN	X18, XZR, X18

(992) 0x49af00 ADD	X18, X16, X18

(992) 0x49af04 CMP	X18, #3

(992) 0x49af08 B.CC	49aea4

(992) 0x49af0c B	49af24

(992) 0x49af10 ORR	X0, XZR, X18

(992) 0x49af14 ORN	X18, XZR, X18

(992) 0x49af18 ADD	X18, X16, X18

(992) 0x49af1c CMP	X18, #3

(992) 0x49af20 B.CC	49aea4

(992) 0x49af24 UBFM	X1, X0, #61, #60

(992) 0x49af28 SUB	X18, X16, X0

(992) 0x49af2c ADD	X0, X14, X1

(992) 0x49af30 ADD	X1, X15, X1

(992) 0x49af34 HINT	#0

(992) 0x49af38 HINT	#0

(992) 0x49af3c HINT	#0

  (993) 0x49af40 LDP	X2, X3, [X1, #1008]

  (993) 0x49af44 LDP	D2, D3, [X0, #1008]

  (993) 0x49af48 SUBS	X18, X18, #4

  (993) 0x49af4c LDR	D1, [X11, X2,LSL #3]

  (993) 0x49af50 FMADD	D0, D2, D1, D0

  (993) 0x49af54 LDR	D1, [X11, X3,LSL #3]

  (993) 0x49af58 FMADD	D0, D3, D1, D0

  (993) 0x49af5c LDP	X2, X3, [X1], #32

  (993) 0x49af60 LDR	D2, [X11, X2,LSL #3]

  (993) 0x49af64 LDP	D1, D3, [X0], #32

  (993) 0x49af68 FMADD	D0, D1, D2, D0

  (993) 0x49af6c LDR	D1, [X11, X3,LSL #3]

  (993) 0x49af70 FMADD	D0, D3, D1, D0

  (993) 0x49af74 B.NE	49af40

(992) 0x49af78 B	49aea4

0x49af7c FMOV	D1, #-1.0000000

0x49af80 FCMP	D0, D1

0x49af84 B.NE	49b3dc

0x49af88 CMP	X20, X19

0x49af8c B.GE	49b83c

0x49af90 LDR	X9, [X24]

0x49af94 LDR	X10, [X23]

0x49af98 LDR	X12, [X26]

0x49af9c ADD	X14, X10, #16

0x49afa0 LDR	X8, [X8]

0x49afa4 LDR	X11, [X27]

0x49afa8 LDR	X13, [X25]

0x49afac LDR	X16, [X9, X20,LSL #3]

0x49afb0 ADD	X15, X12, #16

0x49afb4 B	49afd0

0x49afb8 HINT	#0

0x49afbc HINT	#0

(968) 0x49afc0 STR	D0, [X13, X20,LSL #3]

(968) 0x49afc4 ORR	X20, XZR, X17

(968) 0x49afc8 CMP	X17, X19

(968) 0x49afcc B.EQ	49b83c

(968) 0x49afd0 LDR	D0, [X8, X20,LSL #3]

(968) 0x49afd4 ADD	X17, X20, #1

(968) 0x49afd8 ORR	X18, XZR, X16

(968) 0x49afdc LDR	X16, [X9, X17,LSL #3]

(968) 0x49afe0 CMP	X16, X18

(968) 0x49afe4 B.LE	49afc0

(968) 0x49afe8 SUB	W0, W16, W18

(968) 0x49afec ANDS	X1, X0, #4160

(968) 0x49aff0 B.EQ	49b030

(968) 0x49aff4 ORR	X0, XZR, X18

(968) 0x49aff8 HINT	#0

(968) 0x49affc HINT	#0

  (970) 0x49b000 LDR	X2, [X12, X0,LSL #3]

  (970) 0x49b004 LDR	D1, [X10, X0,LSL #3]

  (970) 0x49b008 ADD	X0, X0, #1

  (970) 0x49b00c SUBS	X1, X1, #1

  (970) 0x49b010 LDR	D2, [X11, X2,LSL #3]

  (970) 0x49b014 FMSUB	D0, D1, D2, D0

  (970) 0x49b018 B.NE	49b000

(968) 0x49b01c ORN	X18, XZR, X18

(968) 0x49b020 ADD	X18, X16, X18

(968) 0x49b024 CMP	X18, #3

(968) 0x49b028 B.CC	49afc0

(968) 0x49b02c B	49b044

(968) 0x49b030 ORR	X0, XZR, X18

(968) 0x49b034 ORN	X18, XZR, X18

(968) 0x49b038 ADD	X18, X16, X18

(968) 0x49b03c CMP	X18, #3

(968) 0x49b040 B.CC	49afc0

(968) 0x49b044 UBFM	X1, X0, #61, #60

(968) 0x49b048 SUB	X18, X16, X0

(968) 0x49b04c ADD	X0, X14, X1

(968) 0x49b050 ADD	X1, X15, X1

(968) 0x49b054 HINT	#0

(968) 0x49b058 HINT	#0

(968) 0x49b05c HINT	#0

  (969) 0x49b060 LDP	X2, X3, [X1, #1008]

  (969) 0x49b064 LDP	D2, D3, [X0, #1008]

  (969) 0x49b068 SUBS	X18, X18, #4

  (969) 0x49b06c LDR	D1, [X11, X2,LSL #3]

  (969) 0x49b070 FMSUB	D0, D2, D1, D0

  (969) 0x49b074 LDR	D1, [X11, X3,LSL #3]

  (969) 0x49b078 FMSUB	D0, D3, D1, D0

  (969) 0x49b07c LDP	X2, X3, [X1], #32

  (969) 0x49b080 LDR	D2, [X11, X2,LSL #3]

  (969) 0x49b084 LDP	D1, D3, [X0], #32

  (969) 0x49b088 FMSUB	D0, D1, D2, D0

  (969) 0x49b08c LDR	D1, [X11, X3,LSL #3]

  (969) 0x49b090 FMSUB	D0, D3, D1, D0

  (969) 0x49b094 B.NE	49b060

(968) 0x49b098 B	49afc0

0x49b09c CMP	X20, X19

0x49b0a0 B.GE	49b83c

0x49b0a4 LDR	X8, [X24]

0x49b0a8 LDR	X9, [X23]

0x49b0ac LDR	X11, [X26]

0x49b0b0 ADD	X13, X9, #16

0x49b0b4 LDR	X10, [X27]

0x49b0b8 LDR	X12, [X25]

0x49b0bc LDR	X14, [X8, X20,LSL #3]

0x49b0c0 ADD	X15, X11, #16

0x49b0c4 B	49b0e0

(980) 0x49b0c8 LDR	D1, [X21]

(980) 0x49b0cc CMP	X16, X19

(980) 0x49b0d0 FMUL	D0, D0, D1

(980) 0x49b0d4 STR	D0, [X12, X20,LSL #3]

(980) 0x49b0d8 ORR	X20, XZR, X16

(980) 0x49b0dc B.EQ	49b83c

(980) 0x49b0e0 ADD	X16, X20, #1

(980) 0x49b0e4 ORR	X17, XZR, X14

(980) 0x49b0e8 MOVI	D0, #0

(980) 0x49b0ec LDR	X14, [X8, X16,LSL #3]

(980) 0x49b0f0 CMP	X14, X17

(980) 0x49b0f4 B.LE	49b0c8

(980) 0x49b0f8 SUB	W18, W14, W17

(980) 0x49b0fc MOVI	D0, #0

(980) 0x49b100 ANDS	X0, X18, #4160

(980) 0x49b104 B.EQ	49b13c

(980) 0x49b108 ORR	X18, XZR, X17

  (982) 0x49b10c LDR	X1, [X11, X18,LSL #3]

  (982) 0x49b110 LDR	D1, [X9, X18,LSL #3]

  (982) 0x49b114 ADD	X18, X18, #1

  (982) 0x49b118 SUBS	X0, X0, #1

  (982) 0x49b11c LDR	D2, [X10, X1,LSL #3]

  (982) 0x49b120 FMADD	D0, D1, D2, D0

  (982) 0x49b124 B.NE	49b10c

(980) 0x49b128 ORN	X17, XZR, X17

(980) 0x49b12c ADD	X17, X14, X17

(980) 0x49b130 CMP	X17, #3

(980) 0x49b134 B.CC	49b0c8

(980) 0x49b138 B	49b150

(980) 0x49b13c ORR	X18, XZR, X17

(980) 0x49b140 ORN	X17, XZR, X17

(980) 0x49b144 ADD	X17, X14, X17

(980) 0x49b148 CMP	X17, #3

(980) 0x49b14c B.CC	49b0c8

(980) 0x49b150 UBFM	X0, X18, #61, #60

(980) 0x49b154 SUB	X17, X14, X18

(980) 0x49b158 ADD	X18, X13, X0

(980) 0x49b15c ADD	X0, X15, X0

  (981) 0x49b160 LDP	X1, X2, [X0, #1008]

  (981) 0x49b164 LDP	D2, D3, [X18, #1008]

  (981) 0x49b168 SUBS	X17, X17, #4

  (981) 0x49b16c LDR	D1, [X10, X1,LSL #3]

  (981) 0x49b170 FMADD	D0, D2, D1, D0

  (981) 0x49b174 LDR	D1, [X10, X2,LSL #3]

  (981) 0x49b178 FMADD	D0, D3, D1, D0

  (981) 0x49b17c LDP	X1, X2, [X0], #32

  (981) 0x49b180 LDR	D2, [X10, X1,LSL #3]

  (981) 0x49b184 LDP	D1, D3, [X18], #32

  (981) 0x49b188 FMADD	D0, D1, D2, D0

  (981) 0x49b18c LDR	D1, [X10, X2,LSL #3]

  (981) 0x49b190 FMADD	D0, D3, D1, D0

  (981) 0x49b194 B.NE	49b160

(980) 0x49b198 B	49b0c8

0x49b19c FCMP	D0, D2

0x49b1a0 B.NE	49b4fc

0x49b1a4 CMP	X20, X19

0x49b1a8 B.GE	49b83c

0x49b1ac LDR	X9, [X24]

0x49b1b0 LDR	X10, [X23]

0x49b1b4 LDR	X12, [X26]

0x49b1b8 ADD	X14, X10, #16

0x49b1bc LDR	X8, [X8]

0x49b1c0 LDR	X11, [X27]

0x49b1c4 LDR	X13, [X25]

0x49b1c8 LDR	X16, [X9, X20,LSL #3]

0x49b1cc ADD	X15, X12, #16

0x49b1d0 B	49b1f0

0x49b1d4 HINT	#0

0x49b1d8 HINT	#0

0x49b1dc HINT	#0

(965) 0x49b1e0 STR	D0, [X13, X20,LSL #3]

(965) 0x49b1e4 ORR	X20, XZR, X17

(965) 0x49b1e8 CMP	X17, X19

(965) 0x49b1ec B.EQ	49b83c

(965) 0x49b1f0 LDR	D0, [X8, X20,LSL #3]

(965) 0x49b1f4 LDR	D1, [X22]

(965) 0x49b1f8 ADD	X17, X20, #1

(965) 0x49b1fc ORR	X18, XZR, X16

(965) 0x49b200 LDR	X16, [X9, X17,LSL #3]

(965) 0x49b204 CMP	X16, X18

(965) 0x49b208 FMUL	D0, D0, D1

(965) 0x49b20c B.LE	49b1e0

(965) 0x49b210 SUB	W0, W16, W18

(965) 0x49b214 ANDS	X1, X0, #4160

(965) 0x49b218 B.EQ	49b250

(965) 0x49b21c ORR	X0, XZR, X18

  (967) 0x49b220 LDR	X2, [X12, X0,LSL #3]

  (967) 0x49b224 LDR	D1, [X10, X0,LSL #3]

  (967) 0x49b228 ADD	X0, X0, #1

  (967) 0x49b22c SUBS	X1, X1, #1

  (967) 0x49b230 LDR	D2, [X11, X2,LSL #3]

  (967) 0x49b234 FMADD	D0, D1, D2, D0

  (967) 0x49b238 B.NE	49b220

(965) 0x49b23c ORN	X18, XZR, X18

(965) 0x49b240 ADD	X18, X16, X18

(965) 0x49b244 CMP	X18, #3

(965) 0x49b248 B.CC	49b1e0

(965) 0x49b24c B	49b264

(965) 0x49b250 ORR	X0, XZR, X18

(965) 0x49b254 ORN	X18, XZR, X18

(965) 0x49b258 ADD	X18, X16, X18

(965) 0x49b25c CMP	X18, #3

(965) 0x49b260 B.CC	49b1e0

(965) 0x49b264 UBFM	X1, X0, #61, #60

(965) 0x49b268 SUB	X18, X16, X0

(965) 0x49b26c ADD	X0, X14, X1

(965) 0x49b270 ADD	X1, X15, X1

(965) 0x49b274 HINT	#0

(965) 0x49b278 HINT	#0

(965) 0x49b27c HINT	#0

  (966) 0x49b280 LDP	X2, X3, [X1, #1008]

  (966) 0x49b284 LDP	D2, D3, [X0, #1008]

  (966) 0x49b288 SUBS	X18, X18, #4

  (966) 0x49b28c LDR	D1, [X11, X2,LSL #3]

  (966) 0x49b290 FMADD	D0, D2, D1, D0

  (966) 0x49b294 LDR	D1, [X11, X3,LSL #3]

  (966) 0x49b298 FMADD	D0, D3, D1, D0

  (966) 0x49b29c LDP	X2, X3, [X1], #32

  (966) 0x49b2a0 LDR	D2, [X11, X2,LSL #3]

  (966) 0x49b2a4 LDP	D1, D3, [X0], #32

  (966) 0x49b2a8 FMADD	D0, D1, D2, D0

  (966) 0x49b2ac LDR	D1, [X11, X3,LSL #3]

  (966) 0x49b2b0 FMADD	D0, D3, D1, D0

  (966) 0x49b2b4 B.NE	49b280

(965) 0x49b2b8 B	49b1e0

0x49b2bc FMOV	D1, #-1.0000000

0x49b2c0 FCMP	D0, D1

0x49b2c4 B.NE	49b61c

0x49b2c8 CMP	X20, X19

0x49b2cc B.GE	49b83c

0x49b2d0 LDR	X9, [X24]

0x49b2d4 LDR	X10, [X23]

0x49b2d8 LDR	X12, [X26]

0x49b2dc ADD	X14, X10, #16

0x49b2e0 LDR	X8, [X8]

0x49b2e4 LDR	X11, [X27]

0x49b2e8 LDR	X13, [X25]

0x49b2ec LDR	X16, [X9, X20,LSL #3]

0x49b2f0 ADD	X15, X12, #16

0x49b2f4 B	49b310

0x49b2f8 HINT	#0

0x49b2fc HINT	#0

(962) 0x49b300 STR	D0, [X13, X20,LSL #3]

(962) 0x49b304 ORR	X20, XZR, X17

(962) 0x49b308 CMP	X17, X19

(962) 0x49b30c B.EQ	49b83c

(962) 0x49b310 LDR	D0, [X8, X20,LSL #3]

(962) 0x49b314 ADD	X17, X20, #1

(962) 0x49b318 ORR	X18, XZR, X16

(962) 0x49b31c LDR	X16, [X9, X17,LSL #3]

(962) 0x49b320 CMP	X16, X18

(962) 0x49b324 FNEG	D0, D0

(962) 0x49b328 B.LE	49b300

(962) 0x49b32c SUB	W0, W16, W18

(962) 0x49b330 ANDS	X1, X0, #4160

(962) 0x49b334 B.EQ	49b370

(962) 0x49b338 ORR	X0, XZR, X18

(962) 0x49b33c HINT	#0

  (964) 0x49b340 LDR	X2, [X12, X0,LSL #3]

  (964) 0x49b344 LDR	D1, [X10, X0,LSL #3]

  (964) 0x49b348 ADD	X0, X0, #1

  (964) 0x49b34c SUBS	X1, X1, #1

  (964) 0x49b350 LDR	D2, [X11, X2,LSL #3]

  (964) 0x49b354 FMSUB	D0, D1, D2, D0

  (964) 0x49b358 B.NE	49b340

(962) 0x49b35c ORN	X18, XZR, X18

(962) 0x49b360 ADD	X18, X16, X18

(962) 0x49b364 CMP	X18, #3

(962) 0x49b368 B.CC	49b300

(962) 0x49b36c B	49b384

(962) 0x49b370 ORR	X0, XZR, X18

(962) 0x49b374 ORN	X18, XZR, X18

(962) 0x49b378 ADD	X18, X16, X18

(962) 0x49b37c CMP	X18, #3

(962) 0x49b380 B.CC	49b300

(962) 0x49b384 UBFM	X1, X0, #61, #60

(962) 0x49b388 SUB	X18, X16, X0

(962) 0x49b38c ADD	X0, X14, X1

(962) 0x49b390 ADD	X1, X15, X1

(962) 0x49b394 HINT	#0

(962) 0x49b398 HINT	#0

(962) 0x49b39c HINT	#0

  (963) 0x49b3a0 LDP	X2, X3, [X1, #1008]

  (963) 0x49b3a4 LDP	D2, D3, [X0, #1008]

  (963) 0x49b3a8 SUBS	X18, X18, #4

  (963) 0x49b3ac LDR	D1, [X11, X2,LSL #3]

  (963) 0x49b3b0 FMSUB	D0, D2, D1, D0

  (963) 0x49b3b4 LDR	D1, [X11, X3,LSL #3]

  (963) 0x49b3b8 FMSUB	D0, D3, D1, D0

  (963) 0x49b3bc LDP	X2, X3, [X1], #32

  (963) 0x49b3c0 LDR	D2, [X11, X2,LSL #3]

  (963) 0x49b3c4 LDP	D1, D3, [X0], #32

  (963) 0x49b3c8 FMSUB	D0, D1, D2, D0

  (963) 0x49b3cc LDR	D1, [X11, X3,LSL #3]

  (963) 0x49b3d0 FMSUB	D0, D3, D1, D0

  (963) 0x49b3d4 B.NE	49b3a0

(962) 0x49b3d8 B	49b300

0x49b3dc CMP	X20, X19

0x49b3e0 B.GE	49b83c

0x49b3e4 LDR	X9, [X24]

0x49b3e8 LDR	X10, [X23]

0x49b3ec LDR	X12, [X26]

0x49b3f0 ADD	X14, X10, #16

0x49b3f4 LDR	X8, [X8]

0x49b3f8 LDR	X11, [X27]

0x49b3fc LDR	X13, [X25]

0x49b400 LDR	X16, [X9, X20,LSL #3]

0x49b404 ADD	X15, X12, #16

0x49b408 B	49b424

(995) 0x49b40c LDR	D1, [X21]

(995) 0x49b410 CMP	X17, X19

(995) 0x49b414 FMUL	D0, D0, D1

(995) 0x49b418 STR	D0, [X13, X20,LSL #3]

(995) 0x49b41c ORR	X20, XZR, X17

(995) 0x49b420 B.EQ	49b83c

(995) 0x49b424 LDR	D0, [X8, X20,LSL #3]

(995) 0x49b428 ADD	X17, X20, #1

(995) 0x49b42c ORR	X18, XZR, X16

(995) 0x49b430 LDR	X16, [X9, X17,LSL #3]

(995) 0x49b434 CMP	X16, X18

(995) 0x49b438 FNEG	D0, D0

(995) 0x49b43c B.LE	49b40c

(995) 0x49b440 SUB	W0, W16, W18

(995) 0x49b444 ANDS	X1, X0, #4160

(995) 0x49b448 B.EQ	49b490

(995) 0x49b44c ORR	X0, XZR, X18

(995) 0x49b450 HINT	#0

(995) 0x49b454 HINT	#0

(995) 0x49b458 HINT	#0

(995) 0x49b45c HINT	#0

  (997) 0x49b460 LDR	X2, [X12, X0,LSL #3]

  (997) 0x49b464 LDR	D1, [X10, X0,LSL #3]

  (997) 0x49b468 ADD	X0, X0, #1

  (997) 0x49b46c SUBS	X1, X1, #1

  (997) 0x49b470 LDR	D2, [X11, X2,LSL #3]

  (997) 0x49b474 FMADD	D0, D1, D2, D0

  (997) 0x49b478 B.NE	49b460

(995) 0x49b47c ORN	X18, XZR, X18

(995) 0x49b480 ADD	X18, X16, X18

(995) 0x49b484 CMP	X18, #3

(995) 0x49b488 B.CC	49b40c

(995) 0x49b48c B	49b4a4

(995) 0x49b490 ORR	X0, XZR, X18

(995) 0x49b494 ORN	X18, XZR, X18

(995) 0x49b498 ADD	X18, X16, X18

(995) 0x49b49c CMP	X18, #3

(995) 0x49b4a0 B.CC	49b40c

(995) 0x49b4a4 UBFM	X1, X0, #61, #60

(995) 0x49b4a8 SUB	X18, X16, X0

(995) 0x49b4ac ADD	X0, X14, X1

(995) 0x49b4b0 ADD	X1, X15, X1

(995) 0x49b4b4 HINT	#0

(995) 0x49b4b8 HINT	#0

(995) 0x49b4bc HINT	#0

  (996) 0x49b4c0 LDP	X2, X3, [X1, #1008]

  (996) 0x49b4c4 LDP	D2, D3, [X0, #1008]

  (996) 0x49b4c8 SUBS	X18, X18, #4

  (996) 0x49b4cc LDR	D1, [X11, X2,LSL #3]

  (996) 0x49b4d0 FMADD	D0, D2, D1, D0

  (996) 0x49b4d4 LDR	D1, [X11, X3,LSL #3]

  (996) 0x49b4d8 FMADD	D0, D3, D1, D0

  (996) 0x49b4dc LDP	X2, X3, [X1], #32

  (996) 0x49b4e0 LDR	D2, [X11, X2,LSL #3]

  (996) 0x49b4e4 LDP	D1, D3, [X0], #32

  (996) 0x49b4e8 FMADD	D0, D1, D2, D0

  (996) 0x49b4ec LDR	D1, [X11, X3,LSL #3]

  (996) 0x49b4f0 FMADD	D0, D3, D1, D0

  (996) 0x49b4f4 B.NE	49b4c0

(995) 0x49b4f8 B	49b40c

0x49b4fc FMOV	D1, #-1.0000000

0x49b500 FCMP	D0, D1

0x49b504 B.NE	49b71c

0x49b508 CMP	X20, X19

0x49b50c B.GE	49b83c

0x49b510 LDR	X9, [X24]

0x49b514 LDR	X10, [X23]

0x49b518 LDR	X12, [X26]

0x49b51c ADD	X14, X10, #16

0x49b520 LDR	X8, [X8]

0x49b524 LDR	X11, [X27]

0x49b528 LDR	X13, [X25]

0x49b52c LDR	X16, [X9, X20,LSL #3]

0x49b530 ADD	X15, X12, #16

0x49b534 B	49b548

(986) 0x49b538 STR	D0, [X13, X20,LSL #3]

(986) 0x49b53c ORR	X20, XZR, X17

(986) 0x49b540 CMP	X17, X19

(986) 0x49b544 B.EQ	49b83c

(986) 0x49b548 LDR	D0, [X8, X20,LSL #3]

(986) 0x49b54c LDR	D1, [X22]

(986) 0x49b550 ADD	X17, X20, #1

(986) 0x49b554 ORR	X18, XZR, X16

(986) 0x49b558 LDR	X16, [X9, X17,LSL #3]

(986) 0x49b55c CMP	X16, X18

(986) 0x49b560 FNMUL	D0, D0, D1

(986) 0x49b564 B.LE	49b538

(986) 0x49b568 SUB	W0, W16, W18

(986) 0x49b56c ANDS	X1, X0, #4160

(986) 0x49b570 B.EQ	49b5b0

(986) 0x49b574 ORR	X0, XZR, X18

(986) 0x49b578 HINT	#0

(986) 0x49b57c HINT	#0

  (988) 0x49b580 LDR	X2, [X12, X0,LSL #3]

  (988) 0x49b584 LDR	D1, [X10, X0,LSL #3]

  (988) 0x49b588 ADD	X0, X0, #1

  (988) 0x49b58c SUBS	X1, X1, #1

  (988) 0x49b590 LDR	D2, [X11, X2,LSL #3]

  (988) 0x49b594 FMSUB	D0, D1, D2, D0

  (988) 0x49b598 B.NE	49b580

(986) 0x49b59c ORN	X18, XZR, X18

(986) 0x49b5a0 ADD	X18, X16, X18

(986) 0x49b5a4 CMP	X18, #3

(986) 0x49b5a8 B.CC	49b538

(986) 0x49b5ac B	49b5c4

(986) 0x49b5b0 ORR	X0, XZR, X18

(986) 0x49b5b4 ORN	X18, XZR, X18

(986) 0x49b5b8 ADD	X18, X16, X18

(986) 0x49b5bc CMP	X18, #3

(986) 0x49b5c0 B.CC	49b538

(986) 0x49b5c4 UBFM	X1, X0, #61, #60

(986) 0x49b5c8 SUB	X18, X16, X0

(986) 0x49b5cc ADD	X0, X14, X1

(986) 0x49b5d0 ADD	X1, X15, X1

(986) 0x49b5d4 HINT	#0

(986) 0x49b5d8 HINT	#0

(986) 0x49b5dc HINT	#0

  (987) 0x49b5e0 LDP	X2, X3, [X1, #1008]

  (987) 0x49b5e4 LDP	D2, D3, [X0, #1008]

  (987) 0x49b5e8 SUBS	X18, X18, #4

  (987) 0x49b5ec LDR	D1, [X11, X2,LSL #3]

  (987) 0x49b5f0 FMSUB	D0, D2, D1, D0

  (987) 0x49b5f4 LDR	D1, [X11, X3,LSL #3]

  (987) 0x49b5f8 FMSUB	D0, D3, D1, D0

  (987) 0x49b5fc LDP	X2, X3, [X1], #32

  (987) 0x49b600 LDR	D2, [X11, X2,LSL #3]

  (987) 0x49b604 LDP	D1, D3, [X0], #32

  (987) 0x49b608 FMSUB	D0, D1, D2, D0

  (987) 0x49b60c LDR	D1, [X11, X3,LSL #3]

  (987) 0x49b610 FMSUB	D0, D3, D1, D0

  (987) 0x49b614 B.NE	49b5e0

(986) 0x49b618 B	49b538

0x49b61c CMP	X20, X19

0x49b620 B.GE	49b83c

0x49b624 LDR	X9, [X24]

0x49b628 LDR	X10, [X23]

0x49b62c LDR	X12, [X26]

0x49b630 ADD	X14, X10, #16

0x49b634 LDR	X8, [X8]

0x49b638 LDR	X11, [X27]

0x49b63c LDR	X13, [X25]

0x49b640 LDR	X16, [X9, X20,LSL #3]

0x49b644 ADD	X15, X12, #16

0x49b648 B	49b664

(989) 0x49b64c LDR	D1, [X21]

(989) 0x49b650 CMP	X17, X19

(989) 0x49b654 FMUL	D0, D0, D1

(989) 0x49b658 STR	D0, [X13, X20,LSL #3]

(989) 0x49b65c ORR	X20, XZR, X17

(989) 0x49b660 B.EQ	49b83c

(989) 0x49b664 LDR	D0, [X8, X20,LSL #3]

(989) 0x49b668 ADD	X17, X20, #1

(989) 0x49b66c ORR	X18, XZR, X16

(989) 0x49b670 LDR	X16, [X9, X17,LSL #3]

(989) 0x49b674 CMP	X16, X18

(989) 0x49b678 B.LE	49b64c

(989) 0x49b67c SUB	W0, W16, W18

(989) 0x49b680 ANDS	X1, X0, #4160

(989) 0x49b684 B.EQ	49b6bc

(989) 0x49b688 ORR	X0, XZR, X18

  (991) 0x49b68c LDR	X2, [X12, X0,LSL #3]

  (991) 0x49b690 LDR	D1, [X10, X0,LSL #3]

  (991) 0x49b694 ADD	X0, X0, #1

  (991) 0x49b698 SUBS	X1, X1, #1

  (991) 0x49b69c LDR	D2, [X11, X2,LSL #3]

  (991) 0x49b6a0 FMADD	D0, D1, D2, D0

  (991) 0x49b6a4 B.NE	49b68c

(989) 0x49b6a8 ORN	X18, XZR, X18

(989) 0x49b6ac ADD	X18, X16, X18

(989) 0x49b6b0 CMP	X18, #3

(989) 0x49b6b4 B.CC	49b64c

(989) 0x49b6b8 B	49b6d0

(989) 0x49b6bc ORR	X0, XZR, X18

(989) 0x49b6c0 ORN	X18, XZR, X18

(989) 0x49b6c4 ADD	X18, X16, X18

(989) 0x49b6c8 CMP	X18, #3

(989) 0x49b6cc B.CC	49b64c

(989) 0x49b6d0 UBFM	X1, X0, #61, #60

(989) 0x49b6d4 SUB	X18, X16, X0

(989) 0x49b6d8 ADD	X0, X14, X1

(989) 0x49b6dc ADD	X1, X15, X1

  (990) 0x49b6e0 LDP	X2, X3, [X1, #1008]

  (990) 0x49b6e4 LDP	D2, D3, [X0, #1008]

  (990) 0x49b6e8 SUBS	X18, X18, #4

  (990) 0x49b6ec LDR	D1, [X11, X2,LSL #3]

  (990) 0x49b6f0 FMADD	D0, D2, D1, D0

  (990) 0x49b6f4 LDR	D1, [X11, X3,LSL #3]

  (990) 0x49b6f8 FMADD	D0, D3, D1, D0

  (990) 0x49b6fc LDP	X2, X3, [X1], #32

  (990) 0x49b700 LDR	D2, [X11, X2,LSL #3]

  (990) 0x49b704 LDP	D1, D3, [X0], #32

  (990) 0x49b708 FMADD	D0, D1, D2, D0

  (990) 0x49b70c LDR	D1, [X11, X3,LSL #3]

  (990) 0x49b710 FMADD	D0, D3, D1, D0

  (990) 0x49b714 B.NE	49b6e0

(989) 0x49b718 B	49b64c

0x49b71c CMP	X20, X19

0x49b720 B.GE	49b83c

0x49b724 LDR	X9, [X24]

0x49b728 LDR	X10, [X23]

0x49b72c LDR	X12, [X26]

0x49b730 ADD	X14, X10, #16

0x49b734 LDR	X8, [X8]

0x49b738 LDR	X11, [X27]

0x49b73c LDR	X13, [X25]

0x49b740 LDR	X16, [X9, X20,LSL #3]

0x49b744 ADD	X15, X12, #16

0x49b748 B	49b764

(983) 0x49b74c LDR	D1, [X21]

(983) 0x49b750 CMP	X17, X19

(983) 0x49b754 FMUL	D0, D0, D1

(983) 0x49b758 STR	D0, [X13, X20,LSL #3]

(983) 0x49b75c ORR	X20, XZR, X17

(983) 0x49b760 B.EQ	49b83c

(983) 0x49b764 LDR	D0, [X8, X20,LSL #3]

(983) 0x49b768 LDR	D1, [X22]

(983) 0x49b76c ADD	X17, X20, #1

(983) 0x49b770 ORR	X18, XZR, X16

(983) 0x49b774 LDR	X16, [X9, X17,LSL #3]

(983) 0x49b778 CMP	X16, X18

(983) 0x49b77c FMUL	D0, D0, D1

(983) 0x49b780 B.LE	49b74c

(983) 0x49b784 SUB	W0, W16, W18

(983) 0x49b788 ANDS	X1, X0, #4160

(983) 0x49b78c B.EQ	49b7d0

(983) 0x49b790 ORR	X0, XZR, X18

(983) 0x49b794 HINT	#0

(983) 0x49b798 HINT	#0

(983) 0x49b79c HINT	#0

  (985) 0x49b7a0 LDR	X2, [X12, X0,LSL #3]

  (985) 0x49b7a4 LDR	D1, [X10, X0,LSL #3]

  (985) 0x49b7a8 ADD	X0, X0, #1

  (985) 0x49b7ac SUBS	X1, X1, #1

  (985) 0x49b7b0 LDR	D2, [X11, X2,LSL #3]

  (985) 0x49b7b4 FMADD	D0, D1, D2, D0

  (985) 0x49b7b8 B.NE	49b7a0

(983) 0x49b7bc ORN	X18, XZR, X18

(983) 0x49b7c0 ADD	X18, X16, X18

(983) 0x49b7c4 CMP	X18, #3

(983) 0x49b7c8 B.CC	49b74c

(983) 0x49b7cc B	49b7e4

(983) 0x49b7d0 ORR	X0, XZR, X18

(983) 0x49b7d4 ORN	X18, XZR, X18

(983) 0x49b7d8 ADD	X18, X16, X18

(983) 0x49b7dc CMP	X18, #3

(983) 0x49b7e0 B.CC	49b74c

(983) 0x49b7e4 UBFM	X1, X0, #61, #60

(983) 0x49b7e8 SUB	X18, X16, X0

(983) 0x49b7ec ADD	X0, X14, X1

(983) 0x49b7f0 ADD	X1, X15, X1

(983) 0x49b7f4 HINT	#0

(983) 0x49b7f8 HINT	#0

(983) 0x49b7fc HINT	#0

  (984) 0x49b800 LDP	X2, X3, [X1, #1008]

  (984) 0x49b804 LDP	D2, D3, [X0, #1008]

  (984) 0x49b808 SUBS	X18, X18, #4

  (984) 0x49b80c LDR	D1, [X11, X2,LSL #3]

  (984) 0x49b810 FMADD	D0, D2, D1, D0

  (984) 0x49b814 LDR	D1, [X11, X3,LSL #3]

  (984) 0x49b818 FMADD	D0, D3, D1, D0

  (984) 0x49b81c LDP	X2, X3, [X1], #32

  (984) 0x49b820 LDR	D2, [X11, X2,LSL #3]

  (984) 0x49b824 LDP	D1, D3, [X0], #32

  (984) 0x49b828 FMADD	D0, D1, D2, D0

  (984) 0x49b82c LDR	D1, [X11, X3,LSL #3]

  (984) 0x49b830 FMADD	D0, D3, D1, D0

  (984) 0x49b834 B.NE	49b800

(983) 0x49b838 B	49b74c

0x49b83c LDP	X20, X19, [SP, #80]

0x49b840 LDP	X22, X21, [SP, #64]

0x49b844 LDP	X24, X23, [SP, #48]

0x49b848 LDP	X26, X25, [SP, #32]

0x49b84c LDR	X27, [SP, #16]

0x49b850 LDP	X29, X30, [SP], #96

0x49b854 RET

0x49b858 HINT	#0

0x49b85c HINT	#0

Coverage (%)	Name	Source Location	Module

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	csr_matvec.c:243-404
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:243-365,371-404.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 37.00 to 5.67 cycles (6.53x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 37.00 to 4.83 cycles (7.66x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 37.00 to 4.00 cycles (9.25x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 888 bytes. The binary function is storing 88 bytes.

General properties

nb instructions	278
loop length	1112
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

32.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	25.00	25.00	21.75	21.75	21.75	21.75	12.00	2.75	2.75	2.50	37.00	37.00	37.00	3.00	3.00
cycles	25.00	25.00	21.75	21.75	21.75	21.75	12.00	2.75	2.75	2.50	37.00	37.00	37.00	3.00	3.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	32.38
Overall L1	37.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 37.00 cycles. At this rate:

25% of peak load performance is reached (24.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.38 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 49a9a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #928]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X23, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X24, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4997d0 <hypre_CSRMatrixGetLoadBalancedPartitionBegin>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 499860 <hypre_CSRMatrixGetLoadBalancedPartitionEnd>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X20, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 49aa2c <.omp_outlined..18+0x8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X8, <4df9f4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X1, <4b69f8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, #675	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, <4b7a00>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #3881	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8, #3824]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4a2830 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4b8a18>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1582	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #248	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a5070 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
TBNZ X20, #63, 49aa3c <.omp_outlined..18+0x9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X20, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 49aa78 <.omp_outlined..18+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X8, <4dfa3c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X1, <4b6a40>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, #675	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, <4b8a48>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #3187	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8, #3824]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4a2830 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4b8a60>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1582	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #249	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a5070 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X26, X25, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X27, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
TBNZ X19, #63, 49abbc <.omp_outlined..18+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X19, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 49abbc <.omp_outlined..18+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D1, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMP D1, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 49ac00 <.omp_outlined..18+0x260>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMOV D1, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 49ad3c <.omp_outlined..18+0x39c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 49b83c <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X9, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X8, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 49aaf0 <.omp_outlined..18+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
ADRP X8, <4dfbbc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X1, <4b6bc0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, #675	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, <4b8bc8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #3221	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8, #3824]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4a2830 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4b8be0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1582	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #250	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a5070 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D1, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMP D1, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.EQ 49aa98 <.omp_outlined..18+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FMOV D0, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMP D1, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 49ae5c <.omp_outlined..18+0x4bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMOV D1, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 49af7c <.omp_outlined..18+0x5dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 49b83c <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 49ac70 <.omp_outlined..18+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
FMOV D1, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 49b09c <.omp_outlined..18+0x6fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 49b83c <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X9, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X8, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 49ad90 <.omp_outlined..18+0x3f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
LDR D0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMOV D2, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMP D1, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 49b19c <.omp_outlined..18+0x7fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FCMP D0, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 49b2bc <.omp_outlined..18+0x91c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 49b83c <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 49aeb4 <.omp_outlined..18+0x514>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMOV D1, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 49b3dc <.omp_outlined..18+0xa3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 49b83c <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 49afd0 <.omp_outlined..18+0x630>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 49b83c <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X9, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X8, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 49b0e0 <.omp_outlined..18+0x740>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FCMP D0, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 49b4fc <.omp_outlined..18+0xb5c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 49b83c <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 49b1f0 <.omp_outlined..18+0x850>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
FMOV D1, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 49b61c <.omp_outlined..18+0xc7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 49b83c <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 49b310 <.omp_outlined..18+0x970>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 49b83c <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 49b424 <.omp_outlined..18+0xa84>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMOV D1, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 49b71c <.omp_outlined..18+0xd7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 49b83c <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 49b548 <.omp_outlined..18+0xba8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 49b83c <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 49b664 <.omp_outlined..18+0xcc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 49b83c <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 49b764 <.omp_outlined..18+0xdc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Source file and lines	csr_matvec.c:243-404
Module	exec

The function is defined in /home/hbollore/qaas-runs/171-233-5044/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:243-365,371-404.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 37.00 to 5.67 cycles (6.53x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 37.00 to 4.00 cycles (9.25x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 888 bytes. The binary function is storing 88 bytes.

General properties

nb instructions	278
loop length	1112
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

32.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	25.00	25.00	21.75	21.75	21.75	21.75	12.00	2.75	2.75	2.50	37.00	37.00	37.00	3.00	3.00
cycles	25.00	25.00	21.75	21.75	21.75	21.75	12.00	2.75	2.75	2.50	37.00	37.00	37.00	3.00	3.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	32.38
Overall L1	37.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 37.00 cycles. At this rate:

25% of peak load performance is reached (24.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.38 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 49a9a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #928]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X23, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X24, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X21, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X22, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X25, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4997d0 <hypre_CSRMatrixGetLoadBalancedPartitionBegin>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 499860 <hypre_CSRMatrixGetLoadBalancedPartitionEnd>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X20, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 49aa2c <.omp_outlined..18+0x8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X8, <4df9f4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X1, <4b69f8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, #675	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, <4b7a00>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #3881	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8, #3824]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4a2830 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4b8a18>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1582	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #248	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a5070 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
TBNZ X20, #63, 49aa3c <.omp_outlined..18+0x9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X20, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 49aa78 <.omp_outlined..18+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADRP X8, <4dfa3c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X1, <4b6a40>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, #675	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, <4b8a48>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #3187	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8, #3824]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4a2830 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4b8a60>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1582	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #249	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a5070 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X26, X25, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X27, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
TBNZ X19, #63, 49abbc <.omp_outlined..18+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X19, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 49abbc <.omp_outlined..18+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D1, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMP D1, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 49ac00 <.omp_outlined..18+0x260>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMOV D1, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 49ad3c <.omp_outlined..18+0x39c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 49b83c <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X9, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X8, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 49aaf0 <.omp_outlined..18+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
ADRP X8, <4dfbbc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X1, <4b6bc0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, #675	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X2, <4b8bc8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #3221	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8, #3824]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 4a2830 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X0, <4b8be0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #1582	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #250	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 4a5070 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D1, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FCMP D1, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.EQ 49aa98 <.omp_outlined..18+0xf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FMOV D0, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMP D1, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 49ae5c <.omp_outlined..18+0x4bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMOV D1, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 49af7c <.omp_outlined..18+0x5dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 49b83c <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 49ac70 <.omp_outlined..18+0x2d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
HINT #0
FMOV D1, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 49b09c <.omp_outlined..18+0x6fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 49b83c <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X9, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X8, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 49ad90 <.omp_outlined..18+0x3f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
LDR D0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMOV D2, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMP D1, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 49b19c <.omp_outlined..18+0x7fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FCMP D0, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 49b2bc <.omp_outlined..18+0x91c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 49b83c <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 49aeb4 <.omp_outlined..18+0x514>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMOV D1, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 49b3dc <.omp_outlined..18+0xa3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 49b83c <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 49afd0 <.omp_outlined..18+0x630>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 49b83c <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X9, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X9, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X10, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X8, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 49b0e0 <.omp_outlined..18+0x740>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FCMP D0, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 49b4fc <.omp_outlined..18+0xb5c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 49b83c <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 49b1f0 <.omp_outlined..18+0x850>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
HINT #0
FMOV D1, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 49b61c <.omp_outlined..18+0xc7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 49b83c <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 49b310 <.omp_outlined..18+0x970>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 49b83c <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 49b424 <.omp_outlined..18+0xa84>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMOV D1, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
B.NE 49b71c <.omp_outlined..18+0xd7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 49b83c <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 49b548 <.omp_outlined..18+0xba8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 49b83c <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 49b664 <.omp_outlined..18+0xcc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 49b83c <.omp_outlined..18+0xe9c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X13, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [X9, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 49b764 <.omp_outlined..18+0xdc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X19, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X21, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X23, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X25, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼.omp_outlined..18#0x49a9a0–	15.72	5.94
▼Loop 992 - csr_matvec.c:334-341 - exec–	0.28	0.09
○Loop 994 - csr_matvec.c:337-339 - exec	0.42	0.14
○Loop 993 - csr_matvec.c:337-339 - exec	0.12	0.04
▼Loop 977 - csr_matvec.c:256-263 - exec–	0.17	0.05
○Loop 978 - csr_matvec.c:259-261 - exec	6.09	1.99
○Loop 979 - csr_matvec.c:259-261 - exec	0.8	0.26
▼Loop 968 - csr_matvec.c:307-314 - exec–	0.16	0.05
○Loop 969 - csr_matvec.c:310-312 - exec	6.82	2.23
○Loop 970 - csr_matvec.c:310-312 - exec	0.87	0.29
▼Loop 986 - csr_matvec.c:385-392 - exec–	0	0
○Loop 987 - csr_matvec.c:388-390 - exec	0	0
○Loop 988 - csr_matvec.c:388-390 - exec	0	0
▼Loop 974 - csr_matvec.c:295-302 - exec–	0	0
○Loop 976 - csr_matvec.c:298-300 - exec	0	0
○Loop 975 - csr_matvec.c:298-300 - exec	0	0
▼Loop 995 - csr_matvec.c:319-326 - exec–	0	0
○Loop 997 - csr_matvec.c:322-324 - exec	0	0
○Loop 996 - csr_matvec.c:322-324 - exec	0	0
▼Loop 989 - csr_matvec.c:358-365 - exec–	0	0
○Loop 990 - csr_matvec.c:361-363 - exec	0	0
○Loop 991 - csr_matvec.c:361-363 - exec	0	0
▼Loop 962 - csr_matvec.c:346-353 - exec–	0	0
○Loop 964 - csr_matvec.c:349-351 - exec	0	0
○Loop 963 - csr_matvec.c:349-351 - exec	0	0
▼Loop 983 - csr_matvec.c:397-404 - exec–	0	0
○Loop 985 - csr_matvec.c:400-402 - exec	0	0
○Loop 984 - csr_matvec.c:400-402 - exec	0	0
▼Loop 971 - csr_matvec.c:268-275 - exec–	0	0
○Loop 973 - csr_matvec.c:271-273 - exec	0	0
○Loop 972 - csr_matvec.c:271-273 - exec	0	0
▼Loop 965 - csr_matvec.c:373-380 - exec–	0	0
○Loop 966 - csr_matvec.c:376-378 - exec	0	0
○Loop 967 - csr_matvec.c:376-378 - exec	0	0
▼Loop 980 - csr_matvec.c:280-287 - exec–	0	0
○Loop 981 - csr_matvec.c:283-285 - exec	0	0
○Loop 982 - csr_matvec.c:283-285 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code